ICS91305YMI-T [IDT]
PLL Based Clock Driver, 91305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8;
| 型号： | ICS91305YMI-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 91305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS91305I
Integrated
Circuit
Systems, Inc.
High Performance Communication Buffer
General Description
Features
The ICS91305I is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology
to align, in both phase and frequency, the REF input with
theCLKOUTsignal. Itisdesignedtodistributehighspeed
clocks in communication systems operating at speeds
from 10 to 133 MHz.
•
•
•
•
Zero input - output delay
Frequency range 10 - 133 MHz (3.3V)
5V tolerant input REF
High loop filter bandwidth ideal for Spread
Spectrum applications.
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 pin 150 mil SOIC & 173 mil
TSSOP packages
•
•
•
•
ICS91305I is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to
theinputofthePLL. Sincetheskewbetweentheinputand
outputislessthan+/-350pS, thepartactsasazerodelay
buffer.
•
•
3.3V ±10% operation
Supports industrial temperature range -40°C to
85°C
The ICS91305I comes in an eight pin 150 mil SOIC
package. It has five output clocks. In the absence of REF
input, will be in the power down mode. In this mode, the
PLL is turned off and the output buffers are pulled low.
Powerdownmodeprovidesthelowestpowerconsumption
for a standby condition.
Block Diagram
Pin Configuration
REF
CLK2
CLK1
GND
1
2
3
4
8
7
6
5
CLKOUT
CLK4
VDD
CLK3
8 pin SOIC & TSSOP
0691E—08/20/04
ICS91305I
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
IN
DESCRIPTION
Input reference frequency, 5V tolerant input.
Buffered clock output
1
2
3
4
5
6
7
8
REF2
CLK23
CLK13
GND
OUT
OUT
PWR
OUT
PWR
OUT
OUT
Buffered clock output
Ground
CLK33
Buffered clock output
VDD
Power Supply (3.3V)
CLK43
CLKOUT3
Buffered clock output
Buffered clock output. Internal feedback on this pin
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. Weakpull-down
3. Weak pull-down on all outputs
0691E—08/20/04
2
ICS91305I
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs (Except REF) . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V
Logic Input REF . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to GND + 5.5 V
Ambient OperatingTemperature . . . . . . . . . . -40°C to +85°C
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.6V, TA = -40°C to +85°C unless otherwise stated
DC Chara cteris tic s
P
A
R
A
ME
In put Low oltage
In put igh oltage
In put Low ur ent
In put igh ur ent
T
E
R
S
Y
MBOL
T
E
S
T
C
O
N
D
ITION
S
MIN
T
Y
P
MA
X
UNITS
V
V
I
L
0.8
V
H
V
V
I
H
2.0
V
C
r
I
I
LI
V
V
NI
NI
=
0V
19
100.0
250.0
µA
µA
H
C
r
I
H
=V
D
D
0.10
Output Low
V
OL
1
I
O
L
=
12mA
12mA
MH
0.25
0.4
V
Voltage
Output
H
1
igh
V
OH
V
oltage
ower
uppl
uppl
I
O
H
=
F
-
2.4
2.9
0.3
V
µA
mA
P
D
ow
n
I
D
D
R
E
=
0
z
100.0
80.0
S
y
C
ur
r
ent
S
y
C
urr
ent
I
D
D
U
n
load ed oututs at 66. 66 MH
nputs at or
z
30.0
S
E
L
i
V
D
D
G
N
D
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. All Skew specifications are mesured with a 50Ω transmission line, load teminated with 50Ω to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
0691E—08/20/04
3
ICS91305I
Switching Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
100.00
(10)
7.5
(133)
ns
(MHz)
Output period
t1
With CL=30pF
100.00
(10)
7.5
(133)
ns
(MHz)
Input period
Duty Cycle1
Duty Cycle1
t1
With CL=30pF
Dt1
Dt2
Measured at 1.4V; CL=30pF
40.0
45
50
50
60
55
%
%
Measured at VDD/2 Fout
<66.6MHz
Measured between 0.8V and 2.0V:
CL=30pF
Rise Time1
Fall Time1
tr1
tf1
1.2
1.2
1.5
1.5
ns
ns
Measured between 2.0V and 0.8V;
CL=30pF
Delay, REF Rising
Edge to CLKOUT
Rising Edge1, 2
Dr1
Measured at 1.4V
0
±350
ps
Output to Output
Skew1
All outputs equally loaded,
CL=20pF
Tskew
Tdsk-Tdsk
Tcyc-Tcyc
tLOCK
250
700
200
1.0
ps
ps
ps
ms
ps
ps
Device to Device
Skew1
Measured at VDD/2 on the
CLKOUT pins of devices
0
Cycle to Cycle
Jitter1
Measured at 66.66 MHz, loaded
outputs
Stable power supply, valid clock
presented on REF pin
PLL Lock Time1
Jitter; Absolute
Jitter1
@ 10,000 cycles
CL = 30pF
Tjabs
-200
70
14
200
60
@ 10,000 cycles
CL = 30pF
Jitter; 1 - Sigma1
Tj1s
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. REF input has a threshold voltage of 1.4V
3. All parameters expected with loaded outputs
0691E—08/20/04
4
ICS91305I
Output to Output Skew
The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL.Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it;and if the CLK(1-4) is more loaded
than CLKOUT, CLK(1-4) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause
them to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loadedEqually
REF input and CLK(1-4)
outputsloadedequally,with
CLKOUT loaded More.
REF input and CLK(1_4)
outputsloadedequally,with
CLKOUT loaded Less.
Timing diagrams with different loading configurations
0691E—08/20/04
5
ICS91305I
SYMBOL
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
C
N
MIN
1.35
0.10
0.33
0.19
MAX
1.75
0.25
0.51
0.25
MIN
.0532
.0040
.013
MAX
.0688
.0098
.020
L
A
A1
B
C
D
E
e
INDEX
AREA
H
E
.0075
.0098
SEE VARIATIONS
SEE VARIATIONS
3.80
4.0
.1497
.1574
1.27 BASIC
0.050 BASIC
h xx 4455°°
1
22
H
h
5.80
0.25
0.40
6.20
0.50
1.27
.2284
.010
.016
.2440
.020
.050
D
α
A
L
SEE VARIATIONS
SEE VARIATIONS
N
α
A1
0°
8°
0°
8°
SEATING
PLANE
e
B
VARIATIONS
D mm.
D (inch)
.10 ((..000044))
N
8
MIN
4.80
MAX
5.00
MIN
MAX
150 mil (Narrow Body) SOIC
.1890
.1968
Ordering Information
ICS91305yMILF-T
Example:
ICS XXXX y M LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
M = SOIC
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0691E—08/20/04
6
ICS91305I
4.40 mm. Body, 0.65 mm. Pitch TSSOP
(173 mil) (25.6 mil)
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
c
N
SYMBOL
MIN
--
0.05
0.80
0.19
0.09
MAX
1.20
0.15
1.05
0.30
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.012
.008
A
A1
A2
b
L
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
E1
e
L
N
a
4.30
0.65 BASIC
0.45
SEE VARIATIONS
0°
--
4.50
.169
.177
0.0256 BASIC
.030
SEE VARIATIONS
1
2
0.75
.018
α
D
8°
0.10
0°
--
8°
.004
aaa
VARIATIONS
A
D mm.
D (inch)
A2
N
8
MIN
2.90
MAX
3.10
MIN
.114
MAX
.122
A1
- C -
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
e
SEATING
PLANE
b
aaa
C
Ordering Information
ICS91305yGILF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0691E—08/20/04
7
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