ICS9248YF-143-T [IDT]
Processor Specific Clock Generator, 133.37MHz, PDSO48, 0.300 INCH, SSOP-48;
| 型号： | ICS9248YF-143-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 133.37MHz, PDSO48, 0.300 INCH, SSOP-48 光电二极管 |
| 文件： | 总16页 (文件大小：506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Incꢀ
ICS9248-143
Frequency Generator & Integrated Buffers for PENTIUM II/IIITM
& K6
RecommendedApplication:
Pin Configuration
440BX, MX,VIAApollo Pro 133,Apollo Pro Media
or MVP4 style chip set, for Note book applications'
OutputFeatures:
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDREF
*SPREAD/REF0
GNDREF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
REF1/FS2*
VDDLCPU
CPUCLK_F
CPUCLK0
GNDLCPU
CPUCLK1
CPUCLK2
CLK_STOP#
GNDSDR
SDRAM_F
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GNDSDR
SDRAM4
4-CPUs@2'5V/3'3V
including 1 free running CPUCLK_F
X1
X2
VDDPCI
9 - SDRAM @ 3'3V
7 - PCI @ 3'3V, including 1 free running PCICLK_F
1-PCIEarly@3'3V
1-48MHz, @3'3Vfixed'
1-24/48MHz @3'3V
*CPU2.5_3.3#/PCICLK_F
*FS3/PCICLK0
GNDPCI
*SEL24_48#/PCICLK1
*SELPCIE_6#/PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GNDPCI
PCICLK5
2-REF@3'3V,14'318MHz'
Features:
Up to 137MHz frequency support
97MHz to support high-end AMD processor'
PCICLK6/PCICLK_E
VDDCOR
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
PCI_STOP#
*PD#
Support power management: CLK, PCI, stop and Power
down Mode from I2C programming'
GND48
SDATA
SCLK
48MHz/FS0*
24_48MHz/FS1*
Spread spectrum for EMI control
(±'25% & 0 to -0'5% down spread)'
Uses external 14'318MHz crystal
FS pins for frequency select
48-Pin SSOP and TSSOP
* Internal Pull-up Resistor of 120K to VDD
KeySpecifications:
CPU Output Jitter @ 2'5V: <300ps
CPU Output Jitter @ 3'3V: <250ps
PCI Output Jitter @ 3'3V: <250ps
CPUOutputSkew@2'5V:<175ps
CPUOutputSkew@3'3V:<175ps
PCIOutputSkew@3'3V:<500ps
PCI Early to PCI Skew @ 3'3V: typ = 3ns
Functionality
CPU
(MHz)
66.67
100.00
100.30
133.33
105.00
133.37
137.00
75.00
100.00
95.00
97.00
133.33
90.00
96.22
PCI
(MHz)
33.33
33.33
33.43
33.33
35.00
33.34
34.25
37.50
33.33
31.67
32.33
33.33
30.00
32.07
33.41
30.50
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Block Diagram
PLL2
48MHz
24_48MHz
REF[1:0]
/ 2
X1
X2
XTAL
OSC
2
BUFFER IN
CPUCLK_F
PLL1
Spread
Spectrum
STOP
STOP
CPUCLK [2:0]
3
4
FS(0:3)
SDRAM [7:0]
SDRAM_F
LATCH
POR
8
SEL24_48#
4
PCI
CLK_STOP#
CLOCK
DIVDER
STOP
PCICLK [5:0]
PCICLK_F
PCICLK_E
6
PCI_STOP#
CPU2.5_3.3#
Control
Logic
66.82
91.50
SDATA
SCLK
PD#
Config.
Reg.
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9248-143 Rev C 7/26/00
information being relied upon by the customer is current and accurate.
ICS9248-143
Pin Descriptions
PIN
PIN NAME
TYPE
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
Active High Spread Spectrum enable input. Power-up default is "High", spreading is "on"
14.318 Mhz reference clock.This REF output is the STRONGER buffer for ISA BUS loads
NUMBER
1
2
VDDREF
SPREAD1,2
REF0
PWR
IN
OUT
20
PCI_STOP#
IN
Halts PCICLK clocks at logic 0 level, when input low (In mobile mode, MODE=0)
3, 9, 16,
33, 40, 44
GND
PWR
Ground
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
4
X1
IN
5
6,14
X2
OUT
PWR
IN
Crystal output, nominally 14.318MHz.
VDDPCI
CPU2.5_3.3#1,2
PCICLK_F
FS31,2
Supply for PCICLK_F and PCICLK nominal 3.3V
Indicates whether VDDLCPU is 2.5 or 3.3V. High=2.5V CPU, LOW=3.3V CPU. Latched Input.
Free running PCI clock not affected by PCI_STOP# for power management.
Frequency select pin. Latched Input.
7
8
OUT
IN
PCICLK0
OUT
PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early)
SEL24_48#1,2
PCICLK1
IN
OUT
Selects either 24 or 48MHz when Low =48 MHz
PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early)
10
SELPCIE_6#1,2
PCICLK2
IN
PCI Early or normal PCI select latch input. (for pin 18 power-up default is "High" early PCICLK.)
PCICLK clock output.
11
OUT
OUT
17, 13, 12
PCICLK (5:3)
PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early)
15
18
19
BUFFER IN
PCICLK6/PCICLK_E
VDDCOR
IN
OUT
PWR
Input to Fanout Buffers for SDRAM outputs.
PCI clock output or early PCI clock output selectable by SELPCIE_6#
Power pin for the PLL core. 3.3V
Asynchronous active low input pin used to power down the device into a low power state. The
internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power
down will not be greater than 4ms.
21
PD#1
IN
22
28, 29, 31, 32,
34, 35, 37, 38
30, 36
GND48
PWR
OUT
Ground pin for the 24 & 48MHz output buffers & fixed PLL core.
SDRAM (7:0)
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset).
VDDSDR
SDATA
SCLK
PWR
IN
IN
Supply for SDRAM and CPU PLL Core, nominal 3.3V.
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
23
24
24_48MHz
OUT
24MHz or 48MHz output clock selectable by pin 10
25
26
FS11, 2
48MHz
FS01, 2
IN
OUT
IN
Frequency select pin. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
27
VDD48
PWR
OUT
IN
OUT
OUT
PWR
OUT
IN
Power for 24 & 48MHz output buffers and fixed PLL core.
Free running SDRAM clock output. Not affected by CPU_STOP#
This asynchronous input halts CPUCLK, & SDRAM at logic "0" level when driven low.
CPU clock outputs, powered by VDDLCPU
Free running CPU clock. Not affected by the CPU_STOP#
Supply for CPU clocks 2.5V
39
41
SDRAM_F
CLK_STOP#
CPUCLK (2:0)
CPUCLK_F
VDDLCPU
REF1
42, 43, 45
46
47
14.318 MHz reference clock.
48
FS21, 2
Frequency select pin. Latched Input
Notes:
1: Internal Pull-up Resistor of 120K to 3ꢀ3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-resetꢀ Use 10Kohm resistor
to program logic Hi to VDD or GND for logic lowꢀ
2
ICS9248-143
General Description
The ICS9248-143 is the single chip clock solution for Notebook designs using thE 440BX, MX, VIAApollo Pro 133,Apollo Pro
Media or MVP4 style chip set' It provides all necessary clock signals for such a system'
Spread spectrum may be enabled through I2C programming' Spread spectrum typically reduces system EMI by 8dB to 10dB'
This simplifies EMI qualification without resorting to board design iterations or costly shielding' The ICS9248-143 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations'
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
0 - ±0.25% Spread Spectrum Modulation, Center Spread
1 - 0 to -0.5% Down Spread
Bit 7
1
CPUCLK
(MHz)
PCICLK
(MHz)
Bit [2, 6:4]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
66.67
100.00
100.30
133.33
105.00
133.37
137.00
75.00
33.33
33.33
33.43
33.33
35.00
33.34
34.25
37.50
33.33
31.67
32.33
33.33
30.00
32.07
33.41
30.50
Note1
Bit
[2, 6:4]
100.00
95.00
97.00
133.33
90.00
96.22
66.82
91.50
0 - Frequency and Spread Spectrum are selected by hardware
select, latched inputs
1 - Frequency is selected by Bit [2, 6:4]; Spread Spectrum is
selected by bit 1
Bit 3
0
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Bit 1
Bit 0
1
0
Notes:
1, Default at Power-up will be for latched logic inputs to define frequencyꢀ Bit [2, 6:4] are default to 0011ꢀ
2, PWD = Power-Up Default
3
ICS9248-143
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
-
46
-
PWD
Description
(Reserved)
CPUCLK_F (Act/Inact)
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
-
(Reserved)
39
42
43
45
SDRAM_F (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
7
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
PCICLK_F (Act/Inact)
PCICLK6 (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
18
17
13
12
11
10
8
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
1
1
1
1
1
1
1
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM7 (Active/Inactive)
SDRAM6 (Active/Inactive)
SDRAM5 (Active/Inactive)
SDRAM4 (Active/Inactive)
-
28
29
31
32
Notes:
1' Inactive means outputs are held LOW and are disabled from switching'
2' Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions'
4
ICS9248-143
Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
PWD
1
1
X
1
X
1
Description
(Reserved)
(Reserved)
(SEL24_48)#
(Reserved)
Latched FS1#
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
X
1
Latched FS3#
(Reserved)
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Bit
Pin #
34
35
37
38
26
25
48
2
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
48MHz (Act/Inact)
24MHz (Act/Inact)
REF1 (Act/Inact)
REF0 (Act/Inact)
Notes:
1' Inactive means outputs are held LOW and are disabled from switching'
2' Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions'
5
ICS9248-143
Absolute Maximum Ratings
Supply Voltage ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 5'5V
Logic Inputs ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' GND 0'5 V to VDD +0'5 V
Ambient Operating Temperature ' ' ' ' ' ' ' ' ' ' ' ' 0°C to +70°C
Case Temperature ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 115°C
Storage Temperature ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device'These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied' Exposure to absolute maximum rating conditions for extended periods may affect
product reliability'
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
0.8
V
V
VIL
VSS-0.3
CL = 0 pF; Select @ 66MHz
CL = 0 pF; Select @ 100MHz
CL = 0 pF; Select @ 133MHz
90
150
Operating Supply
Current
IDD3.3OP
mA
114
139
170
180
IDDP D
Fi
µA
Powerdown Current
Input Frequency
Input Capacitance1
CL = 0 pF; Input address VDD or GND
VDD = 3.3 V
600
16
12
27
MHz
CIN
Logic Inputs
X1 & X2 pins
5
pF
pF
CINX
45
Clk Stabilization1
Skew1
TSTAB
From VDD = 3.3 V to 1% target Freq.
5.5
4
ms
ns
tCP U-P CI1 VT = 1.5 V
1
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
10
MAX UNITS
15
CL = 0 pF; Select @ 66.8 MHz
CL = 0 pF; Select @ 100 MHz
CL = 0 pF; Select @ 133 MHz
Operating SupplyCurrent
IDDL2.5
mA
13
18
25
10
22
IDDLP D
Powerdown Current
Skew1
A
µ
CL = 0 pF; Input address VDD or GND
VT = 1.5 V; VTL = 1.25 V
tCP U-P CI2
1
3
4
ns
1Guaranteed by design, not 100% tested in production.
6
ICS9248-143
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF
PARAMETER
SYMBOL
VOH2A
VOL2A
IOH2A
CONDITIONS
MIN
2.4
TYP
2.85
0.31
-45
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -20 mA
IOL = 12 mA
VOH = 2.0 V
VOL = 0.8 V
0.4
-27
V
mA
mA
IOL2A
22
45
29
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
tr2A
tf2 A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.4
2
ns
ns
%
2
dt2A
52.4
80
55
175
250
tsk2A
VT = 1.5 V
ps
ps
Jitter, Cycle-to-cycle1
tjcyc-cyc2A VT = 1.5 V
200
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 20 pF
PARAMETER
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP
1.39
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-21
V
mA
mA
IOL2B
22
Rise Time1
Fall Time1
tr2B
tf2 B
VOL = 0.4 V, VOH = 2.0 V
1.8
ns
ns
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V, < 133 MHz
VT = 1.25 V, >= 133 MHz
1.47
47.9
45.8
1.8
55
52
45
42
Duty Cycle1
dt2B
%
Skew window1
Jitter, Cycle-to-cycle1
tsk2B
VT = 1.25 V
VT = 1.25 V
85
175
300
ps
ps
tjcyc-cyc2B
183
1Guaranteed by design, not 100% tested in production.
7
ICS9248-143
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
Skew window1
Jitter, Absolute1
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
-33
V
IOH1
mA
mA
IOL1
38
45
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.56
1.74
50.3
357
2.2
2.2
55
ns
ns
%
dt1
tsk1
tsk2
tjabs1
VT = 1.5 V
500
4
ps
ns
ps
VT = 1.5 V PCICLKE to PCI [5:0]
VT = 1.5 V
2
2.77
143
-250
250
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
VOH3
VOL3
IOH3
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
Propagation Time1
IOH = -28 mA
IOL = 19 mA
VOH = 2.0 V
VOL = 0.8 V
0.4
-46
V
mA
mA
ns
IOL3
32
42
Tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.22
1.25
45.6
169
1.6
1.6
52
Tf3
Dt3
ns
%
Tsk3
VT = 1.5 V
250
ps
Tsk3
VT = 1.5 V
3.3
5
ns
(Buffer In to output)
1Guaranteed by design, not 100% tested in production.
8
ICS9248-143
Electrical Characteristics - 24,48MHz, REF(1:0)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -14 mA
IOL = 6 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.4
-20
V
IOH5
mA
mA
IOL5
16
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2.1
2.31
51.5
368
4
4
ns
ns
%
dt5
45
55
600
Jitter, Absolute1
tjabs5
VT = 1.5 V
-600
ps
1Guaranteed by design, not 100% tested in production.
9
ICS9248-143
General I2C serial interface information
The information in this section assumes familiarity with I2C programming'
For more information, contact ICS for an I2C programming application note'
How to Write:
Controller (host) sends a start bit'
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit'
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time'
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1'
The ICS clock generator is a slave/receiver, I2C component' It can read back the data stored in the latches for verification'
Read-BackwillsupportIntelPIIX4"Block-Read"protocol'
2'
3'
4'
5'
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3'3V logic levels'
The data byte format is 8 bit bytes'
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller' The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred' The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes' The data is loaded until a Stop sequence is issued'
6'
At power-on, all registers are set to a default condition, as shown'
10
ICS9248-143
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used' With no jumper is installed
the pin will be pulled high' With the jumper in place the pin
will be pulled low' If programmability is not necessary, than
only a single resistor is necessary'The programming resistors
should be located close to the series termination resistor to
minimize the current loop area' It is more important to locate
the series termination resistor close to the driver than the
programming resistor'
The I/O pins designated by (input/output) on the ICS9248-
143 serve as dual signal functions to the device' During initial
power-up, they act as input pins' The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch' At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output function'
In this mode the pins produce the specified buffered clocks
to external loads'
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential' A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period'
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
11
ICS9248-143
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer' It is used to turn off the CPU clocks for low power operation'
CLK_STOP# is synchronized by the ICS9248-143' The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100
CPU clocks'All other clocks will continue to run while the CPU clocks are disabled' The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse' CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks'
INTERNAL
CPUCLK
PCICLK
CLK_STOP#
PCI_STOP# (High)
SDRAM
CPUCLK
CPUCLK _F
SDRAM_F
Notes:
1ꢀ All timing is referenced to the internal CPU clockꢀ
2ꢀ CLK_STOP# is an asynchronous input and metastable conditions may existꢀ This signal is synchronized
to the CPU clocks inside the ICS9248-143ꢀ
3ꢀ SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-143
CLK_STOP# signalꢀ SDRAM are controlled as shownꢀ
4ꢀ All other clocks continue to run undisturbedꢀ
12
ICS9248-143
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part' PD# is
an asynchronous active low input' This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer'
Internal clocks are not running after the device is put in power down' When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal' The power up latency needs to be less than 4 mS' The power down
latency should be as short as possible but conforming to the sequence requirements shown below' PCI_STOP# and CLK_STOP#
are considered to be donꢀt cares during the power down operations' The REF and 48MHz clocks are expected to be stopped in
the LOW state as soon as possible' Due to the state of the internal logic, stopping and holding the REF clock outputs in the
LOW state may require more than one clock cycle to complete'
PD#
CPUCLK
PCICLK
VCO
Crystal
Notes:
1ꢀ All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device)ꢀ
2ꢀ As shown, the outputs Stop Low on the next falling edge after PD# goes lowꢀ
3ꢀ PD# is an asynchronous input and metastable conditions may existꢀ This signal is synchronized inside this partꢀ
4ꢀ The shaded sections on the VCO and the Crystal signals indicate an active clockꢀ
5ꢀ Diagrams shown with respect to 133MHzꢀ Similar operation when CPU is 100MHzꢀ
13
ICS9248-143
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-143' It is used to turn off the PCICLK clocks for low power operation'
PCI_STOP# is synchronized by the ICS9248-143 internally' The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks' PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed' PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is one PCICLK clock'
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CLK_STOP#
PCI_STOP#
PCICLK
Notes:
1ꢀ All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 deviceꢀ)
2ꢀ PCI_STOP# is an asynchronous input, and metastable conditions may existꢀ This signal is required to be synchronized
inside the ICS9248ꢀ
3ꢀ All other clocks continue to run undisturbedꢀ
4ꢀ CLK_STOP# is shown in a high (true) stateꢀ
14
ICS9248-143
SYMBOL
In Millimeters
In Inc hes
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
.095
.008
.008
.005
c
SEE VARIATIONS
SEE VARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
E1
e
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
0°
8°
0°
8°
α
VARIATIONS
N
D mm.
D (inch)
MIN
MAX
MIN
MAX
9.652
28
34
48
56
64
9.398
11.303
15.748
18.288
20.828
.370
.445
.620
.720
.820
.380
.455
.630
.730
.830
11.557
16.002
18.542
21.082
J E DE C MO- 118
6/ 1/ 00
DOC# 10-0034
REVB
Ordering Information
ICS9248yF-143-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
15
information being relied upon by the customer is current and accurate.
ICS9248-143
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
-
MAX
1.20
0.15
1.05
0.27
0.20
MIN
-
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
0.05
0.80
0.17
0.09
.002
.032
.007
.0035
c
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319
D
E
E1
e
6.00
6.20
0.50 BASIC
0.75
.236
.244
0.020 BASIC
L
0.45
.018
.30
SEE VARIATIONS
SEE VARIATIONS
N
0°
8°
0°
8°
α
aaa
-
0.10
-
.004
VARIATIONS
N
D mm.
D (inch)
MIN
MAX
7.90
MIN
MAX
28
36
40
44
48
56
64
7.70
9.60
.303
.378
.429
.429
.488
.547
.665
.311
.386
.437
.437
.496
.555
6ꢀ10 mmꢀ Body, 0ꢀ50 mmꢀ pitch TSSOP
(0ꢀ020 mil)
9.80
(240 mil)
11.10
11.10
12.60
14.10
17.10
10.90
10.90
12.40
13.90
16.90
.673
MO-153 JEDEC
7/6/00 Rev B
Doc.# 10-0039
Ordering Information
ICS9248yG-143-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
16
information being relied upon by the customer is current and accurate.
相关型号：
ICS9248YF-146-T
Processor Specific Clock Generator, 166.67MHz, PDSO48, 0.300 INCH, MO-118, SSOP-48
IDT
ICS9248YF-146LF-T
Processor Specific Clock Generator, 166.67MHz, PDSO48, 0.300 INCH, LEAD FREE, MO-118, SSOP-48
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