ICS932S203GT [IDT]
Clock Generator, PDSO56;
| 型号： | ICS932S203GT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO56 光电二极管 |
| 文件： | 总18页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS932S203
Integrated
Circuit
Systems, Inc.
Frequency Generator with 133MHz Differential CPU Clocks
Recommended Application:
Servers based on Intel CK408 processors
Pin Configuration
Output Features:
•
•
•
•
•
•
•
•
•
4 Differential CPU Clock Pairs @ 3.3V
7 PCI (3.3V) @ 33.3MHz
3 PCI_F (3.3V) @ 33.3MHz
1 USB (3.3V) @ 48MHz
1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
1 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN
or 66.6MHz
•
1 66MHz_IN/3V66 (3.3V) @ Input/66MHz
Features:
•
Supports spread spectrum modulation,
down spread 0 to -0.5%.
•
Efficient power management scheme through PD#
and PCI_STOP#.
•
•
Uses external 14.318MHz crystal
Stop clocks and functional control available through
SMBus interface.
56-Pin 300mil SSOP/TSSOP
* These inputs have 150K internal pull-up resistor to VDD.
Key Specifications:
•
•
•
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <150ps
Block Diagram
Functionality
66Buff[2:0]
3V66[4:2]
(MHz)
PCI_F
PCI
(MHz)
CPU
3V66
FS1 FS0
(MHz) (MHz)
1
1
0
1
0
1
0
1
100
133.3
100
66.6
66.6
66.6
66.6
Hi-Z
66.6 In path 66.6 in/2
66. In path
66.6
66.6 in/2
33.3
0
0
133.3
Hi-Z
66.6
33.3
mid
mid
Hi-Z
Hi-Z
Tclk/2 Tclk/4
Tclk/4
Tclk/8
0601F—09/30/05
ICS932S203
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 8, 14, 19, 26,
32, 37, 46, 50
VDD
PWR
3.3V power supply
2
X1
X2
X2 Crystal Input 14.318MHz Crystal input
X1 Crystal
3
14.318MHz Crystal output
Output
7, 6, 5
PCICLK_F (2:0)
GND
OUT
Free running PCI clock not affected by PCI_STOP# for power management.
4, 9, 15, 20, 27,
31, 36, 41, 47
PWR
Ground pins for 3.3V supply
18, 17, 16, 13,
12,11, 10
PCICLK (6:0)
OUT
PCI clock outputs
66MHz_OUT (2:0)
3V66 (4:2)
66MHz_IN
3V66_5
OUT
OUT
IN
66MHz buffered 66MHz_OUT from 66MHz_IN input.
66MHz reference clocks, from internal VCO
66MHz input to buffered 66MHz_OUT and PCI clocks
66MHz reference clock, from internal VCO
Invokes power-down mode. Active Low.
23, 22, 21
24
25
OUT
IN
PD#
This 3.3V LVTTL input is a level sensitive strobe used to determine
when FS[0:2] and MULTISEL0 inputs are valid and are ready to be
sampled
28
Vtt_PWRGD#
IN
(active low)
29
30
33
SDATA
SCLK
Data pin for SMBus circuitry 5V tolerant
Clock pin of SMBus circuitry 5V tolerant
66MHz reference clocks, from internal VCO
I/O
IN
3V66_0
OUT
Halts PCICLK clocks at logic 0 level, when input low except
PCICLK_F which are free running
3.3V output selectable through I2C to be 66MHz from internal VCO or
48MHz (non-SSC)
34
35
PCI_STOP#
IN
3V66_1/VCH_CLK
OUT
38
39
48MHz_DOT
48MHz_USB
FS (1:0)
OUT
OUT
IN
48MHz output clock for DOT
48MHz output clock for USB
40, 55
Special 3.3V input for Mode selection
This pin establishes the reference current for the CPUCLK pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the
appropriate current.
42
I REF
OUT
MULTSEL0 input is sensed on power-up and then internally latched prior to
the pin being used for output on 3V 14.318MHz clocks.
43
MULTSEL0
IN
"Complementary" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
44, 48, 51, 53
CPUCLKC (3:0)
OUT
"True" clocks of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
45, 49, 52, 54
56
CPUCLKT (3:0)
REF
OUT
OUT
14.318MHz reference clock.
Power Groups
(Analog)
(Digital)
VDDA = PLL1
VDD48 = 48MHz, PLL
VDDREF = VDD for Xtal, POR VDDCPU
VDDPCI
VDD3V66
0601F—09/30/05
2
ICS932S203
Frequency Select Table
66Buff (2:0) /
3V66 (4:2)
66 In /
3V66_5
USB,
DOT
FS1
1
FS0
0
CPU 3V66 (1:0)
PCI
REF
note
Buffer
mode 66
Buffer
mode 66
Driven 66
Driven 66
Tri-state
outputs
100
66.6
66.6
66.6 In path
66.6 In path
66.6 IN 66.6 in/2 14.318
66.6 IN 66.6 in/2 14.318
48
48
1
1
133.3
0
0
0
1
100
66.6
66.6
66.6
66.6
66.6
66.6
33.3
33.3
14.318
14.318
48
48
133.3
mid1
mid1
0
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Tclk
Hi-Z
Tclk is at
X1 input
Tclk/2
Tclk/4
Tclk/4
Tclk/4
Tclk/8
Tclk/2
1. Low=Vin < 0.8V, Mid=1.0V < Vin < 1.8V, High=Vin > 2.0V
Host Swing Select Functions
Reference R,
Board Target
Output
Current
MULTISEL0
Iref =
Voh @ Z
Trace/Term Z
VDD/(3*Rr)
Rr = 221 1%,
Iref = 5.00mA
0
1
50 ohms
Ioh = 4* I REF 1.0V @ 50
Ioh = 6* I REF 0.7V @ 50
Rr = 475 1%,
Iref = 2.32mA
50 ohms
0601F—09/30/05
3
ICS932S203
Byte 0: Control Register
Bit
Pin#
-
55
40
Name
PWD
Type
Description
Bit 0
Bit 1
Bit 2
1
X
X
(Reserved)
FS0
FS1
R
R
Reflects the value of FS0 pin sampled on power up
Reflects the value of FS1 pin sampled on power up
Hardware mode: Reflects the value of PCI_STOP#
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
34
-
PCI_STOP#3
X
1
0
0
0
R
pin sampled on PWD
(Reserved)
VCH Select 66MHz/48MHz
0=66MHz, 1=48MHz
35
-
3V66_1/VCH
RW
RW
(Reserved)
Spread
Enabled
-
0=Spread Off, 1=Spread On
Byte 1: Control Register
Bit
Pin#
Name
PWD
Type
Description
CPUCLKT0
Bit 0 52, 51
Bit 1 49, 48
Bit 2 45, 44
1
RW
RW
RW
0=Disabled 1=Enabled
CPUCLKC0
CPUCLKT1
CPUCLKC1
CPUCLKT2
CPUCLKC2
1
1
0=Disabled 1=Enabled
0=Disabled 1=Enabled
Bit 3 52, 51
Bit 4 49, 48
Bit 5 45, 44
0
0
0
-
-
-
Reserved
Reserved
Reserved
CPUCLKT3
CPUCLKC3
MULTSEL0
Bit 6 53, 54
1
RW
R
0=Disabled 1=Enabled
Bit 7
43
X
Reflects the current value of MULTSEL0
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways.
Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert
PCI_STOP functionality via SMBus Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the SMBus Byte 0 Bit3. In Software mode it is not allowed to pull
the external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped
PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it
is not allowed to mix these modes.
In Hardware mode the SMBus byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the
chip is in PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (SMBus Byte 0 Bit 3 = 0)].
0601F—09/30/05
4
ICS932S203
Byte 2: Control Register
Bit
Pin#
10
11
12
13
16
17
18
-
Name
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
-
PWD
Type
RW
RW
RW
RW
RW
RW
RW
-
Description
0=Disabled 1=Enabled
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
1
1
1
1
1
1
1
0
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
(Reserved)
Byte 3: Control Register
Bit
Pin#
Name
PWD
Type
RW
RW
RW
Description
Bit 0
Bit 1
Bit 2
5
6
7
PCICLK_F0
PCICLK_F1
PCICLK_F2
1
1
1
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
Allow control of PCICLK_F0 with assertion of
Bit 3
Bit 4
Bit 5
5
6
7
PCICLK_F0
PCICLK_F1
PCICLK_F2
0
0
0
RW
RW
RW
PCI_STOP#. 0=Free Running, 1=Not free running
Allow control of PCICLK_F1 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free running
Allow control of PCICLK_F2 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free running
Bit 6
Bit 7
39
38
48MHz_USB
48MHz_DOT
1
1
RW
RW
0=Disabled 1=Enabled
0=Disabled 1=Enabled
Byte 4: Control Register
Bit
Pin#
21
22
23
24
35
33
-
Name
66MHz_OUT0/3V66-2
66MHz_OUT0/3V66-3
66MHz_OUT0/3V66-4
3V66_5
3V66_1/VCH_CLK
PWD
Type
RW
RW
RW
RW
RW
RW
R
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
(Reserved)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
1
1
1
1
1
1
0
0
3V66_0
-
-
-
R
(Reserved)
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
0601F—09/30/05
5
ICS932S203
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Bit
Pin#
X
X
X
X
X
X
X
X
Name
48MHz_USB
48MHz_USB
48MHz_DOT
PWD
Type
RW
RW
RW
Description
USB edge rate cntrol
USB edge rate cntrol
DOT edge rate control
DOT edge rate control
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
0
0
0
0
0
0
0
48MHz_DOT
RW
-
-
-
-
-
-
-
-
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Pin#
X
X
X
X
X
X
X
X
Name
PWD
1
0
0
0
X
X
X
X
Type
R
R
R
R
R
R
R
R
Description
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Vendor ID Bit0
Vendor ID Bit1
Vendor ID Bit2
Vendor ID Bit3
Revision ID Bit0
Revision ID Bit1
Revision ID Bit2
Revision ID Bit3
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Revision ID values will be based on
individual device's revision
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
0601F—09/30/05
6
ICS932S203
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
VIH
VIL
IIH
2
VSS - 0.3
-5
VDD + 0.3
V
V
0.8
5
VIN = VDD
mA
mA
IIL1 VIN = 0 V; Inputs with no pull-up resistors
-5
Input Low Current
IIL2 VIN = 0 V; Inputs with pull-up resistors
-200
229
220
Operating Supply Current IDD3.3OP
IDD3.3OP
mA
mA
CL = Full load; Select @ 100 MHz
CL =Full load; Select @ 133 MHz
230
233
360
360
60
Powerdown Current
Input Frequency
Pin Inductance
IDD3.3PD
Fi
mA
MHz
nH
pF
VDD = 3.3 V
14.318
Lpin
7
5
CIN Logic Inputs
Input Capacitance1
COUT Output pin capacitance
CINX X1 & X2 pins
6
pF
27
45
3
pF
Transition time1
Settling time1
Ttrans To 1st crossing of target frequency
ms
ms
ms
ns
Ts
From 1st crossing to 1% target frequency
3
Clk Stabilization1
TSTAB From VDD = 3.3 V to 1% target frequency
3
tPZH,tPZL
Output enable delay (all outputs)
PHZ,tPLZ
Output disable delay (all outputs)
1
1
10
10
Delay1
t
ns
1Guaranteed by design, not 100% tested in production.
0601F—09/30/05
7
ICS932S203
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF
PARAMETER
SYMBOL
Zo1
CONDITIONS
VO = Vx
MIN
TYP
MAX
850
UNITS NOTES
Current Source Output
Impedance
3000
Ω
1
Statistical measurement on single
ended signal using oscilloscope
math function.
Voltage High
Voltage Low
VHigh
VLow
660
770
5
1
1
mV
-150
150
Measurement on single ended
signal using absolute value.
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
756
-7
350
1150
1
1
1
mV
mV
mV
-300
250
550
140
Variation of crossing over all
edges
see Tperiod min-max values
200MHz nominal
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
12
1
-300
300
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
1,2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1
1
1
1
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
4.8735
5.8732
7.3728
9.8720
175
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
Average period
Tperiod
200MHz nominal
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
Tabsmin
Absolute min period
tr
tf
d-tr
d-tf
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
332
344
30
700
700
125
125
VOH = 0.525V VOL = 0.175V
175
ps
ps
ps
30
Measurement from differential
wavefrom
VT = 50%
Measurement from differential
wavefrom
dt3
tsk3
Duty Cycle
Skew
45
49
8
55
%
ps
ps
1
1
1
100
150
tjcyc-cyc
Jitter, Cycle to cycle
60
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
0601F—09/30/05
8
ICS932S203
Electrical Characteristics - PCICLK Un-Buffered Mode
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
33
MAX
55
UNITS
MHz
Ω
1
RDSP1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
12
1
VOH
2.4
V
1
VOL
0.55
-33
38
V
1
-33
30
mA
mA
ns
IOH
1
IOL
1
tr1
0.5
0.5
45
1.32 0.5to 2
1.39 0.5 to 2
1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
ns
1
Duty Cycle
%
dt1
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
52
55
1
Skew
tsk1
247
111
500
500
ps
1
tjcyc-cyc
Jitter,cycle to cyc
1Guaranteed by design, not 100% tested in production.
ps
Electrical Characteristics - PCICLK Buffered Mode
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
33
MAX
55
UNITS
MHz
Ω
1
RDSP1
VO = VDD*(0.5)
12
1
VOH
IOH = -1 mA
2.4
V
1
VOL
IOL = 1 mA
0.55
-33
38
V
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
-33
30
mA
mA
ns
IOH
1
IOL
1
tr1
0.5
0.5
45
1.29
1.32
51.9
209
0.5to 2
0.5 to 2
1
Fall Time
tf1
ns
1
Duty Cycle
%
dt1
VT = 1.5 V
VT = 1.5 V
55
1
Skew
tsk1
500
500
ps
1
tjcyc-cyc VT = 1.5 V
Jitter,cycle to cyc
1Guaranteed by design, not 100% tested in production.
107
ps
0601F—09/30/05
9
ICS932S203
Electrical Characteristics - 3V66 -Un-Buffered Mode: 3V66 [5:0]
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN TYP MAX UNITS
66.66
33
MHz
Ω
1
RDSP1
VO = VDD*(0.5)
12
55
1
VOH
IOH = -1 mA
2.4
V
1
VOL
IOL = 1 mA
0.55
-33
38
2
V
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
mA
mA
ns
ns
%
IOH
1
IOL
1
tr1
0.5
0.5
45
1.38
1.45
54.4
90
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
1
Skew
Jitter
tsk1
VT = 1.5 V
250
250
ps
ps
1
tjcyc-cyc VT = 1.5 V 3V66
128
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics- 3V66 - Buffered Mode: 3V66 [1:0] 66MHz_OUT [2:0]
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
66.66
33
MAX UNITS
MHz
1
RDSP1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
55
W
V
1
VOH
2.4
1
VOL
0.55
-33
38
2
V
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
mA
mA
ns
ns
%
IOH
1
IOL
1
tr1
0.5
0.5
45
1.44
1.36
54.6
105
121
169
89
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
250
1
Skew
Jitter
Skew
Jitter
tsk1
VT = 1.5 V 3V66 [1:0]
ps
ps
ps
ps
1
tjcyc-cyc
VT = 1.5 V 3V66 [1:0]
300
250
300
1
tsk1
tjcyc-cyc
VT = 1.5 V 66MHz_OUT [2:0]
VT = 1.5 V 66MHz_OUT [2:0]
1
1Guaranteed by design, not 100% tested in production.
0601F—09/30/05
10
ICS932S203
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
48DOT Rise Time
48DOT Fall Time
SYMBOL
CONDITIONS
MIN
TYP
48
MAX UNITS
MHz
FO1
1
RDSP1 VO = VDD*(0.5)
20
48
60
Ω
V
1
VOH
IOH = -1 mA
2.4
1
VOL
IOL = 1 mA
0.4
-23
27
1
V
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
-29
29
0.5
0.5
1
mA
mA
ns
ns
ns
ns
%
IOH
1
IOL
1
tr1
tf1
tr1
tf1
0.6
0.8
1
1
1
1
VCH 48 USB Rise Time
VCH 48 USB Fall Time
48 DOT Duty Cycle
VCH 48 USB Duty Cycle
48 DOT Jitter
1.2
2
1
1.3
2
1
1
dt1
dt1
VT = 1.5 V
VT = 1.5 V
45
45
52.8
53.5
183
223
55
55
%
1
tjcyc-cyc VT = 1.5 V
350
350
ps
ps
1
tjcyc-cyc VT = 1.5 V
VCH Jitter
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
48
MAX UNITS
MHz
1
RDSP1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
20
60
Ω
V
1
VOH
2.4
1
VOL
0.4
-23
27
V
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
-29
29
1
mA
mA
ns
ns
%
IOH
1
IOL
1
tr1
1.25
1.15
53
2
1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
1
2
1
Duty Cycle
dt1
VT = 1.5 V
VT = 1.5 V
45
55
1
tjcyc-cyc
Jitter
723
1000
ps
1Guaranteed by design, not 100% tested in production.
0601F—09/30/05
11
ICS932S203
General SMBus serial interface information
The information in this section assumes familiarity with SMBus programming.
For more information, contact ICS for an SMBus software program.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, SMBus component. It can read back the data stored in the latches
for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
2.
3.
4.
5.
The data byte format is 8 bit bytes.
To simplify the clock generator SMBus interface, the protocol is set to use only "Block-Writes" from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop
after any complete byte has been transferred. The Command code and Byte count shown above must be sent,
but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0601F—09/30/05
12
ICS932S203
Buffered Mode - 3V66[0:1], 66MHz_IN, 66MHz_OUT[0:2] and PCI Phase Relationship
All 3V66 clocks are to be in phase with each other. All 66MHz_OUT clocks are to be in phase with each other. There
is NO phase relationship between the 3V66 clocks and the 66MHz_OUT and PCI clocks. In the case where 3V66_1
is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks.
The PCI group should lag 3V66 by the standard skew described below as Tpci.
The 66MHz_IN to 66MHz_OUT delay is shown in the figure below and is specified to be within a min and max
propagation value.
66MHz_IN
Tpd
66MHz_OUT
Tpci
PCICLK_F
3V66
No Relationship
Group Skews at Common Transition Edges: (Buffered Mode)
GROUP
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
3V66
66MHz_OUT
3V66
66OUT
3V66 (1:0) pin to pin skew
66MHz_OUT (2:0) pin to pin skew
0
0
500
175
ps
ps
PCI
PCI
Tpd
Tpci
PCI_F (2:0) and PCI (6:0) pin to pin skew
0
500
4.5
3.5
ps
ns
ns
Propogation delay from 66MHz_IN to
66MHz_OUT (2:0)
66MHz_OUT (2:0) leads 33 MHz PCI
66MHz_IN 66MHz_OUT
66MHz_OUT to PCI
2.5
1.5
1Guaranteed by design, not 100% tested in production.
0601F—09/30/05
13
ICS932S203
Un-Buffered Mode 3V66 & PCI Phase Relationship
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock,
there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66
by the standard skew described below as Tpci.
3V66 (1:0)
3V66 (4:2)
3V66_5
Tpci
PCICLK_F (2:0) PCICLK (6:0)
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP
SYMBOL
3V66
CONDITIONS
MIN
0
TYP MAX UNITS
3V66
PCI
3V66 (5:0) pin to pin skew
500
500
3.5
ps
ps
ns
PCI
PCI_F (2:0) and PCI (6:0) pin to pin skew
0
3V66 to PCI
S3V66-PCI 3V66 (5:0) leads 33MHz PCI
1.5
1Guaranteed by design, not 100% tested in production.
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will
latch low in their next high to low transition.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
0601F—09/30/05
14
ICS932S203
PD# - Assertion (transition from logic "1" to logic "0")
When PD# is sampled low by two consecutive rising edges of CPU clock then all clock outputs except CPU clocks
must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with
a value of 2x Iref, and CPUC undriven. Note the example below shows CPU = 100MHz, this diagram and description
is applicable for all valid CPU frequencies 66, 100, 133, 200MHz.
Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more
than one clock cycle to complete.
Power Down Assertion of Waveforms - Buffered Mode
0ns
25ns
50ns
PD#
CPUT 100MHz
CPUC 100MHz
3V66MHz
66MHz_IN
66MHz_OUT
PCI 33MHz
USB 48MHz
REF 14.318MHz
PD# Functionality
PCICLK_F
PCICLK
USB/DOT
48MHz
CPU_STOP#
CPUT
CPUC
3V66
66MHz_OUT
PCICLK
1
0
Normal
Normal
Float
66MHz
Low
66MHz_IN
Low
66MHz_IN 66MHz_IN
Low Low
48MHz
Low
iref * Mult
0601F—09/30/05
15
ICS932S203
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
c
SEE VARIATIONS
SEE VARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
E1
e
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
.720
MAX
.730
56
18.288
18.542
JEDEC MO-118
6/1/00
DOC# 10-0034
REV B
300 mil SSOP
Ordering Information
ICS932S203yFLxT
Example:
ICS XXXX y F Lx T
Designation for tape and reel packaging
LF or LN = Lead Free, RoSH Compliant (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS, AV = Standard Device
0601F—09/30/05
16
ICS932S203
SYMBOL
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
c
N
MIN
-
MAX
1.20
0.15
1.05
0.27
0.20
MIN
-
MAX
.047
.006
.041
.011
.008
L
A
A1
A2
b
0.05
0.80
0.17
0.09
.002
.032
.007
.0035
E1
E
INDEX
AREEAA
c
1
2
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319
D
α
E
D
E1
e
6.00
6.20
0.50 BASIC
0.75
.236
.244
0.020 BASIC
L
0.45
.018
.30
A
A2
SEE VARIATIONS
SEE VARIATIONS
N
A1
0°
-
8°
0°
-
8°
α
- C -
aaa
0.10
.004
e
SEATINGG
PLAANNEE
b
VARIATIONS
aaaaa
C
D mm.
D (inch)
N
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
MIN
MAX
MIN
.547
MAX
(240 mil)
56
13.90
14.10
.555
7/6/00 Rev B
MO-153 JEDEC
Doc.# 10-0039
Ordering Information
ICS932S203yGLxT
Example:
ICS XXXX y G Lx T
Designation for tape and reel packaging
LF or LN = Lead Free, RoSH Compliant (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 to 7 digit numbers)
Prefix
ICS, AV = Standard Device
0601F—09/30/05
17
ICS932S203
Revision History
Rev.
Issue Date Description
Page #
1. Corrected Frequency Select Table Typo.
i. Added Foot Note.
F
9/30/2005 2. Updated LF Ordering Information.
3, 16-17
0601F—09/30/05
18
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