ICS950202YFLFT [IDT]
Processor Specific Clock Generator, 200MHz, PDSO48, 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48;
| 型号： | ICS950202YFLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 200MHz, PDSO48, 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48 光电二极管 |
| 文件： | 总20页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS950202
Systems, Inc.
Programmable Timing Control HubTM for P4TM
Recommended Application:
CK-408 clock for Intel® 845 chipset.
Pin Configuration
VDDREF
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF/FS2**1
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
Output Features:
X2
GND
•
•
•
•
•
•
3 - Pairs of differential CPU clocks @ 3.3V
3 - 3V66 @ 3.3V
9 - PCI @ 3.3V
2 - 48MHz @ 3.3V fixed
1 - VCH/3V66 @ 3.3V, 48MHz or 66MHz
1 - REF @ 3.3V, 14.318MHz
1**FS0/PCICLK7
1**FS1/PCICLK8
VDDPCI
GND
VDDCPU
1*WDEN/PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
CPUCLKT2
CPUCLKC2
MULTISEL0*
I REF
Features/Benefits:
GND
•
•
•
•
•
•
Programmable output frequency.
48MHz_USB/FS3**
48MHz_DOT
AVDD48
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_1
3V66_2
3V66_3
#RESET
VDDA
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
GND
3V66_0/VCH_CLK/FS4**
VDD3V66
GND
SCLK
SDATA
Vtt_PWRGD/PD#
GND
•
•
Programmable watch dog safe frequency.
Support I2C Index read/write and block read/write
operations.
•
Uses external 14.318MHz crystal.
48-Pin 300-mil SSOP
Key Specifications:
1. These outputs have 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
•
•
•
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
Block Diagram
Frequency Table
CPUCLK 3V66 PCICLK
FS4 FS3 FS2 FS1 FS0
MHz
MHz
MHz
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
1
100.00
133.33
66.67
66.67
66.67
66.67
66.67
33.33
33.33
33.34
33.33
200.00
For additional frequency selections please refer to Byte 0.
Power Groups
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz
0461M—02/10/06
Integrated
Circuit
ICS950202
Systems, Inc.
General Description
The ICS950202 is a single chip clock solution for desktop designs using the Intel 845 chipset with PC133 or DDR memory. It
provides all necessary clock signals for such a system.
The ICS950202 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially
programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider
ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output
clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 7, 13, 18,
30, 41, 45
VDD
PWR 3.3V power supply.
2
3
X1
X2
IN
Crystal input, has internal load cap (33pF) and feedback resistor from X2.
Crystal output, nominally 14.318MHz. Has internal load cap (33pF).
OUT
4, 8, 14, 19, 25, 29,
32, 36, 42
GND
PWR Ground pins for 3.3V supply.
22, 21, 20
3V66 (3:1)
OUT
3.3V Fixed 66MHz clock outputs for HUB.
PCICLK7
FS0
OUT
IN
3.3V PCI clock output
5
Logic input frequency select bit. Input latched at power on.
3.3V PCI clock output.
PCICLK8
OUT
6
9
FS1
IN
IN
Logic input frequency select bit. Input latched at power on.
Hardware enable of watch dog circuit. Enabled when latched high.
3.3V PCI clock output.
WDEN
PCICLK0
OUT
OUT
17, 16, 15, 12, 11, 10 PCICLK (6:1)
3.3V PCI clock outputs.
Real time system reset signal for frequency value or watchdog timmer timeout. This
signal is active low.
23
24
RESET#
VDDA
OUT
PWR Analog power 3.3V.
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (4:0)
inputs are valid and are ready to be sampled (active high).
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
Vtt_PWRGD
IN
IN
26
PD#
28
27
SCLK
SDATA
IN
I/O
Clock pin for I2C circuitry 5V tolerant.
Data pin for I2C circuitry 5V tolerant.
3.3V output selectable through I2C to be 66MHz from internal VCO or
48MHz (non-SSC).
3V66_0/VCH_CLK
OUT
31
FS4
IN
Logic input frequency select bit. Input latched at power on.
33
34
AVDD48
48MHz_DOT
FS3
PWR Analog power 3.3V.
OUT
IN
3.3V Fixed 48MHz clock output for DOT.
Logic input frequency select bit. Input latched at power on.
3.3V Fixed 48MHz clock output for USB.
35
48MHz_USB
OUT
This pin establishes the reference current for the CPUCLK pairs. This pin requires a
fixed precision resistor tied to ground in order to establish the appropriate current.
3.3V LVTTL input for selecting the current multiplier for CPU outputs
"Complementory" clocks of differential pair CPU outputs. These are current outputs
and external resistors are required for voltage bias.
37
38
I REF
OUT
IN
MULTSEL0
CPUCLKC (2:0)
39, 43, 46
OUT
"True" clocks of differential pair CPU outputs. These are current outputs and external
resistors are required for voltage bias.
40, 44, 47
CPUCLKT (2:0)
OUT
FS2
REF
IN
OUT
Logic input frequency select bit. Input latched at power on.
3.3V, 14.318MHz reference clock output.
48
0461M—02/10/06
2
Integrated
Circuit
ICS950202
Systems, Inc.
Maximum Allowed Current
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
All static inputs = Vdd or GND
Condition
Powerdown Mode
(PWRDWN# = 0)
40mA
Full Active
360mA
Host Swing Select Functions
Reference R,
Iref =
VDD/(3*Rr)
Board Target
MULTISEL0
Output
Current
Voh @ Z
Trace/Term Z
Rr = 221 1%,
Iref = 5.00mA
0
1
50 ohms
50 ohms
Ioh = 4* I REF 1.0V @ 50
Ioh = 6* I REF 0.7V @ 50
Rr = 475 1%,
Iref = 2.32mA
0461M—02/10/06
3
Integrated
Circuit
ICS950202
Systems, Inc.
General I2C serial interface information
How to Read:
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
Controller (Host)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
starT bit
T
T
starT bit
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
*See notes on the following page.
0461M—02/10/06
4
Integrated
Circuit
ICS950202
Systems, Inc.
Byte 0: Functionality and frequency select register (Default=0)
Bit
Description
PWD
Bit2 Bit7 Bit6 Bit5 Bit4
FS4 FS3 FS2 FS1 FS0
CPUCLK 3V66 PCICLK
Spread %
MHz
MHz
MHz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.90
100.00
103.00
105.00
107.00
109.00
111.00
114.00
117.00
120.00
127.00
130.00
133.33
170.00
180.00
190.00
133.90
133.33
120.00
125.00
134.90
137.00
139.00
141.00
143.00
145.00
150.00
155.00
160.00
170.00
66.67
67.27
66.67
68.67
70.00
71.33
72.67
74.00
76.00
78.00
80.00
84.67
86.67
88.89
56.67
60.00
63.33
66.95
66.67
60.00
62.50
67.45
68.50
69.50
70.50
71.50
72.50
75.00
77.50
80.00
85.00
66.67
66.67
33.63
33.33
34.33
35.00
35.67
36.33
37.00
38.00
39.00
40.00
42.33
43.33
44.44
28.33
30.00
31.67
33.48
33.33
30.00
31.25
33.73
34.25
34.75
35.25
35.75
36.25
37.5
+/-0.35% center spread
0 to -0.6% down spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
0 to -0.6% down spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
+/-0.35% center spread
0 to -0.6% down spread
0 to -0.6% down spread
Bit
(2,7:4)
Note 1
38.75
40.00
42.50
33.34
33.33
200.00
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2,7:4
0 - Normal
Bit 3
Bit 1
Bit 0
0
1
0
1 - Spread spectrum enable
0 - Watch dog safe frequency will be selected by latch inputs
1 - Watch dog safe frequency will be programmed by Byte 10 bit (4:0)
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
0461M—02/10/06
5
Integrated
Circuit
ICS950202
Systems, Inc.
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
PWD
Description
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
40, 39
44, 43
47, 46
1
1
1
X
X
X
X
X
CPUT/C2
CPUT/C1
CPUT/C0
FS4 Read back
FS3 Read back
FS2 Read back
FS1 Read back
FS0 Read back
-
-
-
-
-
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
-
PWD
Description
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
X
1
1
1
1
1
1
1
MULTSEL (Read back)
PCICLK_6
PCICLK_5
PCICLK_4
PCICLK_3
PCICLK_2
PCICLK_1
PCICLK_0
17
16
15
12
11
10
9
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
PWD
Description
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
34
35
-
-
31
-
1
1
1
X
0
X
1
1
48MHZ_DOT
48MHz_USB
Reset gear shift detect 1 = Enable, 0 = Disable
Reserved
3V66_0/VCH_CLK, (default) = 66.66MHz, 1=48MHz
Reserved
PCICLK8
PCICLK7
6
5
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
20
31
-
-
22
21
X
X
1
1
X
X
1
1
Reserved
Reserved
3V66_1
3V66_0/VCH_CLK
Reserved
Reserved
3V66_3
3V66_2
Notes:
1. PWD = Power on Default
2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at
high, CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0461M—02/10/06
6
Integrated
Circuit
ICS950202
Systems, Inc.
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Bit
Pin#
X
X
X
X
X
X
X
X
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Name
PWD
X
X
X
X
0
0
0
1
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision ID Bit3
Revision ID Bit2
Revision ID Bit1
Revision ID Bit0
Vendor ID Bit3
Vendor ID Bit2
Vendor ID Bit1
Vendor ID Bit0
Revision ID values will be based on individual device's revision
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 7: Revision ID and Device ID Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Device ID7
Device ID6
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
0
0
1
0
0
0
1
0
Device ID values will be based on individual device
"22H" in this case.
Byte 8: Byte Count Read Back Register
Bit
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
1
1
1
Note: Writing to this register will configure byte count and how
many bytes will be read back, default is 0FH = 15 bytes.
0461M—02/10/06
7
Integrated
Circuit
ICS950202
Systems, Inc.
Byte 9: Watchdog Timer Count Register
Bit
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
0
0
0
The decimal representation of these 8 bits correspond to X •
290ms the watchdog timer will wait before it goes to alarm mode
and reset the frequency to the safe setting. Default at power up is
8 • 290ms = 2.3 seconds.
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit
Name
PWD
Description
Programming Enable bit
Program
Enable
Bit 7
0
0 = no programming. Frequencies are selected by HW latches or Byte0 1
= enable all I2C programing.
Watchdog Enable bit.
This bit will over write WDEN latched value. 0 = disable, 1 = Enable.
Bit 6
WD Enable
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WD Alarm
SF4
0
0
1
0
0
0
Watchdog Alarm Status 0 = normal 1= alarm status
SF3
SF2
SF1
SF0
Watchdog safe frequency bits. Writing to these bits will configure the safe
frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit
Name
Ndiv 8
Mdiv 6
Mdiv 5
Mdiv 4
Mdiv 3
Mdiv 2
Mdiv 1
Mdiv 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the
reference divider value. Default at power up is equal to the
latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit
Name
Ndiv 7
Ndiv 6
Ndiv 5
Ndiv 4
Ndiv 3
Ndiv 2
Ndiv 1
Ndiv 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of Ndiv (8:0) correspond to the
VCO divider value. Default at power up is equal to the
latched inputs selecton. Notice Ndiv 8 is located in Byte 11.
0461M—02/10/06
8
Integrated
Circuit
ICS950202
Systems, Inc.
Byte 13: Spread Spectrum Control Register
Bit
Name
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The Spread Spectrum (12:0) bit will program the spread
precentage. Spread precent needs to be calculated based on the
VCO frequency, spreading profile, spreading amount and spread
frequency. It is recommended to use ICS software for spread
programming. Default power on is latched FS divider.
Byte 14: Spread Spectrum Control Register
Bit
Name
Reserved
Reserved
Reserved
SS 12
SS 11
SS 10
SS 9
SS 8
PWD
X
X
X
X
X
X
X
X
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
0
1
0
0
0
1
0
0
CPU 2 clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
CPU (1:0) clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
Byte 16: Output Divider Control Register
Bit
Name
Div 3
Div 2
Div 1
Div 0
Div 3
Div 2
Div 1
Div 0
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
1
0
1
0
1
3V66_0 clock divider ratio can be configured via these
4 bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
3V66 (3:1) clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
0461M—02/10/06
9
Integrated
Circuit
ICS950202
Systems, Inc.
Byte 17: Output Divider Control Register
Bit
Name
PWD
Description
3V66_0 Phase Inversion bit
3V66 (3:1) Phase Inversion bit
CPU 2 Phase Inversion bit
CPU (1:0) Phase Inversion bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3V66_INV
3V66_INV
CPU_INV
CPU_INV
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
0
0
0
0
1
0
0
1
PCI clock divider ratio can be configured via these 4 bits
individually. For divider selection table refer to Table 2.
Default at power up is latched FS divider.
Table 1
Table 2
Div (3:2)
Div (3:2)
00
01
10
11
00
01
10
11
Div (1:0)
Div (1:0)
00
01
10
11
/2
/3
/5
/7
/4
/6
/8
/16
/24
/40
/56
00
01
10
11
/4
/3
/5
/9
/8
/6
/16
/12
/20
/36
/32
/24
/40
/72
/12
/20
/28
/10
/14
/10
/18
Byte 18: Group Skew Control Register
Bit
Name
PWD
Description
These 2 bits delay the CPUCLKC/T2 with respect to
CPUCLKC/T (1:0)
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Bit 7
CPU_Skew 1
0
Bit 6
CPU_Skew 0
0
Bit 5
Bit 4
Reserved
Reserved
0
0
Reserved
Reserved
These 2 bits delay the CPUCLKC/T (1:0) clock with respect to
CPUCLKC/T2
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
Bit 3
Bit 2
CPU_Skew 1
CPU_Skew 0
0
0
Bit 1
Bit 0
Reserved
Reserved
0
0
Reserved
Reserved
Byte 19: Group Skew Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3V66_Skew 1
3V66_Skew 0
Reserved
1
0
0
0
0
1
0
0
These 2 bits delay the 3V66 (3:2) with respect to CPUCLK
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Reserved
Reserved
These 2 bits delay the 3V66 (1:0) with respect to CPUCLK
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Reserved
Reserved
Reserved
3V66_Skew 1
3V66_Skew 0
Reserved
Reserved
0461M—02/10/06
10
Integrated
Circuit
ICS950202
Systems, Inc.
Byte 20: Group Skew Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCI_Skew 3
PCI_Skew 2
PCI_Skew 1
PCI_Skew 0
Reserved
Reserved
Reserved
Reserved
1
0
0
0
1
0
0
0
These 4 bits can change the CPU to PCI (8:0) skew from 2.2ns
0.7ns. Default at power up is 0.5ns. Each binary increment or
decrement of Bits (3:0) will increase or decrease the delay of the
PCI clocks by 100ps.
Reserved
Reserved
Reserved
Reserved
Byte 21: Slew Rate Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCICLK8 Slew 1
PCICLK8 Slew 0
PCICLK7 Slew 1
PCICLK7 Slew 0
3V66 (3:1)_Slew 1
3V66 (3:1)_Slew 1
3V66_0_Slew 1
3V66_0_Slew 0
1
0
1
0
1
0
1
0
PCICLK8 clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCICLK7 clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
3V66 (3:1) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
3V66_0 clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
Byte 22: Slew Rate Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF Slew 1
REF Slew 0
1
0
1
0
1
0
1
0
REF clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI (6:4) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI (6:4) Slew 1
PCI (6:4) Slew 0
PCI (3:1) Slew 1
PCI (3:1) Slew 0
PCI0 Slew 1
PCI (3:1) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI0 clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI0 Slew 0
Byte 23: Slew Rate Control Register
Bit
Name
PWD
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
X
X
1
0
1
0
1
0
Reserved
VCH Slew 1
VCH Slew 0
48USB Slew 1
48USB Slew 0
48DOT Slew 1
48DOT Slew 0
VCH clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
48USB clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
48DOT clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
0461M—02/10/06
11
Integrated
Circuit
ICS950202
Systems, Inc.
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
UNITS
V
Input High Voltage
VDD+0.3
Input Low Voltage
Input High Current
VIL
IIH
VSS-0.3
-5
0.8
5
V
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
resistors
mA
IIL1
IIL2
-5
Input Low Current
mA
-200
Operating Supply Current
Powerdown Current
Input Frequency
IDD3.3OP
IDD3.3PD
Fi
CL= Full load
221
22
360
25
mA
mA
MHz
pF
IREF= 2.32
VDD = 3.3 V
14.318
CIN
Logic Inputs
5
6
Input Capacitance1
COUT
CINX
Output pin capacitance
X1 & X2 pins
pF
27
45
pF
From VDD = 3.3 V to 1% target
frequency
Clk Stabilization1
3V66 to PCI
TSTAB
1.8
ms
VT = 1.25 V/ VT = 1.5 V (target)
1.5
2.8
3.5
ns
ps
tsk3V66-PCI
VT = 1.25 V/ VT = 1.5 V (tol)
150
500
1 Guarenteed by design,not 100% tested in production
0461M—02/10/06
12
Integrated
Circuit
ICS950202
Systems, Inc.
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF
PARAMETER
SYMBOL
Zo1
CONDITIONS
VO = Vx
MIN
TYP
MAX
850
UNITS NOTES
Current Source Output
Impedance
3000
Ω
1
Statistical measurement on
single ended signal using
oscilloscope math function.
Voltage High
Voltage Low
VHigh
VLow
660
770
5
1
1
mV
-150
150
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Measurement on single ended
signal using absolute value.
756
-7
350
1150
1
1
1
mV
mV
mV
-300
250
550
140
Variation of crossing over all
edges
see Tperiod min-max values
200MHz nominal
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
12
1
-300
300
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
1,2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
4.8735
5.8732
7.3728
9.8720
175
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
Average period
Tperiod
200MHz nominal
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
Absolute min period
Tabsmin
Rise Time
Fall Time
tr
332
344
30
700
700
125
125
tf
VOH = 0.525V VOL = 0.175V
175
ps
ps
ps
1
1
1
Rise Time Variation
Fall Time Variation
d-tr
d-tf
30
Measurement from differential
wavefrom
VT = 50%
Measurement from differential
wavefrom
Duty Cycle
Skew
dt3
tsk3
45
49
8
55
%
ps
ps
1
1
1
100
150
Jitter, Cycle to cycle
tjcyc-cyc
60
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
0461M—02/10/06
13
Integrated
Circuit
ICS950202
Systems, Inc.
Electrical - Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3V +/-5%; CL= 10- 30pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO
CONDITIONS
MIN
TYP
33.33
MAX
UNITS
MHz
Ω
RDSN1
VOH1
VO = VDD*(0.5)
12
55
IOH = -1mA
IOL = -1mA
2.4
V
VOL1
0.17
0.55
-33
V
VOH@ MIN =1.0V, VOH@ MAX
=3.135V
Output High Current
Output Low Current
IOH1
IOL1
-33
30
mA
V
OL@ MIN = 1.95 V
60
23
VOL@ MAX = 0.4V
VOL = 0.4V, Voh =2.4V
VOH = 2.4V, VOL = 0.4V
VT = 1.5V
38
2
mA
ns
ns
%
Rise Time
Fall Time
Duty Cycle
Skew
tr1
tf1
0.5
0.5
45
1.7
1.4
53.6
218
210
2
dt1
55
500
250
tsk1
VT = 1.5V
ps
ps
Jitter
tjcyc-cyc
VT = 1.5V
1 Guarenteed by design,not 100% tested in production
Electrical Characteristics-3V66
TA = 0 - 70C; VDD = 3.3V+/- 5%; CL= 10-30pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
TYP
66.66
MAX
UNITS
MHz
Ω
FO1
1
VO = VDD*(0.5)
12
55
RDSP1
VOH1
VOL1
IOH = -1mA
IOL = -1mA
2.4
V
0.17
0.55
-33
V
VOH@ MIN =1.0V, VOH@ MAX
=3.135V
Output High Current
Output Low Current
IOH1
IOL1
-33
30
mA
V
OL@ MIN = 1.95 V,
60
23
VOL@ MAX = 0.4V
VOL = 0.4V, Voh =2.4V
VOH = 2.4V, VOL = 0.4V
VT = 1.5V
38
2
mA
ns
ns
%
Rise Time
Fall Time
Duty Cycle
Skew
tr1
tf1
0.5
0.5
45
1.7
1.4
50.7
284
170
2
dt1
55
500
250
tf1
VT = 1.5V
ps
ps
Jitter
tjcyc-cyc1
VT = 1.5V
45
1 Guarenteed by design,not 100% tested in production
0461M—02/10/06
14
Integrated
Circuit
ICS950202
Systems, Inc.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70C; VDD = 3.3V +/-5%; CL= 10-30pF (unlessotherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1mA
MIN
TYP
48.008
MAX
55
UNITS
MHz
Ω
FO
1
12
RDSN1
VOH1
VOL1
2.4
3.1
0.19
-42
V
IOL = -1mA
0.55
-23
V
VOH@ MIN =1.0V
OH@ MAX =3.135V
-29
29
Output High Current
Output Low Current
IOH1
V
-6
mA
VOL@ MIN = 1.95 V
VOL@ MAX = 0.4V
VOL = 0.4V, Voh =2.4V
VOH = 2.4V, VOL = 0.4V
VT = 1.5V
56
IOL1
24
27
1
mA
ns
ns
%
1
48DOT Rise Time
48DOT Fall Time
0.5
0.5
45
1
0.93
0.81
52.4
1.7
tr1
1
1
tf1
1
Duty Cycle-48 DOT
VCH 48 USB -Rise Time
VCH 48 USB -Fall Time
Duty Cycle-48 USB
48 DOT to 48 USB Skew
Jitter
55
2
dt1
tr1
tf1
VOL = 0.4V, Voh =2.4V
VOH = 2.4V, VOL = 0.4V
VT = 1.5V
ns
ns
%
1
1.4
2
1
45
52.9
187
55
1
dt1
1
VT = 1.5V
ns
tskew
1
tjcyc-cyc
VT = 1.5V
207
350
ps
1Guarenteed by design, not 100% tested.
Electrical Characteristics- REF
TA = 0 - 70C; VDD = 3.3V+/- 5%; CL= 10-30pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
MIN
TYP
14.318
MAX
UNITS
MHz
FO1
1
VO = VDD*(0.5)
IOH = -1mA
20
60
RDSP1
Ω
V
VOH1
VOL1
2.4
IOL = -1mA
0.17
0.55
-33
V
VOH@ MIN =1.0V, VOH@ MAX
=3.135V
Output High Current
Output Low Current
IOH1
IOL1
-33
30
mA
V
OL@ MIN = 1.95 V
OL@ MAX = 0.4V
60
23
V
38
2
mA
ns
ns
%
Rise Time
Fall Time
Duty Cycle
Jitter
tr1
tf1
VOL = 0.4V, Voh =2.4V
VOH = 2.4V, VOL = 0.4V
VT = 1.5V
1
1
1.7
1.4
54.5
400
2
dt1
45
55
1000
tjcyc-cyc1
VT = 1.5V
ps
1 Guarenteed by design,not 100% tested in production
0461M—02/10/06
15
Integrated
Circuit
ICS950202
Systems, Inc.
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In this
mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0461M—02/10/06
16
Integrated
Circuit
ICS950202
Systems, Inc.
3V66 & PCI Phase Relationship
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no
defined phase relationship between 3V66_1/VCH and other 3V66 clocks.The PCI group should lag 3V66 by the standard skew
described below as Tpci.
3V66 (1:0)
3V66 (4:2)
3V66_5
Tpci
PCICLK_F (2:0) PCICLK (6:0)
Group Skews at Common Transition Edges
GROUP
SYMBOL
3V66
CONDITIONS
MIN
0
TYP MAX UNITS
3V66
PCI
3V66 (5:0) pin to pin skew
500
ps
PCI
PCI_F (2:0) and PCI (6:0) pin to pin skew
0
500
ps
3V66 to PCI
S3V66-PCI 3V66 (5:0) leads 33MHz PCI
1.5
3.5
ns
1Guarenteed by design, not 100% tested in production.
PD# Functionality
PCICLK_F
PCICLK
USB/DOT
48MHz
CPU_STOP#
CPUT
CPUC
3V66
66MHz_OUT
PCICLK
1
0
Normal
Normal
Float
66MHz
Low
66MHz_IN
Low
66MHz_IN 66MHz_IN
Low Low
48MHz
Low
iref * Mult
0461M—02/10/06
17
Integrated
Circuit
ICS950202
Systems, Inc.
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising
edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion
of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.The final state
of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current values. The
CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUT
CPUC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
0
Normal
Normal
Float
iref * Mult
0461M—02/10/06
18
Integrated
Circuit
ICS950202
Systems, Inc.
c
In Millimeters
In Inches
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
a
hh xx 4455°°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
15.75
MAX
16.00
MIN
.620
MAX
b
48
.630
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS950202yFLFT
Example:
ICS XXXX y F - LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
0461M—02/10/06
19
Integrated
Circuit
ICS950202
Systems, Inc.
Revision History
Rev.
Issue Date Description
Page #
M
2/10/2006 Added LF to Ordering Information.
19
0461M—02/10/06
20
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