ICS950401FLF-T [IDT]
Clock Generator, PDSO48;
| 型号： | ICS950401FLF-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO48 光电二极管 |
| 文件： | 总14页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS950401
Integrated
Circuit
Systems, Inc.
AMD - K8™ System Clock Chip
Recommended Application:
AMD K8 Systems
Pin Configuration
REF1/FS1*
GND
*FS0/REF0 1
VDDREF 2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Output Features:
•
•
2 - Differential pair push-pull CPU clocks @ 3.3V
7 - PCI (Including 1 free running) @3.3V
VDDREF
REF2/FS2*
SPREAD*
VDDA
X1 3
X2 4
•
•
•
•
3 - Selectable HT/PCI 66/33MHz @3.3V
1 - 48MHz, @3.3V fixed.
1 - 24/48MHz @ 3.3V
GND 5
*PCI33/HT66SEL# 6
PCICLK33/HT66_0 7
PCICLK33/HT66_1 8
VDDPCI 9
GNDA
3 - REF @3.3V, 14.318MHz.
CPUCLKT0
CPUCLKC0
GND
Features:
•
•
Up to 220MHz frequency support
GND 10
VDDCPU
CPUCLKT1
CPUCLKC1
VDD
Support power management: PCI stop and stop
PCICLK33/HT66_2 11
NC 12
clocks controlled by I2C.
•
•
•
•
Spread spectrum for EMI reduction
Uses external 14.318MHz crystal
PCICLK0 13
PCICLK1 14
GND 15
I2C programmability features
GND
GNDA
Supports Hypes transport technology (HT66 output).
VDDPCI 16
PCICLK2 17
PCICLK3 18
VDDPCI 19
GND 20
VDDA
48MHz
GND
VDD
24_48MHz/Sel24_48#*
GND
PCICLK4 21
PCICLK5 22
PCICLK_F 23
*PCI_STOP# 24
SDATA
SCLK
48-SSOP/ TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
Block Diagram
Functionality
PCI33_HT66
FS2 FS1 FS0
CPU
PCI33
PCI33_HT66
COMMENTS
SEL#
PLL2
48MHz
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
1
1
0
1
0
1
0
1
X
0
1
X
X
X
X
X
X
Hi-Z
X
X
180.00
220.00
100.00
133.33
166.66
200.00
Hi-Z
X/6
X/6
30.00
36.56
33.33
33.33
33.33
33.33
Hi-Z
X/3
X/6
60.00
73.12
33.33/66.66
33.33/66.66
33.33/66.66
33.33/66.66
Tri-State Mode
Bypass Mode
Bypass Mode
10% under-clk
10% over-clk
Athlon Compatible
Athlon Compatible
Reserved
24_48MHz
/ 2
X1
X2
XTAL
OSC
REF (2:0)
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
Stop
CPUCLKC (1:0)
CPUCLKT (1:0)
PCICLK (5:0)
Hammer Operation
PCI
SDATA
SCLK
Control
Logic
DIVDER
PCICLK_F
FS (2:0)
Config.
Reg.
PCICLK33/HT66(2:0)
PCI33/HT66SEL#
PCI_STOP#
X 2
SPREAD
24_48SEL#
0499C—11/01/04
ICS950401
Pin Descriptions
PIN
PIN
PIN
TYPE
I/O
DESCRIPTION
#
NAME
1
Frequency select latch input pin / 14.318 MHz reference clock.
*FS0/REF0
2
3
4
5
6
7
8
9
VDDREF
X1
X2
GND
*PCI33/HT66SEL#
PCICLK33/HT66_0
PCICLK33/HT66_1
VDDPCI
PWR Ref, XTAL power supply, nominal 3.3V
IN Crystal input, Nominally 14.318MHz.
OUT Crystal output, Nominally 14.318MHz
PWR Ground pin.
IN
IN
IN
Input for PCI33/HT66 select. 0= 66.66MHz, 1= 33.33MHz,
PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.
PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.
PWR Power supply for PCI clocks, nominal 3.3V
PWR Ground pin.
10 GND
11 PCICLK33/HT66_2
12 NC
IN
NC
PCI clocks at 33.33MHz or HT clocks at 66.66MHz, selected by pin 6 select input.
No Connect
13 PCICLK0
14 PCICLK1
15 GND
OUT PCI clock output.
OUT PCI clock output.
PWR Ground pin.
16 VDDPCI
17 PCICLK2
18 PCICLK3
19 VDDPCI
20 GND
PWR Power supply for PCI clocks, nominal 3.3V
OUT PCI clock output.
OUT PCI clock output.
PWR Power supply for PCI clocks, nominal 3.3V
PWR Ground pin.
21 PCICLK4
22 PCICLK5
23 PCICLK_F
OUT PCI clock output.
OUT PCI clock output.
I/O
Free running PCI clock not affected by PCI_STOP# / Mode selection latch input pin.
Input select pin, Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
input low.
24 *PCI_STOP#
I/O
25 SCLK
26 SDATA
27 GND
IN
I/O
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
PWR Ground pin.
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =
24MHz.
28 24_48MHz/Sel24_48#*
I/O
29 VDD
30 GND
31 48MHz
32 VDDA
33 GNDA
34 GND
35 VDD
PWR Power supply, nominal 3.3V
PWR Ground pin.
OUT 48MHz clock output.
PWR 3.3V power for the PLL core.
PWR Ground pin for the PLL core.
PWR Ground pin.
PWR Power supply, nominal 3.3V
Complementory clock of differential CPU outputs. Push-pull requires external
termination.
36 CPUCLKC1
OUT
37 CPUCLKT1
38 VDDCPU
39 GND
OUT True clock of differential CPU outputs. Push-pull requires external termination.
PWR Supply for CPU clocks, 3.3V nominal
PWR Ground pin.
Complementory clock of differential CPU outputs. Push-pull requires external
termination.
40 CPUCLKC0
OUT
41 CPUCLKT0
42 GNDA
OUT True clock of differential CPU outputs. Push-pull requires external termination.
PWR Ground pin for the PLL core.
43 VDDA
PWR 3.3V power for the PLL core.
Asynchronous, active high input, with internal 120Kohm pull-up resistor, to enable
spread spectrum functionality.
44 SPREAD*
IN
45 REF2/FS2*
46 VDDREF
47 GND
I/O
14.318 MHz reference clock / Frequency select latch input pin.
PWR Ref, XTAL power supply, nominal 3.3V
PWR Ground pin.
48 REF1/FS1*
I/O
14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Drive Strength
0499C—11/01/04
2
ICS950401
General Description
The ICS950401 is a main clock synthesizer chip for AMD-K8. This provides all clocks required for Clawhammer and
Sledgehammer systems.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB
to 10dB.This simplifies EMI qualification without resorting to board design iterations or costly shielding.The ICS950401
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDDA = PLL2
Pin 32
Pin 43
Pin 2
VDDA = VDD for Core PLL
VDDREF = REF, Xtal
Skew Characteristics
Skew
Window
250
Parameter
Description
Test Conditons
Unit
measured at x-ing of CPU,
measured at x-ing of CPU,
1.5V of PCI clock
Tsk_CPU_CPU
ps
Tsk_CPU_PCI
Tsk_PCI_PCI
Tsk_PCI33-HT66
Tsk_CPU_HT66
2000
500
ps
ps
ps
ps
measured between rising
edge at 1.5V
time independent
skew
not dependent on
V, T changes
measured between rising
edge at 1.5V
500
measured between rising
edge at 1.5V
2000
measured at x-ing of CPU,
1.5V of PCI clock
Tsk_CPU_HT66
Tsk_CPU_CPU
500
200
ps
ps
measured at x-ing of CPU,
measured at x-ing of CPU,
1.5V of PCI clock
Tsk_CPU_PCI
Tsk_PCI_PCI
200
200
200
200
200
ps
ps
ps
ps
ps
measured between rising
time variant skew edge at 1.5V
varies over
V, T changes
measured between rising
edge at 1.5V
Tsk_PCI33-HT66
Tsk_CPU_HT66
Tsk_CPU_HT66
measured between rising
edge at 1.5V
measured at x-ing of CPU,
1.5V of PCI clock
0499C—11/01/04
3
ICS950401
General I2C serial interface information
How to Read:
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0499C—11/01/04
4
ICS950401
Byte0: Functionality and Frequency Select
Bit Pin # PWD
Description
Write disable (Write once)1
Spread Spectrum Enable. 0 =
Disable; 1 = Enable 2
Reserved
7
6
0
0
0
0
0
0
0
0
5
4
3
2
1
0
Reserved
FS2
45
48
1
FS1
FS0
Write Enable 3
Notes:
1. Write Disable. A '1' written to this bit after a '1' is written to BYTE0/bit 0 will permanently disable writing to I2C until
the part is powered off. Once the clock generator has been write disabled, the SMBus controller should still accept and
acknowledge subsequent write cycles but it should not modify any of the registers.
Spread Pin SS Bit Spread Enable
2.
0
0
1
1
0
1
0
1
Disabled
Enabled
Enabled
Enabled
3. A '1' written to this bit after power-up will enable writing to I2C. Subsequent '0's written to this bit will disable
modification of all registers except this single bit. When a '1' is written to Byte 0 Bit 7, all modification is permanently
disabled until the device power cycles. Block write transactions to the interface will complete, however unless the
interface has been previously unlocked, the writes will have no effect. The effect of writing to this bit does not take effect
until the subsequent block write command.
4. Clarification on frequency select on power-up:
i. Upon power-up, Byte0, bits (5:1) [FS(4:0)] are set to default hardware settings.
ii. A '1' is written to Byte0, bit 0 to enable software control.
iii. Every time Byte0 is written, frequency input defaults will be affected.
iv. If a '0' is written to Byte0, bit0, the software control is disabled. Disabling software control does not cause the
contents of Byte0
to default back to hardware setting for FS(4:0).
0499C—11/01/04
5
ICS950401
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7
1
1
1
1
1
1
1
1
PCICLK33/66_1
PCICLK33/66_0
PCICLK5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
37, 36
41, 40
45
1
1
1
1
1
1
1
1
CPUCLKT/C_1 (Note)
CPUCLKT/C_0
REF2
8
22
21
18
17
14
13
PCICLK4
48
REF1
PCICLK3
1
REF0
PCICLK2
28
24_48MHz
48MHz
PCICLK1
31
PCICLK0
11
PCICLK33/66_2
Note: This bit can be optional to disable the CPUCLKT/
C1 clock pair; CPUCLKT=L, CPUCLKC=H.
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: Read-Back Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
(Reserved)
BIT PIN# PWD
DESCRIPTION
PCICLK_F (Note)
-
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
0
23
44
28
6
-
(Reserved)
SPREAD
22
21
18
17
14
13
PCICLK5 (Note)
PCICLK4 (Note)
PCICLK3 (Note)
PCICLK2 (Note)
PCICLK1 (Note)
PCICLK0 (Note)
24_48SEL
PCI33/66SEL#
FS2 power-up latched pin state
FS1 power-up latched pin state
FS0 power-up latched pin state
(Reserved)
45
48
1
-
Note: The above individual free running enable/disable
controls are intended to allow individual clock
outputs to be made free running. A clock output
that has it's free running bit enabled will not be
turned off with the assertion of either PCI_STOP#.
Note: Can be optionally used as PCI33_F enable
control.
Byte 6: Byte Count Register
(1= enable, 0 = disable)
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Byte7 (Note)
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
1
0
0
0
0
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
1
VENDOR ID
Byte6 (Note)
Byte5 (Note)
Byte4 (Note)
Byte3 (Note)
Byte2 (Note)
Byte1 (Note)
Byte0 (Note)
REVISION ID
Notes:
Note: Writing to this register will configure byte count
and how many bytes will be read back. Default
state is 07H = 7 bytes.
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
0499C—11/01/04
6
ICS950401
Byte 7: Reserved, Active/Inactive Register
(1= enable, 0 = disable)
Byte 8: Single Pulse Mode Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved
BIT PIN# PWD
DESCRIPTION
Single Pulse Trigger
Single Pulse Activate
(Reserved)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
1
0
0
0
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Notes:
ATPG Function: This feature is only used during processor Burn-In and is an optional feature
for the clk vendor to implement.
Two SMBus register bits are required to implement this feature:
ATPG Mode Bit: Enables/Disables ATPG mode
ATPG Pulse Bit: Triggers a single CPUclk pulse when set
Assuming that the clock synthesizer is operating either in Normal mode or PLL bypass
mode, following sequence may be followed to generate an ATPG pulse.
1. Set the Write Enable Bit (Byte/Bit 0) to program the Clock Synthesizer registers using
the SM Bus.
2. Use the ATPG Mode Bit in the clock synthesizer configuration space to enable/disable
the ATPG mode. When this bit is set, the ATPG mode is enabled and the differential
CPU clock outputs are pulled in differential low state (CPUT = 0 and CPUC = 1). The
ATPG mode also requires the USBclk (48MHz) to run as usual. All other clks (PCI,
Ref, PCI33_66, SuperIO are not used by the ATPG mode therefore can either be left
running or shut off.
3. Use the ATPG Pulse Bit in the clock synthesizer program space to generate the ATPG
pulse. When the ATPG Pulse Bit is set, a differential ATPG pulse will be generated on
the differential CPU clock pins. The pulse width of the ATPG pulse will be one CPU
clock period. The CPU clock period in the ATPG mode is same as the one in Normal
mode or PLL bypass mode.
4. Clear the ATPG Pulse Bit, as the clock synthesizer only recognizes 0 to 1 transition of
the ATPG pulse bit for next ATPG pulse generation.
5. Use the ATPG Pulse Bit to generate the next ATPG pulse (set to 1).
6. If the ATPG Pulse bit is not set and the ATPG Mode Bit is cleared then the synthesizer
should work in normal or PLL bypass mode.
0499C—11/01/04
7
ICS950401
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 3.8V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +3.8 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V+/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
µ
IIH
VIN = VDD
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
A
µ
IIL2
-200
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
IDD3.3OP133 CL = 0 pF; Select @ 133MHz
PD
180
mA
Supply Current
600
16
5
Power Down
A
µ
Input frequency
Fi
VDD = 3.3 V;
10
27
14.318
MHz
pF
CIN
Logic Inputs
Input Capacitance1
Clk Stabilization1
CINX
TSTAB
X1 & X2 pins
45
3
pF
From VDD = 3.3 V to 1% target Freq.
ms
1Guaranteed by design, not 100% tested in production.
0499C—11/01/04
8
ICS950401
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output High Voltage
Output Low Voltage
Output Low Current
Rise Edge Rate1
Fall Edge Rate1
SYMBOL
ZO
CONDITIONS
VO = VX
MIN
15
TYP
MAX
UNITS
Ω
55
1.2
0.4
VOH2B
VOL2B
IOL2B
1
V
V
VOL = 0.3 V
18
2
mA
Measured from 20-80%
7
7
V/ns
V/ns
Measured from 80-20%
2
Differential Voltage,
Measured @ the Hammer
test load (single-ended
measurement)
VDIFF
0.4
2.3
V
Change in VDIFF_DC
magnitude, Measured @ the
Hammer test load (single-
ended measurement)
V
DIFF
-150
150
mV
∆
Common Mode Voltage,
Measured @ the Hammer
test load (single-ended
measurement)
Change in Common Mode
Voltage, Measured @ the
Hammer test load (single-
ended measurement)
VT = 50%
VCM
1.05
-200
1.45
200
V
V
CM
mV
∆
Duty Cycle1
Jitter, Cycle-to-cycle1
Notes:
dt2B
45
0
53
%
tjcyc-cyc2B
VT = VX
200
ps
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true"
input level and VCP is the "complement" input level.
3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max=(Vpullup(external)/2)+150mV
0499C—11/01/04
9
ICS950401
Electrical Characteristics - PCICLK, PCICLK33/HT66 (33MHz)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 9.0 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
-15
V
IOH1
mA
mA
IOL1
10
1
Rise Edge Rate1
Fall Edge Rate1
Duty Cycle1
Measured from 20-60%
Measured from 60-20%
VT = 50%
4
4
V/ns
V/ns
%
1
dt1
45
55
Jitter, Cycle-to-cycle1
tjcyc-cyc2B Measured on rising edge @ 1.5V
250
ps
Jitter, Accumulated1
Output Impedance
-1000
12
1000
55
ps
ZO
VO = VX
Ω
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK33/HT66 (66MHz)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 9.0 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
-15
V
IOH1
mA
mA
IOL1
10
1
Rise Edge Rate1
Fall Edge Rate1
Duty Cycle1
Measured from 20-60%
Measured from 60-20%
VT = 50%
4
4
V/ns
V/ns
%
1
dt1
45
55
Jitter, Cycle-to-cycle1
tjcyc-cyc2B Measured on rising edge @ 1.5V
250
ps
Jitter, Accumulated1
Output Impedance
-1000
12
1000
55
ps
ZO
VO = VX
Ω
1Guaranteed by design, not 100% tested in production.
0499C—11/01/04
10
ICS950401
Electrical Characteristics - REF
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Edge Rate1
Fall Edge Rate1
Duty Cycle1
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.4
-22
V
IOH5
mA
mA
IOL5
16
0.5
0.5
45
Measured from 20-80%
Measured from 80-20%
VT = 50%
2
2
V/ns
V/ns
%
dt5
55
Jitter, Cycle-to-cycle1
Jitter, Accumulated1
tjcyc-cyc2B Mesured on rising edge @ 1.5V
0
1000
1000
ps
ps
-1000
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Edge Rate1
Fall Edge Rate1
Duty Cycle1
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.4
-22
V
IOH5
mA
mA
IOL5
16
0.5
0.5
45
-1
Measured from 20-80%
Measured from 80-20%
VT = 50%
2
2
V/ns
V/ns
%
dt5
55
1
Jitter, Absolute1
tjabs5
VT = 1.5 V
ns
Jitter, Cycle-to-cycle1
tjcyc-cyc2B VT = VX, for 24_48MHz clock
tjcyc-cyc2B VT = VX, for 48MHz clock
0
500
ps
Jitter, Cycle-to-cycle1
Output Impedance
0
200
60
ps
ZO
VO = VX
20
Ω
0499C—11/01/04
11
ICS950401
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output) on the ICS9248-
175 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0499C—11/01/04
12
ICS950401
c
N
In Millimeters
In Inches
L
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
E1
E
A
A1
b
INDEX
AREA
c
1
2
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
a
hh xx 4455°°
D
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
A
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A1
- CC --
VARIATIONS
e
SEATING
PLANE
D mm.
D (inch)
N
b
MIN
15.75
MAX
16.00
MIN
.620
MAX
.10 (.004)
C
48
.630
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS950401yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0499C—11/01/04
13
ICS950401
c
N
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
In Inches
L
SYMBOL
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
SEE VARIATIONS
0.319 BASIC
.236
MAX
.047
.006
.041
.011
.008
E1
E
A
A1
A2
b
c
D
E
E1
e
INDEX
AREA
1
2
SEE VARIATIONS
8.10 BASIC
6.00
a
D
6.20
.244
0.50 BASIC
0.020 BASIC
L
0.45
0.75
.018
.030
N
α
aaa
SEE VARIATIONS
SEE VARIATIONS
A
0°
--
8°
0.10
0°
--
8°
.004
A2
A1
- CC --
VARIATIONS
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
12.40
MAX
12.60
MIN
.488
MAX
.496
b
48
aaa
C
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
(240 mil)
Ordering Information
ICS950401yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0499C—11/01/04
14
相关型号：
ICS950401YFLF-T
Processor Specific Clock Generator, 220MHz, PDSO48, 0.300 INCH, LEAD FREE, MO-118, SSOP-48
IDT
ICS950401YG-T
Processor Specific Clock Generator, 220MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48
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