ICS950811F [IDT]
Clock Generator;
| 型号： | ICS950811F |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator |
| 文件： | 总17页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS950811
Integrated
Circuit
Systems, Inc.
Frequency Generator with 200MHz Differential CPU Clocks
Recommended Application:
CK-408 clock for Brookdale-Mobile chipsets.
Programmable for group to group skew.
Pin Configuration
Output Features:
•
3 Differential CPU Clock Pairs (differential current
mode)
•
•
•
•
•
•
•
7 PCI (3.3V) @ 33.3MHz
3 PCI_F (3.3V) @ 33.3MHz
1 USB (3.3V) @ 48MHz
1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
5 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
•
•
Supports spread spectrum modulation,
down spread 0 to -0.5%.
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Key Specifications:
•
•
•
•
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
66MHz Output Jitter (Buffered Mode Only) <100ps
CPU Output Skew <100ps
56-Pin 300mil SSOP
6.10 mm. Body, 0.50 mm. pitch TSSOP
* These inputs have 150K internal pull-up resistor to VDD.
Block Diagram
Functionality
66MHzOut(2:0)
3V66(4:2)
(MHz)
PCI_F
PCI
(MHz)
66MHzIn
3V66(5)
(MHz)
CPU
(MHz)
3V66(1:0)
(MHz)
FS2 FS1 FS0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
66.66
100.00
200.00
133.33
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
Tristate
66.66
66.66
66.66
66.66
33.33
33.33
33.33
33.33
66.66
66.66
66.66
66.66
0
0
1
Buffered Mode
Not Supported
See ICS950805
1
100.00
200.00
133.33
Tristate
1
1
Mid
Mid
Tristate
TCLK/4
Tristate
TCLK/8
Tristate
TCLK/4
TCLK/2 TCLK/4
Reserv-
Reserved
ed
Mid
Mid
1
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserv-
Reserved
ed
0482C—11/06/02
ICS950811
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 8, 14, 19, 26,
32, 37, 46, 50
VDD
PWR
3.3V power supply
X2 Crystal
Input
2
3
X1
X2
14.318MHz Crystal input
X1 Crystal
Output
14.318MHz Crystal output
Free running PCI clock not affected by PCI_STOP# for
power management.
7, 6, 5
PCICLK_F (2:0)
GND
OUT
PWR
OUT
4, 9, 15, 20, 27,
31, 36, 41, 47
Ground pins for 3.3V supply
PCI clock outputs
18, 17, 16, 13,
12,11, 10
PCICLK (6:0)
24, 23, 22, 21
3V66 (5:2)
PD#
OUT
IN
66MHz reference clocks, from internal VCO
Invokes power-down mode. Active Low.
25
28
29
30
33
Vtt_PWRGD#
SDATA
IN
I/O
IN
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
66MHz reference clocks, from internal VCO
SCLK
3V66_0
OUT
Halts PCICLK clocks at logic 0 level, when input low except
PCICLK_F which are free running
3.3V output selectable through I2C to be 66MHz from internal
VCO or 48MHz (non-SSC)
34
35
PCI_STOP#
IN
3V66_1/VCH_CLK
OUT
38
39
40
48MHz_DOT
48MHz_USB
FS2
OUT
OUT
IN
48MHz output clock for DOT
48MHz output clock for USB
Special 3.3V input for Mode selection
This pin establishes the reference current for the CPUCLK
pairs. This pin requires a fixed precision resistor tied to ground
in order to establish the appropriate current.
42
43
I REF
OUT
IN
3.3V LVTTL input for selecting the current multiplier for CPU
outputs
MULTSEL0
"Complementory" clocks of differential pair CPU outputs. These
are current outputs and external resistors are required for
voltage bias.
44, 48, 51
CPUCLKC (2:0)
OUT
"True" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
45, 49, 52
CPUCLKT (2:0)
OUT
53
55, 54
56
CPU_STOP#
FS (1:0)
REF
IN
IN
Halts CPUCLK clocks at logic 0 level, when input low
Frequency select pins
OUT
14.318MHz reference clock.
Power Groups
(Analog)
(Digital)
VDDA = PLL1
VDD48 = 48MHz, PLL
VDDREF = VDD for Xtal, POR VDDCPU
VDDPCI
VDD3V66
0482C—11/06/02
2
ICS950811
Truth Table
3V66
(1:0)
(MHz)
66Buff (2:0)
3V66 (4:2)
(MHz)
PCI_F
PCI
(MHz)
CPU
(MHz)
66MHz_IN/
3V66_5
REF0
(MHz)
USB/DOT
(MHz)
FS2
FS1
FS0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
66.66
100.00
200.00
133.33
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
Tristate
TCLK/4
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
33.33
33.33
33.33
33.33
14.318
14.318
14.318
14.318
48.00
48.00
48.00
48.00
0
0
1
1
100.00
200.00
133.33
Tristate
TCLK/2
Buffered Mode Not Supported
See ICS950805
1
1
Mid
Mid
Mid
Mid
Tristate
TCLK/4
Tristate
TCLK/4
Tristate
TCLK/8
Tristate
TCLK
Tristate
TCLK/2
Reserved Reserved
Reserved Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Maximum Allowed Current
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
All static inputs = Vdd or GND
Condition
Powerdown Mode
(PWRDWN# = 0)
40mA
Full Active
360mA
Host Swing Select Functions
Reference R,
Iref =
VDD/(3*Rr)
Board Target
MULTISEL0
Output
Current
Voh @ Z
Trace/Term Z
Buffered Mode Not Supported
See ICS950805
0
Rr = 475 1%,
Iref = 2.32mA
1
50 ohms
Ioh = 6* I REF 0.7V @ 50
0482C—11/06/02
3
ICS950811
Byte 0: Control Register
Bit
Pin#
Name
PWD2
Type1
Description
Reflects the value of FS0 pin sampled on
power up
Bit 0
54
FS0
X
R
Reflects the value of FS1 pin sampled on
power up
Reflects the value of FS2 pin sampled on
power up
Hardware mode: Reflects the value of
PCI_STOP# pin sampled on PWD
Software mode:
0=PCICLK stopped
1=PCICLK not stopped
Bit 1
Bit 2
55
40
FS1
FS2
X
X
X
R
R
R
Bit 3
34
PCI_STOP#3
1
RW
Reflects the current value of the external
CPU_STOP# pin
VCH Select 66MHz/48MHz
0=66MHz, 1=48MHz
Bit 4
Bit 5
53
35
CPU_STOP#
3V66_1/VCH
X
0
R
RW
In power down mode controls output level
Bit 6
Bit 7
-
-
CPU_T(2:0)
0
0
0=stop high
1=stop low
Spread
Enabled
RW
0=Spread Off, 1=Spread On
Byte 1: Control Register
Bit
Pin#
Name
PWD2
Type1
Description
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
CPUCLKT2
CPUCLKC2
Bit 0 52, 51
Bit 1 49, 48
Bit 2 45, 44
1
RW
0=Disabled 1=Enabled4
1
1
RW
RW
0=Disabled 1=Enabled4
0=Disabled 1=Enabled4
Allow control of CPUCLKT0/C0 with assertion
of CPU_STOP# 0=Not free running 1=Free
running
Allow control of CPUCLKT1/C1 with assertion
of CPU_STOP# 0=Not free running 1=Free
running
Allow control of CPUCLKT2/C2 with assertion
of CPU_STOP# 0=Not free running 1=Free
running
CPUCLKT0
CPUCLKC0
Bit 3 52, 51
Bit 4 49, 48
Bit 5 45, 44
0
0
0
RW
RW
RW
CPUCLKT1
CPUCLKC1
CPUCLKT2
CPUCLKC2
Bit 6
Bit 7
-
43
-
0
X
-
R
(Reserved)
Reflects the current value of MULTSEL0
MULTSEL0
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways.
Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert
PCI_STOP functionality via I2C Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the I2C Byte 0 Bit3. In Software mode it is not allowed to pull the
external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped
PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it
is not allowed to mix these modes.
In Hardware mode the I2C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip
is in PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I2C Byte 0 Bit 3 = 0)].
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0482C—11/06/02
4
ICS950811
Byte 2: Control Register
Bit
Pin#
10
11
12
13
16
17
18
-
Name
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
-
PWD
Type
RW
RW
RW
RW
RW
RW
RW
-
Description
0=Disabled 1=Enabled
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
1
1
1
1
1
1
1
0
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
(Reserved)
Byte 3: Control Register
Bit
Pin#
Name
PWD
Type
RW
RW
RW
Description
Bit 0
Bit 1
Bit 2
5
6
7
PCICLK_F0
PCICLK_F1
PCICLK_F2
1
1
1
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
Allow control of PCICLK_F0 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free
running
Allow control of PCICLK_F1 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free
running
Allow control of PCICLK_F2 with assertion of
PCI_STOP#. 0=Free Running, 1=Not free
running
Bit 3
Bit 4
Bit 5
5
6
7
PCICLK_F0
PCICLK_F1
PCICLK_F2
0
0
0
RW
RW
RW
Bit 6
Bit 7
39
38
48MHz_USB
48MHz_DOT
1
1
RW
RW
0=Disabled 1=Enabled
0=Disabled 1=Enabled
Byte 4: Control Register
Bit
Pin#
21
22
23
24
35
33
-
Name
3V66-2
3V66-3
3V66-4
3V66_5
PWD
Type
RW
RW
RW
RW
RW
RW
R
Description
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
0=Disabled 1=Enabled
(Reserved)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
1
1
1
1
1
1
0
0
3V66_1/VCH_CLK
3V66_0
-
-
-
R
(Reserved)
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
0482C—11/06/02
5
ICS950811
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Bit
Pin#
X
X
X
X
X
X
X
X
Name
48MHz_USB
48MHz_USB
48MHz_DOT
PWD
Type
RW
RW
RW
Description
USB edge rate cntrol
USB edge rate cntrol
DOT edge rate control
DOT edge rate control
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
0
0
0
0
0
0
0
48MHz_DOT
RW
-
-
-
-
-
-
-
-
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Pin#
X
X
X
X
X
X
X
X
Name
PWD
Type
R
R
R
R
R
R
R
R
Description
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Vendor ID Bit0
Vendor ID Bit1
Vendor ID Bit2
Vendor ID Bit3
Revision ID Bit0
Revision ID Bit1
Revision ID Bit2
Revision ID Bit3
1
1
1
1
1
1
1
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Revision ID values will be based on
individual device's revision
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
0482C—11/06/02
6
ICS950811
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
VIH
CONDITIONS
MIN
TYP
MAX
VDD + 0.3
0.8
UNITS
V
2
VSS - 0.3
-5
VIL
V
IIH
VIN = VDD
5
mA
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
Input Low Current
mA
IIL2
VIN = 0 V; Inputs with pull-up resistors
CL = Full load; Select @ 100 MHz
CL =Full load; Select @ 133 MHz
-200
229
220
Operating Supply
Current
IDD3.3OP
mA
mA
230
360
IDD3.3OP
233
38.1
360
45
Powerdown Current
Input Frequency
Pin Inductance
IDD3.3PD IREF=5 mA
mA
MHz
nH
Fi
Lpin
VDD = 3.3 V
14.318
7
5
CIN
Logic Inputs
pF
Input Capacitance1
COUT
CINX
Ttrans
Ts
Output pin capacitance
6
pF
X1 & X2 pins
27
36
1
45
3
pF
Transition time1
Settling time1
Clk Stabilization1
Time to first clock1
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
From VDD = 3.3 V to 1% target frequency
Time to first clock
ms
ms
ms
3
TSTAB
T1C
3
1.8
10
10
ms
ns
ns
tPZH,tPZL Output enable delay (all outputs)
1
1
Delay1
tPHZ,tPLZ
Output disable delay (all outputs)
1Guaranteed by design, not 100% tested in production.
0482C—11/06/02
7
ICS950811
Electrical Characteristics - CPU
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Current Source
Output Impedance
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Zo1
VOH3
VOL3
tr3
VO = Vx
3000
2.4
Ω
Output High Voltage
Output Low Voltage
Rise Time
IOH = -1 mA
IOL = 1 mA
V
0.4
VOL = 0.41V, VOH = 0.86V
VOH = 0.86V VOL = 0.41V
175
175
240
242
700
700
ps
ps
Fall Time
tf3
measurement from differential wavefrom -
0.35V to +035V
VT = 50%
Duty Cycle
dt3
45
51
55
%
Skew
tsk3
50
76
100
150
ps
ps
1
tjcyc-cyc
VT = 50%
Jitter, Cycle to cycle
1Guaranteed by design, not 100% tested in production.
2 IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
MAX
55
UNITS
MHz
Ω
33.33
33
1
RDSP1
VO = VDD*(0.5)
12
1
VOH
IOH = -1 mA
2.4
V
1
VOL
IOL = 1 mA
0.55
-33
38
V
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
mA
mA
ns
IOH
1
IOL
1
tr1
0.5
0.5
45
1.32 0.5to 2
1.39 0.5 to 2
1
Fall Time
tf1
ns
1
Duty Cycle
dt1
%
52
55
1
Skew
tsk1
VT = 1.5 V
247
111
500
500
ps
1
tjcyc-cyc
VT = 1.5 V
Jitter,cycle to cyc
ps
1Guaranteed by design, not 100% tested in production.
0482C—11/06/02
8
ICS950811
Electrical Characteristics - 3V66
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
66.66
33
MAX
55
UNITS
MHz
Ω
Output Frequency
FO1
1
Output Impedance RDSP1 VO = VDD*(0.5)
12
1
Output High Voltage VOH
IOH = -1 mA
IOL = 1 mA
2.4
V
1
Output Low Voltage VOL
0.55
-33
38
2
V
1
Output High Current
Output Low Current
Rise Time
V OH@MIN = 1.0 V, V OH@MAX = 3.135 -33
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 30
mA
mA
ns
IOH
1
IOL
1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.5
0.5
45
1.38
1.45
54.4
243
1
Fall Time
2
ns
1
Duty Cycle
dt1
%
55
1
Skew
Jitter
tsk1
VT = 1.5 V
500
300
ps
ps
1
tjcyc-cyc VT = 1.5 V 3V66
139
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
48DOT Rise Time
48DOT Fall Time
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
MHz
FO1
48
48
1
Ω
V
RDSP1 VO = VDD*(0.5)
20
60
1
VOH
IOH = -1 mA
IOL = 1 mA
2.4
1
VOL
0.4
-23
27
1
V
1
V
OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29
mA
mA
ns
ns
ns
ns
%
IOH
1
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
29
0.5
0.5
1
IOL
1
tr1
tf1
tr1
tf1
0.6
0.8
1
1
1
1
1
VCH 48 USB Rise Time
VCH 48 USB Fall Time
48 DOT Duty Cycle
VCH 48 USB Duty Cycle
48 DOT Jitter
1.2
2
1
1.3
2
dt1
dt1
45
45
52.8
53.5
183
223
55
55
1
%
ps
ps
VT = 1.5 V
1
tjcyc-cyc VT = 1.5 V
350
350
1
tjcyc-cyc VT = 1.5 V
VCH Jitter
1Guaranteed by design, not 100% tested in production.
0482C—11/06/02
9
ICS950811
Electrical Characteristics - REF
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
14.318
48
MAX UNITS
MHz
1
Ω
V
RDSP1
VO = VDD*(0.5)
20
60
1
VOH
IOH = -1 mA
2.4
1
VOL
IOL = 1 mA
0.4
-23
27
2
V
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
-29
29
1
mA
mA
ns
ns
%
IOH
1
IOL
1
tr1
1.25
1.15
53
1
Fall Time
tf1
1
2
1
Duty Cycle
dt1
VT = 1.5 V
VT = 1.5 V
45
55
1
tjcyc-cyc
Jitter
723
1000
ps
1Guaranteed by design, not 100% tested in production.
0482C—11/06/02
10
ICS950811
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Dummy Byte Count
Byte 0
Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0482C—11/06/02
11
ICS950811
Un-Buffered Mode 3V66 & PCI Phase Relationship
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock,
there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66
by the standard skew described below as Tpci.
3V66 (1:0)
3V66 (4:2)
3V66_5
Tpci
PCICLK_F (2:0) PCICLK (6:0)
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
3V66
PCI
3V66
3V66 (5:0) pin to pin skew
0
42
500
ps
PCI
PCI_F (2:0) and PCI (6:0) pin to pin skew
0
130
500
ps
3V66 to PCI
S3V66-PCI 3V66 (5:0) leads 33MHz PCI
1.5
2.86
3.5
ns
1Guaranteed by design, not 100% tested in production.
0482C—11/06/02
12
ICS950811
Normal operation transition to Suspend State S1 Entry sequence of events:
1. Power-Down (PD#) pin is taken from a high to low to start into S1 Suspend state with digital filtering of the
transition in the clock circuit.
2. The first clocks to be forced to a Stop Low power down condition are the PCI buffer output clocks after a full
clock cycle. If the PCI_Stop# is low, then the free-running PCI clocks (for PCI and APIC signals) are the
remaining PCI buffer clocks stopped.
3. Immediately after the PCI clocks have been stopped the 66Buf_0:2 clocks are stopped low after the next
high to low transition. It will always be a sequence of PCI stopping, THEN the 66Buf clocks.
4. Following the two buffer output clocks being stopped (PCI then 66.6Buffer outputs), the remaining clocks
within a short delay will transition to a stopped power-down state. The first of these driven clocks that
transition to a stopped state are all of the CPU PLL clocks: the CPU and the driven 3V66 clocks.
5. After the CPU PLL clocks are stopped, the 48 MHz clocks (USB, DOT clocks) will stop low, then the REF
clock 14.318 MHz clock will stop low.
6. After the clocks have all been stopped, the internal PLL stages and the Crystal oscillator will all be driven to
a low power stopped condition.
7. As a note to power management calculations, please be aware that the CPU design requires that in the
Power-Down (S1 mode) the CPU outputs have a differential bias voltage driving the differential input stage of
the CPU in this S1 state. For this PD condition of the clock generator, the IDD_PD is running around 30 to
45 mA from having the Iref running (5 mA), the output multiplier bias generator at a 2X condition and the
output current source outputs are running at a 2xIref bias level (for approx 10 mA each CPU output). This
results in a higher level of Clock generator IDD_PD than in prior generations of clocks due to the CPU output
differential requirements.
Suspend State S1 Exit transition to normal operation sequence of events:
1. Power-Down (PD#) pin is taken from Low to High with digital filtering of the transition in the clock circuit to
return to normal running operation.
2. The Crystal Oscillator and the two PLL stages are released from PD to start-up to normal operation. No
clocks will operate until the Lock detect circuitry verifies the PLL has reached stable final frequency (the
same as normal initial power-up).
3. The CPU PLL clocks (differential CPU outputs and the driven 3V66_(0:1) clocks are operating first as soon
as the Lock detect releases the clocks. With the release of these clocks, the single 66Buf_1 buffer driven
output (at pin 22) is also released from the PD stopped state (but NOT the other 66Buf0,2 and not the PCI
outputs). This allows the GMCH chipset 66.6 MHz DLL stage to start operating and have an operating
feedback path before the other buffer outputs are released. This change is why the requirement is made that
pin 22 be the connection from the clock to the GMCH chipset. Note that along with the 66Buf_0,2 and the
PCI clocks, the 48 MHz and REF (14.318 MHz) clocks are also NOT released at this point.
4. A delay is built into the clock generator that allows the CPU, driven 3V66_0,1 and the single buffer clock
66Buf_1 (at pin 22) to operate before other clocks are released. This delay is larger than 30 uS and shorter
than 400 uS, and after this the other clocks are staged for a sequential release.
5. The initial clocks released after the delay are the 66Buf_0, 2 outputs.
6. After the 66Buf_0,2 clocks are released, then the PCI clocks are released.
7. It will always be the sequence of 66_1 (pin 22) released with the CPU clocks, then after the delay the
remaining 66Buf_0,2 first, THEN the PCI clocks.
8. Following the 66Buf_0,2 clocks, the 48 MHz (DOT and USB clocks) and the REF (14.318MHz) clocks are
released.
9. Note, the initial power-up time is the same as this PD release, the PLL will power-up and the outputs will be
running within a 3 ms time point.
0482C—11/06/02
13
ICS950811
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will
latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized
by the next rising edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable
via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling
as shown. The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the
output drive current values.The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC
signal will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUT
CPUC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
0
Normal
Normal
Float
iref * Mult
0482C—11/06/02
14
ICS950811
PD# - Assertion (transition from logic "1" to logic "0")
When PD# is sampled low by two consecutive rising edges of CPU clock then all clock outputs except CPU clocks
must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with
a value of 2x Iref, and CPUC undriven. Note the example below shows CPU = 100MHz, this diagram and description
is applicable for all valid CPU frequencies 66, 100, 133, 200MHz.
Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more
than one clock cycle to complete.
Power Down Assertion of Waveforms - Buffered Mode
0ns
25ns
50ns
PD#
CPUT 100MHz
CPUC 100MHz
3V66MHz
66MHz_IN
66MHz_OUT
PCI 33MHz
USB 48MHz
REF 14.318MHz
PD# Functionality
PCICLK_F
PCICLK
USB/DOT
48MHz
CPU_STOP#
CPUT
CPUC
3V66
66MHz_OUT
PCICLK
1
0
Normal
Normal
Float
66MHz
Low
66MHz_IN
Low
66MHz_IN 66MHz_IN
Low Low
48MHz
Low
iref * Mult
0482C—11/06/02
15
ICS950811
c
In Millimeters
In Inches
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
h x 45°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
D mm.
- C -
D (inch)
N
e
SEATING
PLANE
MIN
MAX
MIN
.720
MAX
b
56
18.31
18.55
.730
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS950811yF-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0482C—11/06/02
16
ICS950811
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
E1
E
INDEX
AREA
c
1
22
D
E
E1
e
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
D
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
A
A2
0°
--
8°
0.10
0°
--
8°
.004
α
aaa
A1
- CC --
VARIATIONS
e
SEATING
PLANE
b
D mm.
D (inch)
N
MIN
MAX
MIN
.547
MAX
.555
aaa
C
56
13.90
14.10
Reference Doc.: JEDEC Publication 95, MO-153
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
10-0039
(240 mil)
Ordering Information
ICS950811yG-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0482C—11/06/02
17
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