ICS952621FLF-T [IDT]
Clock Generator, PDSO48;
| 型号： | ICS952621FLF-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO48 光电二极管 |
| 文件： | 总17页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS952621
Systems, Inc.
Programmable Timing Control Hub™ for Next Gen P4™ processor
Features/Benefits:
Recommended Application:
CK409 48-pin part
Output Features:
•
•
Supports tight ppm accuracy clocks for Serial-ATA
Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
•
•
2 - 0.7V current-mode differential CPU pairs
1 - 0.7V current-mode differential CPU pairs for ITP
•
•
•
Supports CPU clks up to 400MHz in test mode
Uses external 14.318MHz crystal
•
•
1 - 0.7V current-mode differential SRC pair
9 - PCI (33MHz), including 3 free running PCI
Supports undriven differential CPU, SRC pair in PD#
and CPU_STOP# for power management.
•
•
•
•
1 - USB, 48MHz
1 - DOT, 48MHz
2 - REF, 14.318MHz
3 - 3V66, 66.66MHz
•
1 - 3V66/VCH, selectable 48MHz or 66MHz
Key Specifications:
•
•
CPU/SRC outputs cycle-cycle jitter < 125ps
3V66 outputs cycle-cycle jitter < 250ps
Pin Configuration
FS_A/REF1
FS_B/REF0
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
1
2
3
4
5
6
7
8
9
48 VDDA
47 GND
46 IREF
•
•
•
PCI outputs cycle-cycle jitter < 250ps
CPU outputs skew: < 100ps
+/- 300ppm frequency accuracy on CPU & SRC clocks
45 CPUCLKT_ITP
44 CPUCLKC_ITP
43 GND
42 CPUCLKT1
41 CPUCLKC1
40 VDDCPU
39 CPUCLKT0
38 CPUCLKC0
37 GND
36 SRCCLKT
35 SRCCLKC
34 VDD
33 VttPWR_GD#
32 SDATA
Functionality
FS2
USB/
DOT
MHz
CPU
MHz
SRC
MHz
3V66 PCI
MHz MHz
REF
MHz
VDDPCI 10
GND 11
B6b5
FS_A FS_B
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100.00 100/200 66.66 33.33 14.318 48.00
200.00 100/200 66.66 33.33 14.318 48.00
133.33 100/200 66.66 33.33 14.318 48.00
166.66 100/200 66.66 33.33 14.318 48.00
200.00 100/200 66.66 33.33 14.318 48.00
400.00 100/200 66.66 33.33 14.318 48.00
266.66 100/200 66.66 33.33 14.318 48.00
333.33 100/200 66.66 33.33 14.318 48.00
PCICLK0 12
PCICLK1 13
PCICLK2 14
PCICLK3 15
VDDPCI 16
GND 17
0
1
PCICLK4 18
PCICLK5 19
PD# 20
31 SCLK
30 3V66_0
29 3V66_1
48MHz_DOT 21
48MHz_USB 22
GND 23
28 GND
27 VDD3V66
26 3V66_2
VDD48 24
25 3V66_3/VCH
**120KΩ pull-down
48-pin SSOP & TSSOP
0756C—04/19/05
Integrated
Circuit
ICS952621
Systems, Inc.
Pin Description
PIN
#
PIN NAME
PIN TYPE
DESCRIPTION
FS_A latched input for frequency select
Reference output, 14.318Hz
FS_B latched input for frequency select
Reference output, 14.318Hz
1
FS_A/REF1
I/O
I/O
2
FS_B/REF0
3
4
VDDREF
X1
PWR
IN
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
5
6
7
8
X2
GND
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
Crystal output, Nominally 14.318MHz
Ground pin.
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
9
10
11
12
13
14
15
16
17
18
19
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCICLK4
PCICLK5
PCI clock output.
Asynchronous active low input pin, with 120Kohm internal pull-up resistor, used
to power down the device. The internal clocks are disabled and the VCO and
the crystal are stopped.
20
PD#
IN
21
22
23
24
48MHz_DOT
48MHz_USB
GND
OUT
OUT
PWR
PWR
48.008MHz Dot clock output
48.008MHz USB clock output
Ground pin.
Power for 48MHz output buffers and fixed PLL core.
3.3V 66.66MHz clock output
VCH: 48MHz VCH clock output
VDD48
25
3V66_3/VCH
OUT
26
27
28
29
30
31
32
3V66_2
VDD3V66
GND
3V66_1
3V66_0
SCLK
OUT
PWR
PWR
OUT
OUT
IN
3.3V 66.66MHz clock output
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch
inputs are valid and are ready to be sampled. This is an active low input.
Power supply, nominal 3.3V
SDATA
I/O
33
34
35
VttPWR_GD#
VDD
IN
OUT
OUT
Complementary clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
SRCCLKC
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
36
37
38
SRCCLKT
GND
OUT
PWR
OUT
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Ground pin.
"Complementary" clocks of differential pair CPU outputs for ITP.. These are
current mode outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs for ITP. These are current mode
outputs. External resistors are required for voltage bias.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
Ground pin.
CPUCLKC0
39
40
41
CPUCLKT0
VDDCPU
OUT
PWR
OUT
CPUCLKC1
42
43
44
CPUCLKT1
GND
OUT
PWR
OUT
CPUCLKC_ITP
45
46
CPUCLKT_ITP
IREF
OUT
OUT
47
48
GND
VDDA
PWR
PWR
3.3V power for the PLL core.
0756C—04/19/05
2
Integrated
Circuit
ICS952621
Systems, Inc.
General Description
ICS962621 is a programmable 48 pin clock chip following Intel CK409 Yellow Cover specification. This clock synthesizer provides a single
chip solution for next generation P4 Intel processors and Intel chipsets. ICS962621 is driven with a 14.318MHz crystal. It generates CPU
outputs up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.
Block Diagram
Frequency
Dividers
48MHz, USB, DOT, VCH
PLL2
X1
X2
XTAL
REF (1:0)
CPUCLKT (1:0)
CPUCLKC (1:0)
SRCCLKT0
Programmable
Spread
Programmable
Frequency
Dividers
STOP
Logic
SRCCLKC0
SCLK
SDATA
PLL1
3V66(3:0)
PCICLK (5:0), PCICLK_F (2:0)
CPUCLKT_ITP
VTTPWRGD#
PD#
Control
Logic
FS_A
CPUCLKC_ITP
I REF
FS_B
MODE
RESET#
Power Groups
Pin Number
Description
VDD
3
GND
6
Xtal, Ref
27
28
3V66 [0:3]
10,16
34
11,17
37
PCICLK outputs
SRCCLK outputs
48
47
Master clock, CPU Analog
48MHz, Fix Digital, Fix Analog
IREF
24
23
--
47
40
43
CPUCLK clocks
0756C—04/19/05
3
Integrated
Circuit
ICS952621
Systems, Inc.
Absolute Max
Symbol
Parameter
Min
Max
Units
V
DD + 0.5V
VDD_A
VDD_In
Ts
Tambient
Tcase
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Storage Temperature
V
V
°C
°C
°C
VDD + 0.5V
150
-0.5
-65
0
Ambient Operating Temp
Case Temperature
70
115
Input ESD protection
human body model
ESD prot
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
CONDITIONS
3.3V +/-5%
3.3V +/-5%
MIN
2
TYP
MAX
VDD + 0.3
0.8
UNITS NOTES
VIH
VIL
IIH
V
V
VSS
0.3
-5
-
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
5
uA
uA
IIL1
-5
Input Low Current
VIN = 0 V; Inputs with pull-up
resistors
IIL2
-200
uA
IDD3.3OP
IDD3.3PD
Full Active, CL = Full load;
Operating Supply Current
Powerdown Current
350
mA
260
0.3
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
35
12
mA
mA
MHz
nH
pF
Input Frequency3
Pin Inductance1
Fi
Lpin
CIN
COUT
CINX
14.31818
3
1
1
1
1
7
5
6
5
Logic Inputs
Output pin capacitance
Input Capacitance1
pF
pF
X1 & X2 pins
From VDD Power-Up or de-
assertion of PD# to 1st clock.
Triangular Modulation
CPU output enable after
PD# de-assertion
Clk Stabilization1,2
Modulation Frequency
Tdrive_PD#
TSTAB
1.8
33
ms
kHz
us
1,2
1
30
300
1
Tfall_Pd#
Trise_Pd#
PD# fall time of
PD# rise time of
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
5
5
ns
ns
1
2
3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
0756C—04/19/05
4
Integrated
Circuit
ICS952621
Systems, Inc.
Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL =2pF
PARAMETER
SYMBOL
CONDITIONS
VO = Vx
MIN
TYP
MAX
850
UNITS NOTES
Current Source Output
Impedance
Zo1
3000
Ω
1
Statistical measurement on single
ended signal using oscilloscope
math function.
Voltage High
Voltage Low
VHigh
VLow
660
749
3
1
1
mV
-150
150
Measurement on single ended
signal using absolute value.
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
756
-7
350
1150
1
1
1
mV
mV
mV
-300
250
550
140
300
Variation of crossing over all
edges
see Tperiod min-max values
200MHz nominal
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
12
1
-300
0
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
1,2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1
1
1
1
4.9985 5.0000 5.0015
4.9985 5.0266
5.9982 6.0000 6.0018
5.9982 6.0320
7.4978 7.5000 7.5023
7.4978 5.4000
9.9970 10.0000 10.0030
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
Average period
Tperiod
9.9970
4.8735
5.8732
7.3728
9.8720
175
10.0533
200MHz nominal
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
Tabsmin
Absolute min period
tr
tf
d-tr
d-tf
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
279
280
30
700
700
125
125
VOH = 0.525V VOL = 0.175V
175
ps
ps
ps
30
Measurement from differential
wavefrom
VT = 50%
Measurement from differential
wavefrom
dt3
tsk3
Duty Cycle
Skew
45
50.9
8
55
%
ps
ps
1
1
1
100
125
tjcyc-cyc
Jitter, Cycle to cycle
40
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair.
0756C—04/19/05
5
Integrated
Circuit
ICS952621
Systems, Inc.
Electrical Characteristics - 3V66 Mode: 3V66 [3:0]
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS
see Tperiod min-max values
66.66MHz output nominal
66.66MHz output spread
IOH = -1 mA
MIN
-300
14.9955
14.9955
2.4
TYP
MAX
300
15.0045
15.0799
UNITS Notes
ppm
ns
1,2
2
Tperiod
Clock period
ns
2
VOH
VOL
Output High Voltage
Output Low Voltage
V
V
IOL = 1 mA
0.55
-33
V
OH = 1.0 V
OH = 3.135 V
OL = 1.95 V
OL = 0.4 V
mA
mA
mA
mA
V/ns
V/ns
ns
IOH
IOL
Output High Current
Output Low Current
V
V
V
-33
30
38
4
4
2
2
Edge Rate
Edge Rate
Rise Time
Fall Time
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
1
1
0.5
0.5
1
1
1
1
tr1
tf1
1.78
1.72
49.9
80
VOH = 2.4 V, VOL = 0.4 V
ns
dt1
VT = 1.5 V
VT = 1.5 V
Duty Cycle
Skew
45
55
%
ps
ps
1
1
1
tsk1
250
250
tjcyc-cyc
VT = 1.5 V 3V66
Jitter
172
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS
see Tperiod min-max values
33.33MHz output nominal
33.33MHz output spread
IOH = -1 mA
MIN
-300
29.9910
29.9910
2.4
TYP
MAX
300
30.0090
30.1598
UNITS Notes
ppm
ns
ns
V
1,2
2
2
Tperiod
Clock period
VOH
VOL
Output High Voltage
Output Low Voltage
IOL = 1 mA
V OH = 1.0 V
0.55
-33
V
mA
mA
mA
mA
IOH
IOL
Output High Current
Output Low Current
VOH = 3.135 V
-33
30
VOL = 1.95 V
VOL = 0.4 V
38
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
1
0.5
0.5
45
4
4
2
V/ns
V/ns
ns
ns
%
1
1
1
1
1
1
1
tr1
tf1
dt1
1.78
1.72
51.2
59
2
55
500
250
tsk1
VT = 1.5 V
ps
tjcyc-cyc
VT = 1.5 V 3V66
Jitter
140
ps
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
0756C—04/19/05
6
Integrated
Circuit
ICS952621
Systems, Inc.
Electrical Characteristics - VCH, USB
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS Notes
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
see Tperiod min-max values
48.008MHz output nominal
IOH = -1 mA
-200
20.8257
2.4
200
20.8340 ns
V
0.55
-29
ppm
1,2
2
VOL
IOL = 1 mA
V OH = 1.0 V
VOH = 3.135 V
VOL = 1.95 V
VOL = 0.4 V
Rising edge rate
Falling edge rate
V
mA
mA
mA
mA
V/ns
V/ns
IOH
Output High Current
Output Low Current
-23
29
IOL
27
2
2
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
1
1
1
1
1
1
1
1
tr1
tf1
dt1
tsk1
VOL = 0.4 V, VOH = 2.4 V
1
1.45
1.37
52.5
2
2
55
1
ns
ns
%
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
45
VT = 1.5 V
ns
125us period jitter
(8kHz frequency modulation
amplitude)
Long Term Jitter
0.628
6
ns
1
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
Electrical Characteristics - 48MHz DOT Clock
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 5-10 pF (unless otherwise specified)
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
Tperiod
CONDITIONS
see Tperiod min-max values
48.008MHz output nominal
IOH = -1 mA
MIN
-200
20.8257
2.4
TYP
MAX
200
20.8340
UNITS Notes
ppm
ns
1,2
2
VOH
Output High Voltage
V
VOL
IOH
IOL = 1 mA
V OH = 1.0 V
VOH = 3.135 V
VOL = 1.95 V
VOL = 0.4 V
Output Low Voltage
0.55
-29
V
mA
mA
mA
mA
V/ns
V/ns
Output High Current
-23
29
IOL
Output Low Current
27
4
4
Edge Rate
Edge Rate
Rising edge rate
Falling edge rate
2
2
1
1
tr1
VOL = 0.4 V, VOH = 2.4 V
Rise Time
0.5
0.87
1
ns
1
tf1
dt1
tsk1
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
Fall Time
Duty Cycle
Skew
0.5
45
0.89
52.3
1
55
1
ns
%
ns
1
1
1
VT = 1.5 V
125us period jitter
(8kHz frequency modulation
amplitude)
Long Term Jitter
0.636
2
ns
1
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
0756C—04/19/05
7
Integrated
Circuit
ICS952621
Systems, Inc.
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
Tperiod
CONDITIONS
see Tperiod min-max values
14.318 MHz output nominal
IOH = -1 mA
MIN
-300
69.8270
2.4
TYP
MAX
300
69.8550
UNITS Notes
ppm
ns
1
1
Output High Voltage
V
VOH
1
IOL = 1 mA
Output Low Voltage
0.4
-33
V
VOL
V
OH = 1.0 V
mA
mA
mA
mA
ns
IOH
IOL
Output High Current
VOH = 3.135 V
VOL = 1.95 V
VOL = 0.4 V
-33
30
Output Low Current
38
2
1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
Rise Time
Fall Time
Skew
0.5
0.5
1.93
1.92
14
1
1
1
1
1
tr1
1
2
ns
tf1
1
500
55
ps
tsk1
1
VT = 1.5 V
Duty Cycle
45
53.8
400
%
dt1
1
VT = 1.5 V
Jitter
1000
ps
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
Group to Group Skews at Common Transition Edges
GROUP
3V66 to PCI
DOT-USB
DOT-VCH
SYMBOL
S3V66-PCI
SDOT_USB
CONDITIONS
3V66 (4:0) leads 33MHz PCI
180 degrees out of phase
in phase
MIN TYP MAX
UNITS
1.50
0.00
0.00
2.0
3.50
1.00
1.00
ns
ns
ns
SDOT_VCH
0756C—04/19/05
8
Integrated
Circuit
ICS952621
Systems, Inc.
I2C Table: Read-Back Register
Byte 0
Bit 7
Pin #
Name
RESERVED
Control Function
Type
-
-
0
1
PWD
X
X
X
X
X
X
-
-
-
-
-
-
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RESERVED
RESERVED
RESERVED
RESERVED
-
R
R
R
Freq Select 1 Read
-
-
FSB
FSA
R
X
Bit 1
READBACK of
CPU(2:0) Frequency
Back
Freq Select 0 Read
Back
R
X
Bit 0
I2C Table: Spreading and Device Behavior Control Register
Byte 1
Pin #
Name
SRC/SRC#
SRC
Control Function
Type
0
1
PWD
SRC Free-Running
FREE- STOPPAB
RW
0
Bit 7
Control
Output Control
RUN
Disable
LE
Enable
RW
R
R
R
R
1
X
X
X
X
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CPUT1/CPUC1
CPUT0/CPUC0
Output Control
Output Enable
RW
RW
Disable
Disable
Enable
Enable
1
I2C Table: Output Control Register
Byte 2 Pin #
Name
SRC_PD#
Drive Mode
Control Function
Type
0
1
PWD
0: Driven in PD#
RW
Driven
Hi-Z
0
Bit 7
SRC_Stop#
Drive Mode
0: Driven in
PCI_Stop#
RW
Driven
Hi-Z
0
Bit 6
RESERVED
RESERVED
0:driven in PD#
1: Tri-stated
RESERVED
RESERVED
RESERVED
-
RESERVED
X
0
0
X
X
X
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPUT1_PD# Drive Mode
CPUT0_PD# Drive Mode
RESERVED
RW
RW
-
-
-
Driven
Driven
Hi-Z
Hi-Z
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
I2C Table: Output Control Register
Byte 3 Pin #
Name
Control Function
PCI_Stop# Control
0:all stoppable PCI
Type
0
1
PWD
PCI_Stop#
RW
Enable
Disable
1
Bit 7
are stopped
RESERVED
Output Control
Output Control
Output Control
Output Control
RESERVED
PCICLK5
PCICLK4
PCICLK3
PCICLK2
-
RESERVED
X
1
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
PCICLK1
PCICLK0
Output Control
Output Control
RW
RW
Disable
Disable
Enable
Enable
1
1
Bit 1
Bit 0
0756C—04/19/05
9
Integrated
Circuit
ICS952621
Systems, Inc.
I2C Table: Output Control Register
Byte 4
Pin #
Name
Control Function
Type
0
1
PWD
48MHz_USB
2x output drive
48MHz_USB
RESERVED
RESERVED
RESERVED
PCICLK_F2
PCICLK_F1
PCICLK_F0
0=2x drive
RW
2x drive
1xdrive
1
Bit 7
Output Control
RESERVED
RESERVED
RESERVED
Output Control
Output Control
Output Control
RW
-
-
Disable
Enable
1
X
X
X
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
-
RW
RW
RW
stoppable Free-run
stoppable Free-run
stoppable Free-run
1
1
I2C Table: Output Control Register
Byte 5 Pin #
Bit 7
Name
Control Function
Output Control
Output Control
Type
RW
RW
0
1
PWD
1
1
DOT_48MHZ
CPU_T/C_ITP
3V66_3/VCH
Frequency Select
Disable
Disable
Enable
Enable
Bit 6
Output Select
RW
3V66
VCH
0
Bit 5
3V66_3/VCH
Frequency Select
Output Control
RW
Disable
Enable
1
Bit 4
RESERVED
3V66_2
3V66_1
RESERVED
Output Control
Output Control
Output Control
-
RESERVED
X
1
1
1
Bit 3
Bit 2
Bit 1
Bit 0
RW
RW
RW
Disable
Disable
Disable
Enable
Enable
Enable
3V66_0
I2C Table: Output Control and Fix Frequecy Register
Byte 6
Bit 7
Bit 6
Pin #
Name
Test Clock Mode
RESERVED
Control Function
Test Clock Mode
-
Type
-
-
0
1
Enable
-
PWD
0
0
Disable
-
FS_A and FS_B
Operation
CPU *2 Test Clock
-
Normal Test Mode
0
Bit 5
SRC Frequency
Select
Down/Center
Spread Spectrum
Enable
SRC Frequency Select
Spread Spectrum Type
Spread Spectrum Mode
-
-
100MHz
200MHz
0
0
0
Bit 4
Bit 3
Bit 2
Down
Spread
OFF
Center
Spread
ON
REF1
REF0
Output Control
Output Control
RW
RW
Disable
Disable
Enable
Enable
1
1
Bit 1
Bit 0
I2C Table: Vendor & Revision ID Register
Byte 7 Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
1
REVISION ID
VENDOR ID
Bit 0
0756C—04/19/05
10
Integrated
Circuit
ICS952621
Systems, Inc.
I2C Table: Byte Count Register
Byte 8
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
1
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to this register
will configure how
many bytes will be
read back, default is
08 = 8 bytes.
0756C—04/19/05
11
Integrated
Circuit
ICS952621
Systems, Inc.
PD#, Power Down
PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power.
When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start
without glitches.
PWRDWN#
CPU
CPU #
SRC
SRC#
3V66
PCIF/PCI USB/DOT
REF
14.318MHz
Low
Note
1
0
Normal
Normal Normal Normal 66MHz
33MHz
Low
48MHz
Low
Iref * 2 or
Float
Float
Iref * 2
or Float
Float
Low
Notes:
1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation.
2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses.
PD# Assertion
PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at
2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will the
tristated.
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
0756C—04/19/05
12
Integrated
Circuit
ICS952621
Systems, Inc.
PD# De-assertion
The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive
mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of
200mV in less than 300µs of PD# deassertion.
Tstable
<1.8mS
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC# 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
Tdrive_PwrDwn#
<300µS, >200mV
3V66_3/VCH Pin Functionality
The 3V66_4/VCH pin can be configured to be a 66.66MHz modulated output or a non-spread 48MHz output. The default is
3V66 clock. The switching is controlled by Byte 5 Bit 5. If it is set to '1' this pin will output the 48MHz VCH clock. The output
will go low on the falling edge of 3V66 for a minimum of 7.49ns. Then the output will transition to 48MHz on the next rising
edge of DOT_48 clock.
3V66
3V66_4/VCH
DOT_48
7.49nS min
0756C—04/19/05
13
Integrated
Circuit
ICS952621
Systems, Inc.
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supplyortheGND(logic0)voltagepotential. A10Kilohm(10K)
resistor is used to provide both the solid CMOS programming
voltageneededduringthepower-upprogrammingperiodandto
provide an insignificant load on the output clock during the
subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0756C—04/19/05
14
Integrated
Circuit
ICS952621
Systems, Inc.
c
In Millimeters
In Inches
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
h x 45°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- C -
D mm.
D (inch)
N
e
SEEAATTIINNGG
PLANE
MIN
15.75
MAX
16.00
MIN
.620
MAX
b
48
.630
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS952621yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0756C—04/19/05
15
Integrated
Circuit
ICS952621
Systems, Inc.
c
6.10 mm. Body, 0.50 mm. Pitch TSSOP
N
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL
L
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
22
E1
e
6.00
0.50 BASIC
6.20
.236
0.020 BASIC
.244
D
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
VARIATIONS
A1
D mm.
D (inch)
- C -
N
MIN
MAX
12.60
MIN
.488
MAX
.496
e
SEATTING
PLANE
48
12.40
b
Reference Doc.: JEDEC Publication 95, M O-153
10-0039
aaa
C
Ordering Information
ICS952621yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0756C—04/19/05
16
Integrated
Circuit
ICS952621
Systems, Inc.
Revision History
Rev.
Issue Date Description
Page #
1. Added TSSOP Ordering Information.
B
C
4/14/2005 2. Updated Ordering Information from "Lead Free" to "Annealed Lead Free".
4/19/2005 1. Corrected Package Type G=TSSOP.
15-16
16
0756C—04/19/05
17
相关型号：
ICS952621YG-T
Processor Specific Clock Generator, 400MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48
IDT
ICS952621YGLF-T
Processor Specific Clock Generator, 400MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, LEAD FREE, MO-153, TSSOP-48
IDT
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