ICS952702YFLFT [IDT]
Processor Specific Clock Generator, 222MHz, PDSO48, LEAD FREE, MO-118, SSOP-48;
| 型号： | ICS952702YFLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 222MHz, PDSO48, LEAD FREE, MO-118, SSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总17页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS952702
Systems, Inc.
Programmable Timing Control Hub for K7TM System
Recommended Application:
SiS746/746FX style chipset
Output Features:
Features/Benefits:
•
Selectable synchronous/asynchronous AGP/PCI
frequency
•
•
•
•
•
•
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
•
•
•
•
•
•
•
•
•
1 - Pair of differential open drain CPU outputs
1 - Single-ended open drain CPU output
8 - PCICLK @ 3.3V including 2 PCI clock free running
2 - AGPCLK @ 3.3V
3 - REF @ 3.3V
2 - ZCLK @ 3.3V
2 - IOAPIC @ 2.5V
1 - 12_48MHz @ 3.3V
1 - 24_48MHz @ 3.3V
•
•
Programmable watch dog safe frequency.
Support I2C Index read/write and block read/write
operations.
Key Specifications:
•
Uses external 14.318MHz reference or XTAL input.
•
•
•
•
•
CPU Output Jitter <250ps
AGP Output Jitter <250ps
ZCLK Output Jitter <250ps
PCI Output Jitter <500ps
CPU-AGP/PCI/ZCLK skew: 2.5ns~3.5ns
Pin Configuration
Functionality
VDDREF 1
**FS0/REF0 2
**FS1/REF1 3
**FS4/REF2 4
GNDREF 5
48 VDDLAPIC
47 IOAPIC1
46 IOAPIC0
45 GNDAPIC
Bit4 Bit3 Bit2 Bit1 Bit0
CPU
MHz
200.00 133.33
200.99 133.99 67.00
200.00
206.00
ZCLK
MHz
AGP
PCI
FS4
0
FS3
0
FS2
0
FS1
0
FS0
0
MHz
66.67
MHz
33.33
33.50
0
0
0
0
1
0
0
0
1
0
66.67
137.33 68.67
66.67
33.33
34.33
33.33
35.67
36.33
37.00
33.33
33.66
CPU_STOP#*
44
43 CPUCLKODT1
0
0
0
1
1
X1 6
0
0
1
0
0
133.33 133.33 66.67
214.00 142.66 71.33
218.00
RESET#
X2 7
42
41
0
0
1
0
1
GNDCPU
GNDZ 8
0
0
1
1
0
145.33 72.67
ZCLK0 9
40 CPUCLKODT0
CPUCLKODC0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
222.00 148.00 74.00
100.00 133.33 66.67
100.99 134.65 67.33
100.00
103.00
ZCLK1 10
39
38 VDDCPU
AGND
VDDZ 11
*PCI_STOP# 12
VDDPCI 13
**FS2/PCICLK_F0 14
*FS3/PCICLK_F1 15
PCICLK0 16
PCICLK1 17
GNDPCI 18
VDDPCI 19
PCICLK2 20
PCICLK3 21
PCICLK4 22
PCICLK5 23
GNDPCI 24
37
36 AVDD
66.67
137.33 68.67
66.67
33.33
34.33
33.33
35.67
36.33
37.00
SCLK
35
34
33
32
31
30
100.00 133.33 66.67
107.00 142.66 71.33
109.00
111.00 148.00 74.00
166.67 133.33 66.67
166.99 133.59 66.80
SDATA
PD#*
145.33 72.67
GNDAGP
AGPCLK0
AGPCLK1
33.33
33.40
33.33
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
166.67
66.67
66.67
29 VDDAGP
AVDD48
171.67 137.33 68.67
175.00 140.00 70.00
178.34 142.66 71.33
181.67 145.33 72.67
185.00 148.00 74.00
133.33 133.33 66.67
133.99 133.99 67.00
34.33
35.00
35.67
36.33
37.00
28
27 12_48MHz/SEL12#_48MHz*
26 24_48MHz/SEL24#_48MHz**
25 GND48
1
1
0
0
1
1
1
1
0
1
48-SSOP
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
33.33
33.50
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
66.67
133.33
66.67
33.33
34.33
35.00
35.67
36.33
37.00
137.33 137.33 68.67
140.00 140.00 70.00
142.66 142.66 71.33
145.33 145.33 72.67
148.00 148.00 74.00
1
1
1
1
1
1
1
1
0
1
0795D—05/06/05
Integrated
Circuit
ICS952702
Systems, Inc.
General Description
The ICS952702 is a two chip clock solution for desktop designs using SIS 746 style chipsets. When used with a zero delay
buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks signals
for such a system.
The ICS952702 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
Frequency
Dividers
PLL2
12_48MHZ
24_48MHZ
X1
X2
XTAL
REF (2:0)
CPUCLKODT (1:0)
CPUCLKODC0
RESET#
CPU_STOP#
PCI_STOP#
SCLK
Programmable
Spread
Programmable
Frequency
Dividers
IOAPIC (1:0)
PCICLKF (1:0)
PCICLK (5:0)
ZCLK (1:0)
STOP
Logic
SEL24_48MHZ
SEL12_48
PD#
PLL1
Control
Logic
SDATA
FS (4:0)
AGPCLK (1:0)
Power Groups
Pin Number
Description
VDD
1
GND
5
8
REF output, Xtal
Hyper ZCLK output
24/48MHz fixed, Fixed PLL (Fix1)
PCICLK output
11
28
25
13,19
29
18,24
32
AGP output
48
45
IOAPIC output
38
41
CPU_T/C output
36
37
CPU PLL, CPU MCLK
0795D—05/06/05
2
Integrated
Circuit
ICS952702
Systems, Inc.
Pin Description
PIN
TYPE
PIN #
PIN NAME
DESCRIPTION
1
2
VDDREF
PWR Ref, XTAL power supply, nominal 3.3V
I/O
I/O
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
**FS0/REF0
**FS1/REF1
**FS4/REF2
GNDREF
X1
X2
GNDZ
ZCLK0
3
4
5
6
7
8
9
PWR Ground pin for the REF outputs.
IN Crystal input, Nominally 14.318MHz.
OUT Crystal output, Nominally 14.318MHz
PWR Ground pin for the ZCLK outputs
OUT 3.3V Hyperzip clock output.
10 ZCLK1
OUT 3.3V Hyperzip clock output.
11 VDDZ
PWR Power supply for ZCLK clocks, nominal 3.3V
12 *PCI_STOP#
13 VDDPCI
IN
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low.
PWR Power supply for PCI clocks, nominal 3.3V
14 **FS2/PCICLK_F0
15 *FS3/PCICLK_F1
16 PCICLK0
17 PCICLK1
18 GNDPCI
I/O
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
OUT PCI clock output.
OUT PCI clock output.
PWR Ground pin for the PCI outputs
PWR Power supply for PCI clocks, nominal 3.3V
OUT PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
OUT PCI clock output.
PWR Ground pin for the PCI outputs
PWR Ground pin for the 48MHz outputs
19 VDDPCI
20 PCICLK2
21 PCICLK3
22 PCICLK4
23 PCICLK5
24 GNDPCI
25 GND48
Selectable 24 or 48MHz clock output / Latched select input for 24/48MHz output. 0=24MHz,
1 = 48MHz.
Selectable 12 or 48MHz clock output / Latched select input for 12/48MHz output. 0=12MHz,
1 = 48MHz.
26 24_48MHz/SEL24#_48MHz**
27 12_48MHz/SEL12#_48MHz*
I/O
I/O
28 AVDD48
29 VDDAGP
30 AGPCLK1
31 AGPCLK0
32 GNDAGP
PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
PWR Power supply for AGP clocks, nominal 3.3V
OUT AGP clock output
OUT AGP clock output
PWR Ground pin for the AGP outputs
Asynchronous active low input pin used to power down the device into a low power state. The
33 PD#*
IN
internal clocks are disabled and the VCO and the crystal are stopped. The latency of the
power down will not be greater than 1.8ms.
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
34 SDATA
35 SCLK
I/O
IN
36 AVDD
37 AGND
38 VDDCPU
PWR 3.3V Analog Power pin for Core PLL
PWR Analog Ground pin for Core PLL
PWR Supply for CPU clocks, 3.3V nominal
"Complememtary" clocks of differential pair CPU outputs. These open drain outputs need an
external 1.5V pull-up.
39 CPUCLKODC0
OUT
True clock of differential pair CPU outputs. These open drain outputs need an external 1.5V
pull-up.
PWR Ground pin for the CPU outputs
40 CPUCLKODT0
41 GNDCPU
OUT
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
42 RESET#
OUT
True clock of differential pair CPU outputs. These open drain outputs need an external 1.5V
pull-up.
43 CPUCLKODT1
OUT
44 CPU_STOP#*
45 GNDAPIC
46 IOAPIC0
47 IOAPIC1
48 VDDLAPIC
* Internal Pull-Up Resistor
IN
Stops all CPUCLK besides the free running clocks
PWR Ground pin for the IOAPIC outputs.
OUT IOAPIC clock outputs, norminal 2.5V.
OUT IOAPIC clock outputs, norminal 2.5V.
PWR Power pin for the IOAPIC outputs. 2.5V.
** Internal Pull-Down Resistor
0795D—05/06/05
3
Integrated
Circuit
ICS952702
Systems, Inc.
General SMBus serial interface information for the ICS952702
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each
byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0795D—05/06/05
4
Integrated
Circuit
ICS952702
Systems, Inc.
Table 1: Frequency Selection Table
FSA FSB
Bit4
Bit3
Bit2
Bit1
Bit0
CPU
ZCLK
AGP
PCI
Spread %
FS4
0
0
0
0
0
0
0
FS3
0
0
0
0
0
0
0
FS2
0
0
0
0
1
1
1
FS1
0
0
1
1
0
0
1
FS0
0
1
0
1
0
1
0
MHz
MHz
MHz
66.67
67.00
66.67
68.67
66.67
71.33
72.67
74.00
MHz
33.33
33.50
33.33
34.33
33.33
35.67
36.33
37.00
200.00
200.99
200.00
206.00
133.33
214.00
218.00
133.33
133.99
66.67
137.33
133.33
142.66
145.33
148.00
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
0
0
1
1
1
222.00
100.00
100.99
100.00
103.00
100.00
107.00
109.00
111.00
166.67
66.67
67.33
33.33
33.66
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
133.33
134.65
66.67
137.33
133.33
142.66
145.33
148.00
66.67
68.67
66.67
71.33
72.67
74.00
33.33
34.33
33.33
35.67
36.33
37.00
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
133.33
133.59
66.67
66.67
66.80
66.67
33.33
33.40
33.33
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
166.99
166.67
171.67
175.00
178.34
181.67
185.00
133.33
133.99
137.33
140.00
142.66
145.33
148.00
133.33
133.99
66.67
68.67
70.00
71.33
72.67
74.00
66.67
67.00
34.33
35.00
35.67
36.33
37.00
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
33.33
33.50
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
+/-0.35% center
133.33
137.33
140.00
142.66
145.33
148.00
66.67
68.67
70.00
71.33
72.67
74.00
33.33
34.33
35.00
35.67
36.33
37.00
137.33
140.00
142.66
145.33
148.00
1
1
1
1
1
1
1
1
0
1
0795D—05/06/05
5
Integrated
Circuit
ICS952702
Systems, Inc.
I2C Table: Frequency Select Register
Byte 0
Bit 7
Pin #
Name
Control Function
Type
0
1
PWD
Frequency H/W IIC
Select
-
FS Source
RW
Latch Inputs
IIC
0
-
27
-
Bit 6
Bit 5
Bit 4
SS_EN
SEL12/48MHz
FS4
Spread Enable Control
RW
RW
RW
OFF
12MHz
ON
48MHz
1
Output Control
Latch
Latch
Freq Select Bit 4
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
-
-
-
-
Bit 3
Bit 2
Bit 1
Bit 0
FS3
FS2
FS1
FS0
RW
RW
RW
RW
Latch
Latch
Latch
Latch
See Table 1: Frequency Selection Table
I2C Table: Output Control Register
Byte 1
Pin #
Name
Control Function
Type
0
1
PWD
26
27
-
47
46
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
24_48MHz
48MHz
SEL24/48MHz
IOAPIC1
IOAPIC0
Reserved
Output Control
Output Control
Output Control
Output Control
Output Control
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
24MHz
Disable
Disable
Reserved
Disable
Disable
Enable
Enable
48MHz
Enable
Enable
Reserved
Enable
Enable
1
1
Latch
1
1
0
1
1
43
40/39
CPUCLKODT1
CPUCLKODT0/C0
Output Control
Output Control
I2C Table: Output Control Register
Byte 2
Pin #
Name
Control Function
Type
0
1
PWD
15
14
23
22
21
20
17
16
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCICLK_F1
PCICLK_F0
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
I2C Table: Output Control Register
Byte 3
Pin #
Name
Control Function
Type
0
1
PWD
4
3
2
-
10
9
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF2
REF1
REF0
Reserved
ZCLK1
ZCLK0
Output Control
Output Control
Output Control
Reserved
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Reserved
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Reserved
Enable
Enable
Enable
Enable
1
1
1
0
1
1
1
1
30
31
AGPCLK1
AGPCLK0
0795D—05/06/05
6
Integrated
Circuit
ICS952702
Systems, Inc.
I2C Table: Async Frequency Selection & Output Skew Control Register
Byte 4
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
ASYNC2
ASYNC1
ASYNC0
Reserved
RW
RW
RW
RW
0
0
0
1
Fix PLL Async Freq
Programming bits
See Table 2: Async Frequency Selection
Table
Reserved
-
-
00:0ps; 01:250ps; 10:500ps; 11:750ps
This byte will advance or delay the skew
by 250ps per step
-
-
-
-
Bit 3
Bit 2
Bit 1
Bit 0
ZCLKSkw1
ZCLKSkw0
AGPSkw1
AGPSkw0
RW
RW
RW
RW
0
1
0
1
CPU-ZCLK Skew Control
00:0ps; 01:250ps; 10:500ps; 11:750ps
This byte will advance or delay the skew
by 250ps per step
CPU-AGP Skew Control
Table 2: Asynchronous Frequency Selection Table
B4 bit7
B4 bit6
B4 bit5
ZCLK
AGP
PCI
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Main PLL
132
132
132
Main PLL
132
Main PLL
66
75.4
88
Main PLL
66
Main PLL
33
37.7
44
Main PLL
33
1
1
1
1
0
1
132
132
75.4
88
33
33
Table 3: AGP Divider Ratio Combination Table
Divider (3:2)
*01
Bit
0
10
11
MSB
1
4
3
5
2
8
4
8
0
1
0
1
100
101
110
1000
1001
1010
16
12
20
1100
1101
1110
32
24
40
6
10
10
10
11
11
15
111
30
1011
60
1111
120
LSB
Address
Div
Address
Div
Address
Div
Address
Div
I2C Table: Revision ID & Output Divider Control Register
Byte 5
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
REV_ID3
REV_ID2
REV_ID1
REV_ID0
R
R
R
-
-
-
-
-
-
-
-
0
0
0
1
1
Revision ID
R
RW
AGPDiv3
AGPDiv2
AGPDiv1
AGPDiv0
AGP divider ratio can be
configured via these 4
bits individually.
-
-
-
Bit 2
Bit 1
Bit 0
RW
RW
RW
1
0
1
See Table 3: Divider Ratio Combination
Table
0795D—05/06/05
7
Integrated
Circuit
ICS952702
Systems, Inc.
I2C Table: Slew Rate Control Register
Byte 6
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCIStr1
PCIStr0
PCIStr1
PCIStr0
PCIStr1
PCIStr0
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
PCICLK_F(1:0) Strength
Control
00=.63x; 01=.75x; 10=.88x; 11=1x
Strength
PCICLK(2:0) Strength
Control
00=.63x; 01=.75x; 10=.88x; 11=1x
Strength
PCICLK(5:3) Strength
Control
00=.63x; 01=.75x; 10=.88x; 11=1x
Strength
AGPStr1
AGPStr0
RW
RW
1
1
AGPCLK Strength
Control
00=.7x; 01=.8x; 10=.9x; 11=1x Strength
I2C Table: Reserved Register
Byte 7
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
I2C Table: Byte Count Register
Byte 8
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
1
1
1
1
Writing to this register will
configure how many
bytes will be read back,
default is 0F = 15 bytes.
I2C Table: Watchdog Timer Control Register
Byte 9
Bit 7
Pin #
-
Name
WDSA control
Control Function
WD soft alarm control
WD Hard Alarm Status
Read back
WD Soft Alarm Status
Type
RW
0
1
PWD
0
Disable
Enable
-
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
WDHRB
WDSRB
GR_EN
WDTCtrl
R
R
Normal
Normal
Alarm
Alarm
X
X
0
0
Read back
Gear Shift Reset Enable
RW
RW
Disable
Enable
Watch Dog Time base
control
290ms base
1160ms base
These bits represent X*290ms (or
1.16S) the watchdog timer will wait
before it goes to alarm mode. Default is
7 X 290ms =2s.
-
-
-
Bit 2
Bit 1
Bit 0
WD2
WD1
WD0
WD Timer Bit2
RW
RW
RW
1
1
1
WD Timer Bit1
WD Timer Bit0
0795D—05/06/05
8
Integrated
Circuit
ICS952702
Systems, Inc.
I2C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Pin #
Name
Control Function
Type
0
1
PWD
M/N Programming
Enable
Bit 7
Bit 6
Bit 5
-
-
-
M/NEN
WDEN
RW
RW
RW
Disable
Disable
Enable
Enable
0
0
0
Watchdog Enable
WD Safe Frequency
Mode
WDFSEN
Latched FS/Byte0
WD B10 b(4:0)
-
-
-
-
-
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
RW
RW
RW
RW
RW
0
1
0
0
0
Watch Dog Safe Freq
Programming bits
Writing to these bit will configure the
safe frequency as Byte 0 Bit (4:0)
I2C Table: VCO Frequency Control Register
Byte 11
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
N Div8
N Div9
M Div5
M Div4
N Divider Bit 8
N Divider Bit 9
The decimal
RW
RW
RW
RW
-
-
-
-
-
-
-
-
X
X
X
X
representation of M Div
(5:0) + 2 is equal to
reference divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
-
-
-
-
Bit 3
Bit 2
Bit 1
Bit 0
M Div3
M Div2
M Div1
M Div0
RW
RW
RW
RW
-
-
-
-
-
-
-
-
X
X
X
X
I2C Table: VCO Frequency Control Register
Byte 12
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
The decimal
representation of N Div
(9:0) + 8 is equal to VCO
divider value. Default at
power up = latch-in or
Byte 0 Rom table.
I2C Table: Spread Spectrum Control Register
Byte 13
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
These Spread Spectrum
bits will program the
spread percentage. It is
recommended to use ICS
Spread % table for
spread programming.
0795D—05/06/05
9
Integrated
Circuit
ICS952702
Systems, Inc.
Absolute Maximum Ratings
Core SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 4.6V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . . . . 0°C to +70°C
StorageTemperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
CaseTemperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
StressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Theseratingsarestress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sectionsofthespecificationsisnotimplied. Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectproduct
reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
VIL
IIH
IIL1
IIL2
V
DD + 0.3
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating Supply
Current
2
V
V
mA
mA
mA
VSS - 0.3
0.8
5
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
-200
IDD(op)
IDDPD
Full Active, CL = full load; Select @ 100MHz
180
250
12
mA
mA
Power Down Supply
Current
All diff pairs tri-stated
1.2
Fi
CIN
CINX
VDD = 3.3 V;
Logic Inputs
X1 & X2 pins
Input frequency
11
14.318
16
5
45
MHz
pF
pF
Input Capacitance1
27
30
Spread Modulation
Frequency1
fSS
320
33
KHz
ms
From VDD Power-Up of de-assertion of PD#
to 1st clock.
Clk Stabilization1
TSTAB
1.8
TCPU-AGP
TCPU-ZCLK
TCPU-PCI
Skew
Skew
CPU @ crossing, AGP @ 1.5V
CPU @ crossing, ZCLK @ 1.5V
VT = 1.5 V CPU @ crossing, PCI @ 1.5V
2.5
2.5
2.5
3.1
3.3
2.9
3.5
3.5
3.5
ns
ns
ns
Skew1
1Guaranteed by design, not 100% tested in production.
0795D—05/06/05
10
Integrated
Circuit
ICS952702
Systems, Inc.
Electrical Characteristics - CPUCLKODC/T
TA = 0 - 70°C; VDD = 1.7 V +/-5%; CL = 5 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
1
TYP
MAX UNITS
VOH2B
VOL2B
IOL2B
tr2B
Output High Voltage
Output Low Voltage
Output Low Current
Rise Time1
Termination to Vpull-up(external)
Termination to Vpull-up(external)
VOL = 0.3 V
VOL = 20%, VOH = 80%
VOH = 80%, VOL = 20%,
1.2
0.4
V
V
18
mA
ns
ns
0.38
0.44
0.9
0.9
Fall Time1
tf2B
Differential voltage-
VDIF
VDIF
VX
0.4
0.2
V
V
AC1
Differential voltage-
DC1
Differential Crossover
550
45
1200
1250
mV
Voltage1
Duty Cycle1
dt2B
tsk2B
VT = 50%
VT = 50%
51.5
140
55
%
Skew1
200
ps
Jitter Diff, Cycle-to-
tjcyc-cyc2B VT = VX
tjcyc-cyc2B VT = 1.0V
60
250
ps
cycle1
Jitter SE, Cycle-to-
100
250
250
ps
ps
cycle1
Jitter, Absolute1
Notes:
tjabs2B
VT = 50%
-250
1 - Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3 V,+/-5%; CL = 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
VOL1
IOH1
IOL1
CONDITIONS
MIN
2.1
TYP
MAX UNITS
V
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
0.4
-22
57
V
mA
mA
ns
ns
%
16
45
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2.25
2.1
2.5
2.5
55
Fall Time1
tf1
Duty Cycle1
dt1
50
Skew1
tsk1
VT = 1.5 V
170
150
500
500
500
ps
ps
ps
1
tjcyc-cyc
VT = 1.5 V
VT = 1.5 V
Jitter
tjabs1
1Guaranteed by design, not 100% tested in production.
0795D—05/06/05
11
Integrated
Circuit
ICS952702
Systems, Inc.
Electrical Characteristics - AGPCLK, ZCLK
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
CONDITIONS
MIN
TYP
MAX UNITS
MHz
66.66
1
RDSP1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
55
Ω
V
V
1
VOH
2.4
1
VOL
0.55
-33
VOH = 1.0 V
1
Output High Current
Output Low Current
IOH
VOH = 3.135 V
VOL = 1.95 V
VOL = 0.4 V
-33
38
mA
1
IOL
30
2.2
2.2
55
mA
ns
ns
%
1
Rise Time
Fall Time
Duty Cycle
Skew
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.5
0.5
45
2
1
tf1
1.9
50.5
70
1
dt1
1
tsk1
VT = 1.5 V
VT = 1.5 V
250
250
ps
ps
1
tjcyc-cyc
Jitter
240
Electrical Characteristics - REF
TA = 0 - 70°C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
VOL5
IOH5
CONDITIONS
MIN
2.6
TYP
MAX UNITS
V
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
0.4
-22
V
mA
mA
ns
ns
%
IOL5
16
45
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1.6
1.6
53
4
4
Fall Time1
tf5
Duty Cycle1
dt5
tjcyc-cyc5
tjabs5
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
55
210
1000
800
ps
ps
Jitter1
0795D—05/06/05
12
Integrated
Circuit
ICS952702
Systems, Inc.
Electrical Characteristics - IOAPIC
TA = 0 - 70°C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
9
TYP
MAX UNITS
1
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
RDSP4B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -5.5 mA
IOL = 9.0 mA
30
30
Ω
Ω
V
V
1
RDSN4B
9
2
VOH4\B
VOL4B
0.4
-27
VOH = 1.0 V
1
Output High Current
Output Low Current
IOH
VOH = 2.375 V
-27
27
mA
V
OL = 1.2 V
OL = 0.3 V
1
IOL
V
30
1.6
1.6
55
mA
ns
ns
%
1
Rise Time
Fall Time
Duty Cycle
Jitter
tr4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.4
0.4
45
1
1
1
tf4B
1
dt4B
49.8
300
10
tjcyc-cyc
VT = 1.25 V
500
250
ps
ps
1
Tsk4
Skew
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 12_48MHz, 24_48MHz
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
20
TYP
MAX
60
UNITS
1
Output Impedance
Output High Voltage
Output Low Voltage
Ω
V
V
RDSP1
1
IOH = -1 mA
2.4
VOH
1
IOL = 1 mA
0.4
-29
VOL
VOH = 1.0 V
1
Output High Current
Output Low Current
IOH
VOH = 3.135 V
VOL = 1.95 V
-23
29
mA
1
IOL
VOL = 0.4 V
27
4
mA
ns
ns
%
1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
Rise Time
Fall Time
Duty Cycle
Jitter
0.5
0.5
45
1.5
1.5
tr1
1
4
tf1
1
52.8
370
55
500
dt1
1
VT = 1.5 V
ps
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
0795D—05/06/05
13
Integrated
Circuit
ICS952702
Systems, Inc.
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supplyortheGND(logic0)voltagepotential. A10Kilohm(10K)
resistor is used to provide both the solid CMOS programming
voltageneededduringthepower-upprogrammingperiodandto
provide an insignificant load on the output clock during the
subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0795D—05/06/05
14
Integrated
Circuit
ICS952702
Systems, Inc.
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following.All PCI and stoppable PCI_F clocks will latch low in their next
high to low transition.The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
Assertion of PCI_STOP#Waveforms
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion
of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.The final state
of the stopped CPU signals is CPUT=Low and CPUC=High.There is to be no change to the output drive current values.The CPUT
will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
Assertion of CPU_STOP#Waveforms
CPU_STOP#
CPUT
CPUC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
0
Normal
Normal
Float
iref * Mult
0795D—05/06/05
15
Integrated
Circuit
ICS952702
Systems, Inc.
c
300 mil SSOP
In Millimeters
N
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
h
L
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
0.635 BASIC
0.025 BASIC
h x 45°
D
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A
VARIATIONS
D mm.
A1
D (inch)
N
- C -
MIN
MAX
MIN
.620
MAX
.630
48
15.75
16.00
e
SEATING
PLANE
b
Reference Doc.: JEDEC Publication 95, M O-118
.10 (.004) C
300 mil SSOP Package
Ordering Information
ICS952702yFLFT
Example:
ICS 95XXXX y FLF - T
Designation for tape and reel packaging
Annealed Lead Free (optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0795D—05/06/05
16
Integrated
Circuit
ICS952702
Systems, Inc.
Revision History
Rev.
Issue Date Description
Page #
D
5/6/2005 Added LF Ordering Information
16
0795D—05/06/05
17
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