ICS95V850AGT [IDT]
PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.240 INCH, MO-153, TSSOP-48;
| 型号： | ICS95V850AGT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, 0.240 INCH, MO-153, TSSOP-48 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总10页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS95V850
Integrated
Circuit
Systems, Inc.
DDR Phase Lock Loop Clock Driver (60MHz - 210MHz)
RecommendedApplication:
DDR Clock Driver
Pin Configuration
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
ProductDescription/Features:
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
•
•
Low skew, low jitter PLL clock driver
Feedback pins for input to output synchronization
•
•
•
•
Spread Spectrum tolerant inputs
With bypass mode mux
GND
GND
CLKC2
CLKT2
VDD
CLKC7
CLKT7
VDD
Operating frequency 60 to 210 MHz
AC Coupled (Universal) CLK inputs:
- 400 mV switching amplitude
- (LVTTL, LVPELL, LVDS, LVCMOS) standards
translation to SSTL2
NC
NC
CLK_INT
CLK_INC
NC
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
FB_INC
FB_INT
VDD
FB_OUTT
FB_OUTC
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
SwitchingCharacteristics:
•
•
•
•
CYCLE - CYCLE jitter: <60ps
OUTPUT - OUTPUT skew: <60ps
Period jitter:±30ps
DUTY CYCLE: 49.5% - 50.5%
48-Pin TSSOP
6.10mm Body, 0.5mm Pitch
Block Diagram
Functionality
INPUTS
OUTPUTS
PLL State
AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
FB_OUTT
FB_OUTC
GND
GND
L
H
L
L
H
L
L
H
L
Bypassed/Off
Bypassed/Off
H
H
H
CLKT0
CLKC0
2.5V
(nom)
L
H
L
L
H
L
L
H
L
On
On
CLKT1
CLKC1
2.5V
(nom)
H
H
H
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
FB_INT
FB_INC
CLKT5
CLKC5
PLL
CLK_INC
CLK_INT
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
AVDD
CLKT9
CLKC9
0458G—11/21/08
ICS95V850
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
GND
PWR Ground
26, 30, 40, 43, 47,
23, 19, 9, 6, 2
CLK[9:0]
CLK[9:0]
VDD
OUT
OUT
"Complementary" clocks of differential pair outputs
"True" Clock of differential pair outputs
27, 29, 39, 44, 46,
22, 20, 10, 5, 3
4, 11, 21, 28,
34, 38, 45,
PWR Power supply, 2.5V
13
14
16
17
CLK_INT
CLK_INC
AVDD
IN
IN
"True" reference clock input
"Complementary" reference clock input
PWR Analog power supply, 2.5V
AGND
PWR Analog ground
"Complementary" Feedback output, dedicated for external feedback. It
32
FB_OUTC
OUT
OUT
switches at the same frequency as the CLK. This output must be wired
to FB_INC
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT
33
35
FB_OUTT
FB_INT
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error
IN
IN
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error
36
FB_INC
NC
12, 15, 37
No Connects
0458G—11/21/08
2
ICS95V850
Absolute Maximum Ratings
Supply Voltage: (VDD & AVDD) . . . . . . . . . . . . . . . . -0.5V to 3.6V
Input clamp current: IIK (VI < 0 or VI > VDD). . . . . . +/- 50mA
Output clamp current: IOK (VO < 0 or VO > VDD) . . +/- 50mA
Continuous output current: IO (VO = 0 to VDD) . . . . +/- 50mA
Package thermal impedance, theta JA: DGG package +89°C/Ω
StorageTemperature . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Input High Current
Input Low Current
SYMBOL
CONDITIONS
VI = VDD or GND
VI = VDD or GND
MIN
5
TYP
MAX
UNITS
µA
IIH
IIL
5
µA
Operating Supply
Current
IDD2.5 CL = 0pf @ 200MHz
IDDPD CL = 0pf
148
100
mA
µA
High Impedance
Output Current
VDD = 2.7V, Vout = VDD or
IOZ
±10
-1.2
mA
GND
Input Clamp Voltage
VIK
VDD = 2.3V Iin = -18mA
V
V
High-level output
voltage
IOH = -1 mA
IOH = -12 mA
IOL =1 mA
VDD - 0.1
1.7V
VOH
V
0.1
0.6
3.5
V
Low-level output voltage
Input Capacitance1
1Guaranteed by design at 233MHz, not 100% tested in production.
VOL
CIN
IOH =12 mA
V
VI = GND or VDD
2.5
pF
0458G—11/21/08
3
ICS95V850
Recommended Operating Condition
(see note1)
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Supply Voltage
SYMBOL
DD, AVDD
CONDITIONS
MIN
2.3
TYP
2.5
MAX
2.7
UNITS
V
V
V
CLK_INT, CLK_INC, FB_INC
0.4
V
DD/2 - 0.18
Low level input voltage
VIL
CLK_INT, CLK_INC (Universal Input)
-0.3
VDD - 0.4
V
CLK_INT, CLK_INC, FB_INC
VDD/2 + 0.18
0.4
2.1
V
V
High level input voltage
VIH
VIN
CLK_INT, CLK_INC (Universal Input)
VDD + 0.3
VDD + 0.3
DC input signal voltage
(note 2)
-0.3
0.36
0.4
V
V
V
DC - CLK_INT, FB_INT
V
V
DD + 0.6
DD + 0.6
Differential input signal
voltage (note 3)
VID
AC - CLK_INT, FB_INT (Universal Input)
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
High level output
current
VOX
VIX
IOH
IOL
TA
VDD/2 - 0.15
VDD/2 + 0.15
V
(Universal Input)
0.45(VIH - VIL)
0.55(VIH - VIL)
V
-6.4
5.5
85
mA
mA
°C
Low level output current
Operating free-air
temperature
0
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VDD and is the
voltage at which the differential signal must be crossing.
Timing Requirements
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
CONDITIONS
PARAMETER
Operating clock frequency
Input clock duty cycle
SYMBOL
freqop
dtin
MIN
66
TYP
MAX UNITS
210
60
MHz
%
40
CLK stabilization
TSTAB
15
µs
0458G—11/21/08
4
ICS95V850
Switching Characteristics (see note 3)
PARAMETER
Low-to high level
propagation delay time
High-to low level propagation
delay time
SYMBOL
CONDITION
MIN
TYP
MAX UNITS
ns
1
CLK_IN to any output
5.5
5.5
tPLH
1
CLK_IN to any output
ns
tPLL
Period jitter
Tjit (per)
t(jit_hper)
tsl(i)
100MHz to 200MHz
100MHz to 200MHz
-30
-75
1
30
30
4
ps
ps
Half-period jitter
Input clock slew rate
V/ns
V/ns
ps
Output clock slew rate
Cycle to Cycle Jitter1
Phase error
tsl(o)
1
2.5
60
50
60
Tcyc-Tcyc
100MHz to 200MHz
4
-50
0
ps
t(phase error)
Tskew
Output to Output Skew
ps
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula:duty cycle=twH/tc, where
the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
0458G—11/21/08
5
ICS95V850
Parameter Measurement Information
V
DD
V
(CLKC)
R = 60Ω
V
/2
R = 60Ω
DD
V
(CLKC)
ICS95V850
GND
Figure 1. IBIS Model Output Load
V
DD/2
C = 14 pF
ICS95V850
-V
DD/2
SCOPE
R = 10Ω Z = 50Ω
Z = 60Ω
Z = 60Ω
R = 50Ω
(TT)
V
R = 10Ω
Z = 50Ω
R = 50Ω
C = 14 pF
DD/2
V
(TT)
-V
-V
DD/2
NOTE: V
(TT) = GND
Figure 2. Output Load Test Circuit
YX, FB_OUTC
YX, FB_OUTT
t
t
c(n+1)
c(n)
t
= t
± t
jit(cc) c(n) c(n+1)
Figure 3. Cycle-to-Cycle Jitter
0458G—11/21/08
6
ICS95V850
Parameter Measurement Information
CLK_INC
CLK_INT
FB_INC
FB_INT
t
t
( ) n
( ) n+1
n = N
t
1
( ) n
t
=
( )
N
(N is a large number of samples)
Figure 4. Static Phase Offset
YX
#
YX
YX, FB_OUTC
YX, FB_OUTT
t(SK_O)
Figure 5. Output Skew
YX, FB_OUTC
YX, FB_OUTT
YX, FB_OUTC
YX, FB_OUTT
1
fO
1
t(jit_per)
tC(n)
=
-
fO
Figure 6. Period Jitter
0458G—11/21/08
7
ICS95V850
Parameter Measurement Information
YX, FB_OUTC
YX, FB_OUTT
t
t
(hper_n+1)
(hper_n)
1
f
o
t(jit_Hper) t(jit_Hper_n)
1
2xfO
=
-
Figure 7. Half-Period Jitter
80%
80%
V
, V
ID OD
20%
20%
Clock Inputs
and Outputs
Rise t
Fall t
sl
sl
Figure 8. Input and Output Slew Rates
0458G—11/21/08
8
ICS95V850
Recommended Layout for the ICS95V850
General Layout Precautions:
Use copper flooded ground on the top signal layer under the
clock buffer The area under U1 on the right is an example.
Flood over the ground vias.
1) Use power vias for power and ground. Vias 20 mil or
larger in diameter have lower high frequency impedance.
Vias for signals may be minimum drill size.
2) Make all power and ground traces are as wide as the via
pad for lower inductance.
3) VAA for pin 16 has a low pass RC filter to decouple the
digital and analog supplies. The 4.7uF capacitors may be
replaced with a single low ESR device with the same
total capacitance. VAA is routed on a outside signal
layer. Do not cut a power or ground plane and route in it.
4) Notice that ground vias are never shared.
5) When ever possible, VCC (net V2P5 in the schematic)
pins have a decoupling capacitor. Power is always routed
from the plane connection via to the capacitor pad to the
VCC pin on the clock buffer. Moats or plane cuts are not
used to isolate power.
6) Differential mode clock output traces are routed:
a. With a ground trace between the pairs. Trace is
grounded on both ends.
b. Without a ground trace, clock pairs are routed with a
separation of at least 5 times the thickness of the
dielectric. If the dielectric thickness is 4.5 mil, the
trace separation is at least 18 mils.
7) Terminate differential CLK_IN and FB_IN traces after
routing to buffer pads.
Component Values:
Ref Desg. Value
Description
CERAMIC MLC
Package
0603
C1,C4,C5,
C7,C11,C12
C2,C3,C8,
C9
.01uF
4.7uF
.22uF
CERAMIC MLC
1206
C10
CERAMIC MLC
0603
0603
0603
C6
2200pF CERAMIC MLC
R9,R12
120 Ω
R9
U1
0603
4.7 Ω
ICS95V850
TSSOP48
0458G—11/21/08
9
ICS95V850
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
E1
E
INDEX
AREA
c
1
22
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
a
D
E1
e
6.00
6.20
.236
0.020 BASIC
.244
0.50 BASIC
L
0.45
0.75
.018
.030
A
N
SEE VARIATIONS
SEE VARIATIONS
A2
0°
--
8°
0.10
0°
--
8°
.004
α
aaa
A1
- CC --
VARIATIONS
e
SEATING
PLANE
b
D mm.
D (inch)
N
aaa
C
MIN
MAX
12.60
MIN
.488
MAX
.496
48
12.40
Reference Doc.: JEDEC Publication 95, M O-153
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
10 - 0 0 3 9
(240 mil)
Ordering Information
95V850yLFGT
Example:
XXXX y G (LF) - T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
0458G—11/21/08
10
相关型号：
ICS95V857AG-130-T
PLL Based Clock Driver, 95V Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48
IDT
ICS95V857AG-130T
PLL Based Clock Driver, 95V Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48
IDT
ICS95V857AG-T
PLL Based Clock Driver, 95V Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48
IDT
ICS95V857AGI-T
PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48
IDT
©2020 ICPDF网 联系我们和版权申明