ICS95V857CK [IDT]
PLL Based Clock Driver, 95V Series, 10 True Output(s), 0 Inverted Output(s), MLF-40;
| 型号： | ICS95V857CK |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 95V Series, 10 True Output(s), 0 Inverted Output(s), MLF-40 |
| 文件： | 总15页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems,Inc.
ICS95V857-XXX
Preliminary Product Preview
2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz)
RecommendedApplication:
Pin Configuration
DDR Memory Modules / Zero Delay Board Fan Out
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ProductDescription/Features:
•
•
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL2)
GND
GND
•
•
Feedback pins for input to output synchronization
PD#forpowermanagement
CLKC2
CLKT2
VDD
CLKC7
CLKT7
VDD
•
•
•
SpreadSpectrum-tolerantinputs
Auto PD when input signal removed
Choice of static phase offset available,
for easy board tuning;
VDD
PD#
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
-XXX = device pattern number for options listed
below.
- ICS95V857 ............. 0ps
-ICS95V857-130 .. +50ps
Specifications:
48-Pin TSSOP/TVSOP
6.10 mm Body, 0.50 mm Pitch = TSSOP
•
Meets or exceeds JEDEC standard #82-1 for
registered DDR clock driver.
•
•
Meets or exceeds proposed DDR1-400 specifications
Covers all DDR1 speed grades
4.40 mm Body, 0.40 mm Pitch = TVSOP
SwitchingCharacteristics:
•
•
•
•
CYCLE - CYCLE jitter (>100MHz):<50ps
OUTPUT - OUTPUT skew: <30ps
Output Rise and Fall Time: 650ps - 950ps
DUTY CYCLE: 49.5% - 50.5%
Block Diagram
FB_OUTT
FB_OUTC
CLKT0
CLKC0
Functionality
CLKT1
CLKC1
INPUTS
OUTPUTS
PLL State
Control
CLKT2
CLKC2
AVDD PD# CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
PD#
Logic
GND
GND
H
H
L
H
L
L
H
L
L
H
L
Bypassed/off
Bypassed/off
CLKT3
CLKC3
H
H
H
CLKT4
CLKC4
2.5V
(nom)
L
L
L
H
L
H
L
Z
Z
L
Z
Z
H
L
Z
Z
L
Z
Z
H
L
off
off
on
on
off
2.5V
(nom)
FB_INT
FB_INC
CLKT5
CLKC5
2.5V
(nom)
PLL
CLK_INC
CLK_INT
H
H
X
H
L
CLKT6
CLKC6
2.5V
(nom)
H
H
Z
H
Z
CLKT7
CLKC7
2.5V
(nom)
<20MHz)(1)
Z
Z
CLKT8
CLKC8
CLKT9
CLKC9
0674I—03/28/03
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are
subject to change without notice.
ICS95V857-XXX
Preliminary Product Preview
Pin Configuration
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
56-Ball BGA
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
CLKT0
CLKC1
GND
CLKT2
VDD
CLK_INT CLK_INC
VDD
AGND
CLKC3
CLKT4
CLKC0
CLKT1
GND
CLKC2
VDD
GND
VDD
NC
NC
NB
NB
NC
NC
VDD
GND
GND
VDD
NC
NC
NB
NB
NC
NC
VDD
GND
CLKC5
CLKT6
GND
CLKC7
VDD
FB_INC
FB_OUTC
GND
CLKT8
CLKC9
CLKT5
CLKC6
GND
CLKT7
PD#
FB_INT
VDD
FB_OUTT
CLKC8
CLKT9
AVDD
GND
CLKT3
CLKC4
K
40
30
29
1
GND
CLKC7
CLKC2
CLKT2
VDD
CLKT7
VDD
PD#
CLK_INT
CLK_INC
VDD
FB_INT
FB_INC
VDD
ICS95V857
AVDD
VDD
AGND
GND 10
FB_OUTC
FB_OUTT
21
11
20
40-Pin MLF
0674I—03/28/03
2
ICS95V857-XXX
Preliminary Product Preview
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
4, 11, 12, 15, 21,
28, 34, 38, 45,
VDD
GND
PWR Power supply 2.5V
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
PWR Ground
16
17
AVDD
AGND
PWR Analog power supply, 2.5V
PWR Analog ground.
27, 29, 39, 44, 46,
22, 20, 10, 5, 3
CLKT(9:0)
CLKC(9:0)
OUT
OUT
"True" Clock of differential pair outputs.
26, 30, 40, 43, 47,
23, 19, 9, 6, 2
"Complementary" clocks of differential pair outputs.
14
13
CLK_INC
CLK_INT
IN
IN
"Complementary" reference clock input
"True" reference clock input
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
33
FB_OUTC
OUT
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT.
32
36
FB_OUTT
FB_INT
OUT
IN
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
35
37
FB_INC
PD#
IN
IN
Power Down. LVCMOS input
This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels.
The ICS95V857 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT,
FB_OUTC).The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC) the 2.5-V LVCMOS input (PD#) and the Analog Power input (AVDD).When input (PD#) is low while power is
applied, the receivers are disabled, the PLL is turned off and the differential clock outputs areTri-Stated.When AVDD
is grounded, the PLL is turned off and bypassed for test purposes.
WhentheinputfrequencyislessthantheoperatingfrequencyofthePLL, appproximately20MHz, thedevicewillenter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low.When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputswillbeenabledandPLLwillobtainphaselockbetweenthefeedbackclockpair(FB_INT, FB_INC) andtheinput
clock pair (CLK_INC, CLK_INT).
The PLL in the ICS95V857 clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) provide high-performance, low-skew, low-jitter output differential clocks (CLKT [0:9], CLKC [0:9]). The
ICS95V857 is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
The ICS95V857 is characterized for operation from 0°C to 85°C.
0674I—03/28/03
3
ICS95V857-XXX
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD). . . . . . . . . . . -0.5V to 4.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V
Ambient OperatingTemperature . . . . . . . . . . 0°C to +85°C
StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These
ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Input High Current
Input Low Current
Operating Supply
Current
SYMBOL
CONDITIONS
VI = VDD or GND
VI = VDD or GND
MIN
5
TYP
MAX
UNITS
µA
IIH
IIL
5
µA
IDD2.5 CL = 0pf @ 200MHz
IDDPD CL = 0pf
145
100
mA
µA
High Impedance
Output Current
VDD = 2.7V, Vout = VDD or
IOZ
±10
-1.2
mA
GND
Input Clamp Voltage
VIK
VDD = 2.3V Iin = -18mA
V
V
High-level output
voltage
IOH = -1 mA
VDD - 0.1
1.7V
VOH
I
I
I
OH = -12 mA
OL =1 mA
V
0.1
0.6
3.5
V
Low-level output voltage
Input Capacitance1
1Guaranteed by design at 233MHz, not 100% tested in production.
VOL
CIN
OH =12 mA
V
VI = GND or VDD
2.5
pF
0674I—03/28/03
4
ICS95V857-XXX
Preliminary Product Preview
Recommended Operating Condition
(see note1)
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Supply Voltage
SYMBOL
VDD, AVDD
CONDITIONS
MIN
2.3
TYP
MAX
2.7
UNITS
V
V
V
V
V
CLKT, CLKC, FB_INC
VDD/2 - 0.18
0.7
Low level input voltage
High level input voltage
VIL
VIH
PD#
-0.3
VDD/2 + 0.18
1.7
CLKT, CLKC, FB_INC
PD#
V
DD + 0.6
VDD
DC input signal voltage
(note 2)
-0.3
V
Differential input signal
voltage (note 3)
DC - CLKT, FB_INT
AC - CLKT, FB_INT
0.36
0.7
V
DD + 0.6
V
V
VID
VDD + 0.6
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
High level output
current
VOX
VIX
IOH
VDD/2 - 0.15
VDD/2 - 0.2
VDD/2 + 0.15
V
V
VDD/2 + 0.2
-4.5
mA
Low level output current
IOL
SR
TA
4.5
4
mA
V/ns
°C
Input slew rate
Operating free-air
temperature
1
0
85
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VCC and is the
voltage at which the differential signal must be crossing.
0674I—03/28/03
5
ICS95V857-XXX
Preliminary Product Preview
Timing Requirements
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
CONDITIONS
PARAMETER
SYMBOL
freqop
MIN
33
MAX UNITS
2.5V+0.2V @ 25oC
Max clock frequency
233
170
60
MHz
MHz
%
Application Frequency
Range
freqApp
dtin
95
40
2.5V+0.2V @ 25oC
Input clock duty cycle
CLK stabilization
TSTAB
100
µs
Switching Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX UNITS
Low-to high level
1
CLK_IN to any output
5.5
5.5
ns
ns
tPLH
propagation delay time
High-to low level propagation
delay time
1
CLK_IN to any output
tPLL
Output enable time
Output disable time
Period jitter
tEN
tdis
PD# to any output
5
5
ns
ns
PD# to any output
Tjit (per)
t(jit_hper)
tsl(i)
100/125/133/167/200MHz
100/133/167/200MHz
-40
-50
1
40
50
ps
Half-period jitter
ps
Input clock slew rate
4
V/ns
V/ns
ps
Output clock slew rate
tsl(o)
1
2.5
50
Cycle to Cycle Jitter1
Phase error
Tcyc-Tcyc
100/125/133/167/200MHz
4
-50
0
50
ps
t(phase error)
Tskew
Output to Output Skew
Duty cycle
30
ps
2
100MHz to 200MHz
49.5
650
50.5
950
%
DC
Rise Time, Fall Time
tr, tf
Load = 120Ω/16pF
800
ps
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula:duty cycle=twH/tc, where
the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
0674I—03/28/03
6
ICS95V857-XXX
Preliminary Product Preview
Parameter Measurement Information
V
DD
V
(CLKC)
R = 60Ω
R = 60Ω
V
/2
DD
V
(CLKC)
ICS95V857
GND
Figure 1. IBIS Model Output Load
V
DD/2
C = 14 pF
ICS95V857
-V
DD/2
SCOPE
R = 10Ω Z = 50Ω
Z = 60Ω
Z = 60Ω
R = 50Ω
(TT)
V
R = 10Ω
Z = 50Ω
R = 50Ω
C = 14 pF
DD/2
V
(TT)
-V
-V
DD/2
NOTE: V
(TT) = GND
Figure 2. Output Load Test Circuit
YX, FB_OUTC
YX, FB_OUTT
t
t
c(n+1)
c(n)
t
= t
± t
jit(cc) c(n) c(n+1)
Figure 3. Cycle-to-Cycle Jitter
0674I—03/28/03
7
ICS95V857-XXX
Preliminary Product Preview
Parameter Measurement Information
CLK_INC
CLK_INT
FB_INC
FB_INT
t
t
(
) n
(
) n+1
n = N
å
=
)
t
1
(
) n
t
(
N
(N is a large number of samples)
Figure 4. Static Phase Offset
YX
#
YX
YX, FB_OUTC
YX, FB_OUTT
t(SK_O)
Figure 5. Output Skew
YX, FB_OUTC
YX, FB_OUTT
YX, FB_OUTC
YX, FB_OUTT
1
fO
1
fO
t(jit_per) =
tC(n) -
Figure 6. Period Jitter
0674I—03/28/03
8
ICS95V857-XXX
Preliminary Product Preview
Parameter Measurement Information
YX, FB_OUTC
YX, FB_OUTT
t
t
(hper_n+1)
(hper_n)
1
f
o
t(jit_Hper) t(jit_Hper_n)
1
2xfO
=
-
Figure 7. Half-Period Jitter
80%
80%
V
, V
ID OD
20%
20%
Clock Inputs
and Outputs
Rise t
Fall t
sl
sl
Figure 8. Input and Output Slew Rates
0674I—03/28/03
9
ICS95V857-XXX
Preliminary Product Preview
In Millimeters
COMMON DIMENSIONS COMMON DIMENSIONS
In Inches
c
N
SYMBOL
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
L
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
22
E1
e
6.00
0.50 BASIC
6.20
.236
.244
a
0.020 BASIC
D
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
VARIATIONS
A1
D mm.
D (inch)
- CC --
N
MIN
MAX
12.60
MIN
.488
MAX
.496
e
SEATING
PLANE
48
12.40
b
Reference Doc.: JEDEC Publication 95, M O-153
aaa
C
10-0039
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
(240 mil)
Ordering Information
ICS95V857yGT, ICS95V857yG-130
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0674I—03/28/03
10
ICS95V857-XXX
Preliminary Product Preview
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.13
0.09
MAX
1.20
0.15
1.05
0.23
0.20
MIN
--
.002
.032
.005
.0035
MAX
.047
.006
.041
.009
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
1
22
E1
e
4.30
4.50
.169
.177
α
D
0.40 BASIC
0.016 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
a
aaa
0°
--
8°
0.08
0°
--
8°
.003
A
A2
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
MIN
9.60
MAX
9.80
MIN
.378
MAX
.386
e
SEATING
PLANE
b
48
Reference Doc.: JEDEC Publication 95, M O-153
aaa
C
10-0037
4.40 mm. Body, 0.40 mm. pitch TSSOP
(16 mil)
(173 mil)
Ordering Information
ICS95V857yL-130
Example:
ICS XXXX y L - PPP - T
Designation for tape and reel packaging
Pattern Number
Package Type
L = TSSOP (TVSOP)
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS = Standard Device
0674I—03/28/03
11
ICS95V857-XXX
Preliminary Product Preview
Symbol
Common Dimensions
A
A1
A2
A3
D
-
0.00
-
0.85
0.90
0.05
0.80
0.01
0.65
0.20 REF
6.00 BSC
5.75 BSC
6.00 BSC
5.75 BSC
D1
E
40-Pin MLF
E1
Q
12
P
0.24
0.13
0.42
0.17
0.60
0.23
R
Pitch Varation D
e
N
0.50 BSC
40
Nd
Ne
L
10
10
0.30
0.18
0.00
2.75
2.75
0.40
0.23
0.20
2.90
2.90
0.50
0.30
0.45
3.05
3.05
Ordering Information
b
Q
ICS95V857yKT
D2
E2
Example:
ICS XXXX y K - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Package Type
K = MLF
Revision Designator (will not correlate with datasheet revision)
DeviceType (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0674I—03/28/03
12
ICS95V857-XXX
Preliminary Product Preview
0.40 DIA.
± 0.15
TYP.
Seating
Plane
SYMBOL
MIN.
0.86
0.15
0.71
4.40
6.90
NOM.
0.93
0.18
0.75
4.50
MAX.
1.00
0.21
0.79
4.60
7.10
A1
A
A1
A2
D
E
I
3 2 1
A
B
C
D
E
F
G
H
I
7.00
E
0.625 REF.
0.575 REF.
6X10
J
M
J
TOP VIEW
D
aaa
bbb
ccc
b
0.10
0.10
0.10
0.45
0.15 MIN.
1.00 MAX.
0.35
0.40
e
0.65 TYP.
Ordering Information
ICS95V857yHT
Example:
ICS XXXX y H - T
Designation for tape and reel packaging
Package Type
H = BGA
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0674I—03/28/03
13
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95V857C (DDR2 PLL)
Description
Market Group
DIMM
Additional Info
Related Orderable Parts
1 2
Attributes
Package
95V857CG
95V857CG8
95V857CGLF
95V857CGLF8
95V857CK
95V857CK8
TSSOP 48 (PA48)
TSSOP 48 (PA48)
TSSOP 48 (PAG48)
TSSOP 48 (PAG48)
VFQFPN 40 (NL40)
VFQFPN 40 (NL40)
NA
C
NA
C
NA
C
NA
C
NA
C
NA
C
Speed
Temperature
Voltage
Status
1.8 V
Active
No
1.8 V
Obsolete
No
1.8 V
Active
No
1.8 V
Obsolete
No
1.8 V
Active
No
1.8 V
Obsolete
No
Sample
Minimum Order
Quantity
304
38
1000
1000
304
38
1000
1000
490
490
1000
1000
Factory Order
Increment
1 2
Related Documents
Type
Title
Size
Revision Date
Datasheet
95V857C Datasheet
136 KB
09/05/2006
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相关型号：
ICS95V857CK-T
PLL Based Clock Driver, 95V Series, 10 True Output(s), 0 Inverted Output(s), PLASTIC, MLF-40
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ICS95V857CK8
PLL Based Clock Driver, 95V Series, 10 True Output(s), 0 Inverted Output(s), MLF-40
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ICS95V857CL-T
PLL Based Clock Driver, 95V Series, 10 True Output(s), 0 Inverted Output(s), PDSO48, 4.40 MM, 0.40 MM PITCH, MO-153, TVSOP-48
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