ICS9FG1200YF-1LF-T [IDT]
Processor Specific Clock Generator, 400MHz, PDSO56, 0.300 INCH, 0.635 MM PITCH, MO-118, SSOP-56;
| 型号： | ICS9FG1200YF-1LF-T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 400MHz, PDSO56, 0.300 INCH, 0.635 MM PITCH, MO-118, SSOP-56 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总23页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2
& FBD
ICS9FG1200D-1
Description
Features/Benefits
ICS9FG1200D-1 follows the Intel DB1200GS Differential Buffer
Specification. This buffer provides 12 output clocks for CPU Host
Bus, PCIe Gen2, or Fully Buffered DIMM applications.The outputs
are configured with two groups. Both groups (DIF 9:0) and (DIF
11:10) can be equal to or have a gear ratio to the input clock. A
differential CPU clock from a CK410B+ main clock generator,
such as the ICS932S421, drives the ICS9FG1200D-1. The
ICS9FG1200D-1 can provide outputs up to 400MHz.
•
•
•
Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)
Power up default is all outputs in 1:1 mode
DIF_(9:0) can be “gear-shifted” from the input CPU Host
Clock
•
DIF_(11:10) can be “gear-shifted” from the input CPU
Host Clock
•
•
•
•
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
Key Specifications
•
DIF output cycle-to-cycle jitter < 50ps
•
DIF output-to-output skew < 100ps across all outputs in 1:1
mode
•
•
56-pin SSOP/TSSOP package
RoHS compliant packaging
Functional Block Diagram
OE#
SPREAD
COMPATIBLE
1:1 PLL
2
STOP
DIF(11:10)
LOGIC
10
OE(9:0)#
SPREAD
COMPATIBLE
GEARING PLL
CLK_IN
10
STOP
DIF(9:0)
LOGIC
CLK_IN#
HIGH_BW#
FS_A_410
VTT_PWRGD#/PD
SMB_A0
SMB_A1
CONTROL
LOGIC
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
IREF
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
1
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
Pin Configuration
HIGH_BW# 1
CLK_IN 2
CLK_IN# 3
SMB_A0 4
OE0# 5
56 VDDA
55 GNDA
54 IREF
53 OE10_11#
52 DIF_11
51 DIF_11#
50 VDD
DIF_0 6
DIF_0# 7
OE1# 8
49 GND
DIF_1 9
DIF_1# 10
VDD 11
48 DIF_10
47 DIF_10#
46 FS_A_410
45 VTT_PWRGD#/PD
44 OE9#
43 DIF_9
42 DIF_9#
41 OE8#
40 DIF_8
39 DIF_8#
38 VDD
37 GND
36 DIF_7
GND 12
DIF_2 13
DIF_2# 14
OE2# 15
DIF_3 16
DIF_3# 17
OE3# 18
DIF_4 19
DIF_4# 20
OE4# 21
VDD 22
35 DIF_7#
34 OE7#
GND 23
DIF_5 24
DIF_5# 25
OE5# 26
SMB_A1 27
SMBDAT 28
33 DIF_6
32 DIF_6#
31 OE6#
30 SMB_A2_PLLBYP#
29 SMBCLK
56-pin SSOP & TSSOP
Power Groups
Pin Number
Description
VDD
56
11,22,38,50
GND
55
12,23,37,49
Main PLL, Analog
DIF clocks
Functionality at Power Up (PLL Mode)
CLK_IN (CPU FSB)
MHz
DIF_(11:0)
FS_A_4101
MHz
1
0
100 <= CLK_IN < 200
200<= CLK_IN <= 400
CLK_IN
CLK_IN
1. FS_A_410 is a low-threshold input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
2
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
Pin Description
PIN # PIN NAME
PIN TYPE DESCRIPTION
3.3V input for selecting PLL Band Width
0 = High, 1= Low
1
HIGH_BW#
IN
2
3
4
CLK_IN
CLK_IN#
SMB_A0
IN
IN
IN
Input for reference clock.
"Complementary" reference clock input.
SMBus address bit 0 (LSB)
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
5
OE0#
IN
6
7
DIF_0
DIF_0#
OUT
OUT
8
OE1#
IN
9
DIF_1
DIF_1#
VDD
GND
DIF_2
DIF_2#
OUT
OUT
PWR
PWR
OUT
OUT
10
11
12
13
14
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 4
1 = tri-state outputs, 0 = enable outputs
Power supply, nominal 3.3V
15
OE2#
IN
16
17
DIF_3
DIF_3#
OUT
OUT
18
OE3#
IN
19
20
DIF_4
DIF_4#
OUT
OUT
21
OE4#
IN
22
23
24
25
VDD
GND
DIF_5
DIF_5#
PWR
PWR
OUT
OUT
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
SMBus address bit 1
26
OE5#
IN
27
28
SMB_A1
SMBDAT
IN
I/O
Data pin of SMBUS circuitry, 5V tolerant
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
3
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
Pin Description (continued)
PIN # PIN NAME
Type
Pin Description
29
SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
SMBus address bit 2. When Low, the part operates as a fanout buffer
with the PLL bypassed. When High, the part operates as a zero-delay
buffer (ZDB) with the PLL operating.
30
SMB_A2_PLLBYP#
IN
0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
31
OE6#
IN
32
33
DIF_6#
DIF_6
OUT
OUT
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
34
OE7#
IN
35
36
37
38
39
40
DIF_7#
DIF_7
GND
VDD
DIF_8#
DIF_8
OUT
OUT
PWR
PWR
OUT
OUT
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
41
OE8#
IN
42
43
DIF_9#
DIF_9
OUT
OUT
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
Vtt_PwrGd# is an active low input used to determine when latched
inputs are ready to be sampled. PD is an asynchronous active high
input pin used to put the device into a low power state. The internal
clocks, PLLs and the crystal oscillator are stopped.
3.3V tolerant low threshold input for CPU frequency selection. This
pin requires CK410 FSA. Refer to input electrical characteristics for
Vil_FS and Vih_FS threshold values.
44
OE9#
IN
45
VTT_PWRGD#/PD
IN
46
FS_A_410
IN
47
48
49
50
51
52
DIF_10#
DIF_10
GND
VDD
DIF_11#
DIF_11
OUT
OUT
PWR
PWR
OUT
OUT
0.7V differential complement clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling output pairs 10 and 11.
1 = tri-state outputs, 0 = enable outputs
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
53
OE10_11#
IN
54
IREF
OUT
55
56
GNDA
VDDA
PWR
PWR
Ground pin for the PLL core.
3.3V power for the PLL core.
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
4
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
9FG1200-1 Programmable Gear Ratios
(FS_A#)
CLK_IN
(CPU FSB)
MHz
Geared DIF
Outputs
MHz
Byte 0, Byte 0, Byte 0, Byte 0, Byte 0,
bit 4
FS4
0
0
Gear
Ratio n/M
1.333
bit 3
FS3
0
0
0
0
0
0
bit 2
FS2
0
0
0
0
1
1
bit 1
FS1
0
0
1
1
0
0
bit 0
FS0
0
1
0
1
0
1
M
3
3
1
3
3
1
n
4
5
2
8
Notes
100.00
100.00
100.00
100.00
100.00
100.00
133.33
166.67
200.00
266.67
333.33
400.00
1.667
2.000
2.667
3.333
0
0
0
0
10
4
4.000
133.33
133.33
133.33
133.33
133.33
166.67
200.00
266.67
333.33
400.00
4
2
1
2
1
5
3
2
5
3
1.250
1.500
1.250
1.500
3.000
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
1
1
1,3
1
166.67
166.67
166.67
160.00
166.67
166.67
133.33
200.00
266.67
320.00
333.33
400.00
5
5
5
4
6
8
0.800
1.200
1.600
0
0
0
1
1
1
0
1
1
1
0
0
1
0
1
1
2
2.000
0
1
1
1
0
1,2
5
3
6
3
3
1
12
2
5
4
5
2.400
0.667
0.833
1.333
1.667
2.000
0
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
200.00
200.00
200.00
200.00
200.00
133.33
166.67
266.67
333.33
400.00
1
1
1
1
1
2
266.67
266.67
320.00
266.67
133.33
166.67
200.00
200.00
2
1
0.500
1
0
1
0
1
1
8
5
0.625
1
0
1
1
0
1, 6
4
5
3
2
0.750
0.400
1
1
0
1
1
0
1
0
1
0
1
1
333.33
320.00
333.33
333.33
133.33
160.00
166.67
200.00
2
1
0.500
1
1
0
0
1
1,5
5
3
0.600
1
1
0
1
0
1
1,4
1
1
1
1
400.00
400.00
400.00
400.00
400.00
133.33
160.00
166.67
320.00
333.33
3
5
12
5
1
2
5
4
5
0.333
0.400
0.417
0.800
0.833
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
6
Notes:
1. Targetted input/output frequency pairs
2. This Gear is also used for 160MHz/320 MHz.
3. Gear Ratio 5/4 is power up default for FS_A_410 = 1
4. Gear Ratio 3/1 is power up default for FS_A_410 = 0
5. This Gear is also used for 400MHz/200MHz
6. This Gear is also used for 320MHz/200MHz
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
5
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
9FG1200-1 1:1 PLL Programming
Byte 8,
Byte 8,
Byte 8,
CLK_IN
(CPU FSB)
MHz
1:1 DIF
Outputs
MHz
bit 2
FSC
bit 1
FSB
bit 0
FS_A_410
Notes
1
0
0
0
0
1
0
0
1
1
0
0
1
1
1
0
0
0
100.00
133.33
166.67
200.00
266.67
333.33
400.00
100.00
133.33
166.67
200.00
266.67
333.33
400.00
3
3
1
3
3
3
2
1
1
0
1
1
1
Reserved
Notes:FS_A_410 = 1
1. Powerup Default for FS_A_410 = 1
2. Powerup Default for FS_A_410 = 0
3. Setting the exact FSB frequency after Power up is required for best phase noise performance.
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
6
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS Notes
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
VDD_A
VDD_In
GND - 0.5
GND - 0.5
VDD + 0.5V
V
V
°C
°C
°C
V
1
1
V
DD + 0.5V
1
1
1
1
Storage Temperature
Ambient Operating Temp
Case Temperature
Ts
Tambient
Tcase
-65
0
150
70
115
Input ESD protection
ESD prot
Human Body Model
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
2
TYP
MAX
UNITS Notes
Input High Voltage
Input Low Voltage
Input High Current
VIH
VIL
IIH
3.3 V +/-5%, except CLK_IN
VDD + 0.3
V
V
1
1
3.3 V +/-5%, except CLK_IN VSS - 0.3
0.8
5
VIN = VDD
VIN = 0 V; Inputs with no pull-
up resistors
-5
uA
Input Low Current
IIL1
-5
uA
Low Threshold Input-
High Voltage
3.3 V +/-5%, Applies to
FS_A_410 pin
VIH_FS
VIL_FS
0.7
VDD + 0.3
0.35
V
1
1
Low Threshold Input-
Low Voltage
3.3 V +/-5%, Applies to
FS_A_410 pin
VSS - 0.3
V
Operating Current
IDD3.3OP
IDD3.3PD
Fi
all outputs driven
375
24
400
7
mA
mA
MHz
nH
1
1
3
1
1
1
Powerdown Current
Input Frequency
Pin Inductance
all differential pairs tri-stated
VDD = 3.3 V
100
30
Lpin
CIN
Logic Inputs
6
pF
Input Capacitance
Clk Stabilization
COUT
Output pin capacitance
5
pF
From VDD Power-Up or de-
assertion of PD# to 1st clock
Triangular Modulation
DIF output enable after
PD# de-assertion
TSTAB
1.8
ms
1
Modulation Frequency
Tdrive_PD#
33
kHz
us
1
1
300
Tfall_Pd#
Trise_Pd#
SMBus Voltage
PD# fall time of
PD# rise time of
Maximum input voltage
5
5
5.5
0.4
ns
ns
V
1
2
1
1
VMAX
VOL
Low-level Output Voltage
Current sinking at
VOL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
@ IPULLUP
V
IPULLUP
TRI2C
4
mA
ns
1
1
1
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
1000
300
TFI2C
ns
Clock/Data Fall Time
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
7
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω
PARAMETER
SYMBOL
Zo1
CONDITIONS
MIN
TYP
MAX
850
UNITS NOTES
Current Source Output
Impedance
VO = Vx
3000
1
Ω
Statistical measurement on
single ended signal using
oscilloscope math function.
Measurement on single ended
signal using absolute value.
Voltage High
Voltage Low
VHigh
VLow
660
1,3
1,3
mV
-150
150
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
1150
1
1
1
mV
mV
mV
-300
250
550
140
Variation of crossing over all
edges
see Tperiod min-max values
400MHz nominal
Crossing Voltage (var)
Long Accuracy
d-Vcross
ppm
1
-300
300
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
7.5400
10.0030
10.0533
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
Average period
Tperiod
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
Tabsmin
Absolute min period
tr
tf
d-tr
d-tf
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
700
700
125
125
VOH = 0.525V VOL = 0.175V
175
1
1
1
Measurement from differential
wavefrom
PLL mode,
from differential wavefrom
dt3
Duty Cycle
45
55
50
50
%
ps
ps
1
tJCYC-CYC
tJBYP
1,4,5
1,4
Jitter, Cycle to cycle
Bypass mode as additive jitter
Notes:
1.Guaranteed by design and characterization, not 100% tested in production.
2. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that the input frequency meets CK410B+ accuracy requirements
3.IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
4. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
5. Measured from differential cross-point to differential cross-point
6. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
8
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
Electrical Characteristics - Skew and Differential Jitter Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
Group
Parameter
Description
Input-to-Output Skew in PLL mode (1:1 only),
nominal value @ 25°C, 3.3V
Input-to-Output Skew in Bypass mode (1:1 only),
nominal value @ 25°C, 3.3V
Min
Typ
Max Units
Notes
1,2,4,5,8,
12
1,2,3,5,
12
1,2,4,5,6,
10,12
1,2,3,4,5,
tSPO_PLL
CLK_IN, DIF[x:0]
-500
140
500
4.5
ps
ns
ps
ps
ps
ps
ps
tPD_BYP
∆tSPO_PLL
∆tPD_BYP
tSKEW_G2
tSKEW_G10
tSKEW_A12
CLK_IN, DIF[x:0]
CLK_IN, DIF [x:0]
CLK_IN, DIF [x:0]
DIF[11:10]
2.5
3.1
270
470
10
Input-to-Output Skew Variation in PLL mode
(over specified voltage / temperature operating ranges)
Input-to-Output Skew Variation in Bypass mode
(over specified voltage / temperature operating ranges)
Output-to-Output Skew Group of 2
|350|
|500|
25
6,10,12
1,2,12
1,2,12
(Common to Bypass and PLL mode)
Output-to-Output Skew Group of 10
(Common to Bypass and PLL mode)
DIF[9:0]
40
50
Output-to-Output Skew across all 12 outputs (Common to
Bypass and PLL mode - all outputs at same gear)
Differential Phase Jitter (RMS Value)
DIF[11:0]
80
100
1,2,3,12
tJPH
DIF[11:0]
DIF[11:0]
5
10
80
ps
ps
1,4,7,12
1,4,9,12
tSSTERROR
Differential Spread Spectrum Tracking Error (peak to peak)
40
jpeak-hibw
jpeak-lobw
PLL Jitter Peaking
PLL Jitter Peaking
(HIGH_BW# = 0)
0
0
2.15
1.2
2.5
2
dB
dB
11,12
11,12
(HIGH_BW# = 1)
pllHIBW
pllLOBW
PLL Bandwidth
PLL Bandwidth
(HIGH_BW# = 0)
(HIGH_BW# = 1)
2
3.6
1.2
4
MHz
MHz
12,13
12,13
0.7
1.4
NOTES on Skew and Differential Jitter Parameters:
1. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2. Measured from differential cross-point to differential cross-point
3. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4. This parameter is deterministic for a given device
5. Measured with scope averaging on to find mean value.
6. Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device.
7. This parameter is measured at the outputs of two separate 9FG1200D-1 devices driven by a single CK410B+. The 9FG1200D-1 must be set to high bandwidth. Differential
phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the affects of spread spectrum). Target ranges of consideration are agents with
BW of 1-22MHz and 11-33MHz.
8. t is the period of the input clock
9. Differential spread spectrum tracking error is the difference in spread spectrum tracking between two 9FG1200D-1 devices This parameter is measured at the outputs of two
separate 9FG1200D-1 devices driven by a single CK410B+ in Spread Spectrum mode. The 9FG1200D-1 must set to high bandwidth. The spread spectrum characterisitics are
: maximum of 0.5%, 30 to 33KHz modulation frequency, linear profile.
10. This parameter is an absolute value. It is not a double-sided figure.
11. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
12. Guaranteed by design and characterization, not 100% tested in production.
13. Measured at 3 db down or half power point.
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
9
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
Electrical Characteristics - Phase Jitter
PARAMETER
SYMBOL
CONDITIONS
PCIe Gen 1 REFCLK phase jitter
(including PLL BW 8 - 16 MHz,
ζ = 0.54,
MIN
TYP. MAX UNITS
NOTES
1,2,3
tjphPCIe1
43/37
86
ps
Td=10 ns, Ftrk=1.5 MHz )
PCIe Gen 2 REFCLK phase jitter
(including PLL BW 8 - 16 MHz,
ζ = 0.54, Td=12 ns)
Lo-band content
(10kHz to 1.5MHz)
PCIe Gen 2 REFCLK phase jitter
(including PLL BW 8 - 16 MHz,
ζ = 0.54, Td=12 ns)
tjphPCIe2Lo
1.2/1.3
3
ps rms
1,2
1,2
Jitter, Phase
tjphPCIe2Hi
3.0/2.4 3.1 ps rms
Hi-band content
(1.5MHz to Nyquist)
FBD REFCLK phase jitter
(including PLL BW 11 - 33 MHz,
ζ = 0.54, Td=12 ns Ftrl=0.2MHz)
FBD REFCLK phase jitter
(including PLL BW 11 - 33 MHz,
ζ = 0.54, Td=12 ns Ftrl=0.2MHz)
ps
(RMS)
tjphFBD1_3.2G
2.5/2.1
3
1,2
1,2
ps
(RMS)
tjphFBD1_4.8G
Notes on Phase Jitter:
2.0/1.6 2.5
1 See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production.
2 Device driven by 932S421BGLF or equivalent
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12
4 Hi-Bandwidth Number/Low Bandwidth Number with Spread On. Spread Off gives lower numbers.
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
10
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
9FG1200 SMBus Address Mapping
when using CK410B+ and DB400/800
SMB_A(2:0) = 000
SMB Adr: D0
9FG1200
(DB1200G)
SMB_A(2:0) = 001
SMB Adr: D2
9FG1200
SMB Adr: D2
932S421
(CK410B+)
OR
(DB1200G)
SMB_A(2:0) = 010
SMB Adr: D4
9FG1200
(DB1200G)
SMB_A(2:0) = 011
SMB Adr: D6
9FG1200
(DB1200G)
SMB_A(2:0) = 100
SMB Adr: D8
9FG1200
(DB1200G)
SMB_A(2:0) = 101
SMB Adr: DA
9FG1200
(DB1200G)
SMB_A(2:0) = 110
SMB Adr: DC
9FG1200
SMB Adr: DC
9DB401/801
(DB400/800)
OR
(DB1200G)
SMB_A(2:0) = 111
SMB Adr: DE
9FG1200
(DB1200G)
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
11
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
General SMBus serial interface information for the 9FG1200D-1
How to Write:
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D0(h)
• ICS clock will acknowledge
• Controller (host) sends a start bit.
• Controller (host) sends the write address D0(h)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D1(h)
• ICS clock will acknowledge
• ICS clock will acknowledge each byte one at a time
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• Controller (host) sends a Stop bit
• ICS clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
Controller (Host)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
starT bit
T
T
starT bit
Slave Address D0(h)*
Slave Address D0(h)*
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D1(h)*
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
* Note: See SMBus Address Mapping (page 10), for programming SMBus Read/Write Address
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
12
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
SMBusTable: Gear Ratio Select Register
Byte 0
Bit 7
Pin #
DIF(9:0)
Name
Control Function
Type
RW Gear Ratio
RW Gear Ratio
RW
RW
RW
RW
RW
RW
0
1
1:1
1:1
PWD
1
1
1
Group of 10 gear ratio enable
Group of 2 gear ratio enable
Reserved
Gear Ratio FS4 (FS_A_410#)
Gear Ratio FS3
DIF(11:10)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
Latch
See 9FG1200-1
Programmable Gear
Ratios Table
1
0
1
1
Gear Ratio FS2
Gear Ratio FS1
Gear Ratio FS0
SMBusTable: Output Control Register
Byte 1
Bit 7
Pin #
35, 36
Name
DIF_7
DIF_6
DIF_5
DIF_4
DIF_3
DIF_2
DIF_1
DIF_0
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
32, 33
24, 25
19,20
16,17
13,14
9,10
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
6,7
SMBusTable: Output and PLL BW Control Register
Byte 2
Bit 7
Pin #
Name
Control Function
Reserved
PLL_BW# adjust
Type
0
1
PWD
1
1
1
1
1
1
1
1
see note
see note
RW
RW
High BW
Bypass
Low BW
PLL
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BYPASS# test mode / PLL
Reserved
DIF_11
DIF_10
DIF_9
DIF_8
51,52
47,48
42,43
39,40
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Enable
Enable
Enable
Enable
Note: Bit 6 is wired OR to the pin 1 input, any 0 selects High BW
Note: Bit 5 is wired OR to the pin 30 input, any 0 selects Fanout Bypass mode
SMBusTable: Output Enable Readback Register
Byte 3 Pin # Name Control Function
34 Readback - OE7# Input
Type
R
0
1
PWD
X
Readback
Bit 7
31
26
21
18
15
8
Readback - OE6# Input
Readback - OE5# Input
Readback - OE4# Input
Readback - OE3# Input
Readback - OE2# Input
Readback - OE1# Input
Readback - OE0# Input
R
R
R
R
R
R
R
Readback
Readback
Readback
Readback
Readback
Readback
Readback
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
5
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
13
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
SMBusTable: Output Enable Readback Register
Byte 4
Bit 7
Pin #
46
1
Name
Control Function
Type
R
R
R
R
R
R
R
R
0
1
PWD
X
X
X
X
X
X
X
X
Readback - FS_A_410
Readback
Readback
Readback
Readback
Readback
Readback
Readback
Readback
Readback - HIGH_BW# In
Readback - SMB_A2_PLLBYP# In
Reserved
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
30
Reserved
53
44
41
Readback - OE10_11# Input
Readback - OE9# Input
Readback - OE8# Input
SMBusTable: Vendor & Revision ID Register
Byte 5
Bit 7
Pin #
-
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
X
X
X
X
0
0
0
1
-
-
-
-
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REVISION ID
VENDOR ID
SMBusTable: DEVICE ID
Byte 6 Pin #
Bit 7
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
-
Device ID 7 (MSB)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
1
0
0
0
0
0
0
-
-
-
-
-
-
-
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBusTable: Byte Count Register
Byte 7
Bit 7
Pin #
-
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
0
0
0
0
1
0
0
1
-
-
-
-
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to this register
configures how many
bytes will be read back.
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
14
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
SMBusTable: 1:1 PLL Frequency Selection
Byte 8
Bit 7
Pin #
Name
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
0
0
0
0
0
x
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
Frequency Select C
Frequency Select B
FS_A_410
RW
RW
RW
See 9FG1200-1 1:1 PLL
Programming Table
1
Latch
SMBusTable: Reserved Register
Byte 9 Pin # Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Type
0
1
PWD
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
0
0
0
SMBus Table: M/N Programming Enable
Byte 10
Pin #
Name
Control Function
Gear PLL and 1:1 PLL
M/N Programming
Enable
Type
0
1
PWD
-
M/N_EN
RW
Disable
Enable
0
Bit 7
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: Gear PLL Frequency Control Register
Byte 11
Bit 7
Pin #
Name
Control Function
RESERVED
Type
0
1
PWD
X
RESERVED
X
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
Gear PLL M Div5
Gear PLL M Div4
Gear PLL M Div3
Gear PLL M Div2
Gear PLL M Div1
Gear PLL M Div0
RW
RW
RW
RW
RW
RW
-
-
-
-
-
M Divider Programming
bits
Contact IDT for 9FG1200-
1 M/N programming Table
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
15
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
SMBus Table: Gear PLL Frequency Control Register
Byte 12
Bit 7
Pin #
-
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
X
Gear PLL N Div7
Gear PLL N Div6
Gear PLL N Div5
Gear PLL N Div4
Gear PLL N Div3
Gear PLL N Div2
Gear PLL N Div1
Gear PLL N Div0
-
-
-
-
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N Divider Programming
bits
Contact IDT for 9FG1200-
1 M/N programming Table
SMBusTable: Gear PLL Output Divider Register
Byte 13
Bit 7
Pin #
Name
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
0
0
0
0
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
RW
RW
RW
GoutDiv 3
GoutDiv 2
GoutDiv 1
GoutDiv 1
Contact IDT for Output
Divider Table
Gear Output Divider
SMBusTable: Reserved Register
Byte 14 Pin # Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
0
0
0
0
0
0
0
0
SMBusTable: Reserved Register
Byte 15 Pin # Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
0
0
0
0
0
0
0
0
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
16
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
SMBusTable: Reserved Register
Byte 16
Bit 7
Pin #
Name
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
0
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBus Table: 1:1 PLL Frequency Control Register
Byte 17
Bit 7
Pin #
Name
Control Function
RESERVED
Type
0
1
PWD
0
RESERVED
0
X
X
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1:1 PLL M Div5
1:1 PLL M Div4
1:1 PLL M Div3
1:1 PLL M Div2
1:1 PLL M Div1
1:1 PLL M Div0
RW
RW
RW
RW
RW
RW
-
-
-
-
-
M Divider Programming
bits
Contact IDT for 9FG1200-
1 M/N programming Table
SMBus Table: 1:1 PLL Frequency Control Register
Byte 18
Bit 7
Pin #
-
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
X
X
X
X
X
X
X
X
1:1 PLL N Div7
1:1 PLL N Div6
1:1 PLL N Div5
1:1 PLL N Div4
1:1 PLL N Div3
1:1 PLL N Div2
1:1 PLL N Div1
1:1 PLL N Div0
-
-
-
-
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N Divider Programming
bits
Contact IDT for 9FG1200-
1 M/N programming Table
SMBusTable: 1:1 PLL Output Divider Register
Byte 19
Bit 7
Pin #
Name
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
0
0
0
0
X
X
X
X
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
RW
RW
RW
1outDiv 3
1outDiv 2
1outDiv 1
1outDiv 1
Contact IDT for Output
Divider Table
1:1 Output Divider
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
17
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
SMBusTable: Reserved Register
Byte 20
Bit 7
Pin #
Name
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Type
0
1
PWD
0
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBusTable: Test Byte Register
Byte 21 Test
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Test Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
Test Result
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWD
`
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
ICS ONLY TEST
0
0
0
0
0
0
0
0
Note: Do NOT write to Bit 21. Erratic device operation will result!
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
18
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
SRC Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
Unit Figure
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
L3 length, Route as non-coupled 50 ohm trace.
Rs
Rt
0.5 max
0.2 max
0.2 max
33
inch
inch
inch
ohm
ohm
1
1
1
1
1
49.9
Down Device Differential Routing
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
2 min to 16 max
1.8 min to 14.4 max
Unit Figure
inch
inch
1
1
Differential Routing to PCIe Connector
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
0.25 to 14 max
0.225 min to 12.6 max inch
Unit Figure
inch
2
2
Figure 1 Down device routing.
L1
L2
L2
L4
Rs
Rs
L4’
L1’
Rt
Rt
HSCL Output
Buffer
PCI Ex Board
Down Device
REF_CLK Input
L3’ L3
Figure 1
Figure 2 PCIe Connector Routing.
L1
L2
L4
Rs
Rs
L4’
L1’
L2’
Rt
Rt
HSCL Output
Buffer
PCI Ex
Add In Board
L3’ L3
REF_CLK Input
Figure 2
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
19
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
Alternative termination for LVDS and other common differential signals. Figure 3.
Vdiff
0.45 v
0.58
0.80
0.60
Vp-p
0.22v
0.28
0.40
0.3
Vcm
1.08
0.6
0.6
1.2
R1
33
33
33
33
R2
R3
R4
Note
150
78.7
78.7
174
100
137
none
140
100
100
100
100
ICS874003i-02 input compatible
Standard LVDS
R1a = R1b = R1
Figure_3.
L1
L2
R3
R4
L4
R1a
R1b
L4’
L1’
L2’
R2a
R2b
HSCL Output
Buffer
Down Device
REF_CLK Input
L3’
L3
R2a = R2b = R2
Cable connected AC coupled application, figure 4
Component
R5a,R5b
R6a,R6b
Cc
Value
8.2K
Note
5%
1K
0.1
5%
uF
0.350
Vcm
volts
3.3 Volts
R5a
R5b
R6b
L4
Cc
L4’
Cc
R6a
PCIe Device
REF_CLK Input
Figure_4.
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
20
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
56-Lead, 300 mil Body, 25 mil, SSOP
c
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
MIN MAX
.095 .110
N
SYMBOL
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
L
A
A1
b
.008
.008
.005
.016
.0135
.010
E1
E
INDEX
AREA
c
D
E
E1
e
h
L
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
0.635 BASIC
0.025 BASIC
α
h x 45°
D
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
a
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A
VARIATIONS
A1
D mm.
D (inch)
- C -
N
MIN
18.31
MAX
18.55
MIN
.720
MAX
.730
e
SEATING
PLANE
56
b
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
21
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
c
N
(240 mil)
(20 mil)
In Millimeters
In Inches
L
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
E1
E
A
A1
A2
b
INDEX
AREA
c
1
2
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
a
D
E1
e
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
L
0.45
0.75
.018
.030
A
A2
N
SEE VARIATIONS
SEE VARIATIONS
a
aaa
0°
--
8°
0.10
0°
--
8°
.004
A1
- CC --
e
SEATING
PLANE
b
VARIATIONS
D mm.
D (inch)
aaa
C
N
MIN
13.90
MAX
14.10
MIN
.547
MAX
.555
56
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
Part / Order Number
9FG1200DF-1LF
9FG1200DF-1LFT
9FG1200DG-1LF
9FG1200DG-1LFT
Shipping Packaging
Tubes
Package
Temperature
0 to +70°C
0 to +70°C
0 to +70°C
0 to +70°C
56-pin SSOP
56-pin SSOP
56-pin TSSOP
56-pin TSSOP
Tape and Reel
Tubes
Tape and Reel
“LF” suffix to the part numbers denotes Pb-Free configuration, RoHS compliant.
“D” is the device revision designator (will not correlate with the datasheet revision).
IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
22
ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
Revision History
A
B
C
12/11/2007 Final Release.
-
1/21/2009 Update Skew and Phase Jitter tables.
2/8/2010 Updated part ordering information
10,11
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
800-345-7015
408-284-6578
408-284-8200
pcclockhelp@idt.com
Fax: 408-284-2775
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Europe
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Fax: 65-6-744-1764
England
Phone: 44-1372-363339
Fax: 44-1372-378851
©
2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is service mark of Integrated Device Technology, Inc. All other brands, product names and marks
a
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
23
相关型号：
ICS9FG1200YG-1LF-T
Processor Specific Clock Generator, 400MHz, PDSO56, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-56
IDT
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