ICSSSTUA32866BHT [IDT]
D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, 5.50 X 13.50 MM, MO-205, LFBGA-96;
| 型号： | ICSSSTUA32866BHT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, 5.50 X 13.50 MM, MO-205, LFBGA-96 |
| 文件： | 总27页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICSSSTUA32866B
Integrated
Circuit
Systems,Inc.
25-Bit Configurable Registered Buffer for DDR2
Pin Configuration
Recommended Application:
•
DDR2 Memory Modules
1
2
3
4
5
6
•
Provides complete DDR DIMM solution with
ICS97ULP877
Ideal for DDR2 400,533 and 667
A
B
C
D
E
F
•
Product Features:
•
•
•
•
25-bit 1:1 or 14-bit 1:2 configurable registered buffer
with parity check functionality
Supports SSTL_18 JEDEC specification on data
inputs and outputs
Supports LVCMOS switching levels on CSR# and
RESET# inputs
Low voltage operation
VDD = 1.7V to 1.9V
Available in 96 BGA package
Drop-in replacement for ICSSSTUA32864
Green packages available
G
H
J
K
L
M
N
P
R
T
•
•
•
FunctionalityTruthTable
96 Ball BGA
(Top View)
Inputs
Outputs
QCS#
Dn,
DODT,
DCKE
QODT,
QCKE
RST#
DCS#
CSR#
CK
CK#
Qn
H
H
H
H
H
H
H
H
H
H
H
H
L
H
X
L
L
L
L
L
L
L
L
L
L
H
H
Q
0
Q
0
Q
0
L or H
L or H
L or H
L or H
L or H
L or H
L
L
L
L
L
L
H
H
H
L
L
H
X
H
H
Q
0
Q
0
Q
0
L
L
L
H
H
H
L
L
L
H
H
H
X
H
H
Q
0
Q
0
Q
0
Q
0
H
H
L
L
H
H
H
H
Q
0
H
X
H
Q
0
Q
0
Q
0
H
H
L or H
X or
L or H
X or
X or
X or
X or
L
L
L
L
Floating Floating Floating Floating Floating
1054A—01/28/05
ICSSSTUA32866B
Ball Assignments
25 bit 1:1 Register
DCKE
D2
PPO
D15
D16
VREF
GND
VDD
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
QCKE
Q2
NC
A
B
C
D
E
F
Q15
Q16
NC
D3
Q3
DODT
D5
QERR# GND
QODT
Q5
D17
D18
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
Q17
Q18
C0
D6
Q6
PAR_IN RST#
C1
G
H
J
CK
DCS#
CSR#
D19
QCS#
ZOH
Q8
NC
CK#
D8
ZOL
Q19
Q20
Q21
Q22
Q23
Q24
Q25
K
L
D9
D20
Q9
D10
D11
D12
D13
D14
D21
Q10
Q11
Q12
Q13
Q14
M
N
P
R
T
D22
D23
D24
D25
1
2
3
4
5
6
C0 = 0, C1 = 0
14 bit 1:2 Registers
D1
PPO
NC
VREF
GND
VDD
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
Q1A
Q2A
Q3A
Q4A
Q5A
Q6A
C1
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
C0
DCKE
D2
PPO
NC
VREF
GND
VDD
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
QCKEA QCKEB
A
B
C
D
E
F
A
B
C
D
E
F
D2
D3
D4
D5
D6
Q2A
Q3A
Q2B
Q3B
NC
D3
NC
QERR# GND
DODT
D5
QERR# GND
QODTA QODTB
NC
NC
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
NC
NC
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VREF
Q5A
Q6A
C1
Q5B
Q6B
C0
D6
PAR_IN RST#
PAR_IN RST#
G
H
J
G
H
J
CK
DCS#
CSR#
NC
QCSA# QCSB#
CK
DCS#
CSR#
NC
QCSA# QCSB#
CK#
D8
ZOH
Q8A
Q9A
Q10A
ZOL
Q8B
Q9B
Q10B
CK#
D8
ZOH
Q8A
ZOL
Q8B
K
L
K
L
D9
NC
D9
NC
Q9A
Q9B
D10
DODT
D12
D13
DCKE
NC
D10
D11
D12
D13
D14
NC
Q10A
Q11A
Q12A
Q13A
Q14A
Q10B
Q11B
Q12B
Q13B
Q14B
M
N
P
R
T
M
N
P
R
T
NC
QODTA QODTB
NC
NC
Q12A
Q13A
Q12B
Q13B
NC
NC
NC
NC
QCKEA QCKEB
NC
1
2
3
4
5
6
1
2
3
4
5
6
Register A (C0 = 0, C1 = 1)
Register B (C0 = 1, C1 = 1)
1054A—01/28/05
2
ICSSSTUA32866B
General Description
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUA32866B operates
from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going low.
The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when
high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).
A - Pair Configuration (CO1 = 0, CI1 = 1 and CO2 = 0, CI2 = 1)
Parity that arrives one cycle after the data input to which it applies is checked on the PAR_IN of the first register.
The second register produces to PPO and QERR# signals. The QERR# of the first register is left floating. The
valid error information is latched on the QERR# output of the second register. If an error occurs QERR# is latched
low for two cycles or until Reset# is low.
B - Single Configuration (CO = 0, C1 = 0)
The device supports low-power standby operation. When the reset input (RST#) is low, the differential input receivers
are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when
RST# is low all registers are reset, and all outputs are forced low. The LVCMOS RST# and Cn inputs must always be
held at a valid logic high or low level.To ensure defined outputs from the register before a stable clock has been supplied,
RST# must be held in the low state during power up.
In the DDR-II RDIMM application, RST# is specified to be completely asynchronous with respect to CK and CK#.
Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared
and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers.
As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST# until
the input receivers are fully enabled, the design of the ICSSSTUA32866B must ensure that the outputs will remain
low, thus ensuring no glitches on the output.
The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS#
and CSR# inputs are high. If either DCS# or CSR# input is low, the Qn outputs will function normally. The RST input
has priority over the DCS# and CSR# control and will force the outputs low. If the DCS#-control functionality is not
desired, then the CSR# input can be hardwired to ground, in which case, the setup-time requirement for DCS# would
be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC).
Parity and Standby Functionality Truth Table
Inputs
Outputs
Sum of Inputs = H
Rst#
DCS#
CSR#
CK
CK#
PAR_IN
PPO
QERR#
(D1 - D25)
Even
Odd
Even
Odd
Even
Odd
X
↑
↑
↑
↑
↑
↑
↑
↓
↓
↓
↓
↓
↓
↓
H
H
H
H
H
H
H
L
L
L
X
X
X
X
L
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
H
L
H
H
X
PPO0 QERR0#
PPO0 QERR0#
H
X
X
L or H
L or H
X
X
X or
X or
X or
X or
X or
Floating
L
X or Floating
L
H
Floating Floating Floating Floating
1. CO = 0 and CI = 0, Data inputs are D2, D3, D5, D6, D8 - D25.
CO = 0 and CI = 1, Data inputs are D2, D3, D5, D6, D8 - D14
CO = 1 and CI = I, Data inputs are D1 - D6, D8 - D10, D12, D13
2. PAR_IN arrives one clock cycle after the data to which it applies when CO = 0.
3. PAR_IN arrives two clock cycles after the data to which it applies when CO = 1.
↑
↓
4. Assume QERR# is high at the CK and CK# crossing. If QERR# is low it stays latched low for two
clock cycles on until Rst# is low.
1054A—01/28/05
3
ICSSSTUA32866B
Ball Assignment
Electrical
Characteristics
Terminal Name
Description
GND
VDD
Ground
Ground input
1.8V nominal
0.9V nominal
Input
Power supply voltage
VREF
ZOH
Input reference voltage
Reserved for future use
Reserved for future use
Positive master clock input
Negative master clock input
Configuration control inputs
ZOL
Input
CK
Differential input
Differential input
LVCMOS inputs
CK
C0, C1
Asynchronous reset input - resets registers and disables VREF data and
clock differential-input receivers
RST#
CSR#, DCS#
D1 - D25
DODT
LVCMOS input
SSTL_18 input
SSTL_18 input
SSTL_18 input
SSTL_18 input
Chip select inputs - disables D1 - D24 outputs switching when both inputs
are high
Data input - clock in on the crossing of the rising edge of CK and the
falling edge of CK#
The outputs of this register bit will not be suspended by the DCS# and
CSR# control
The outputs of this register bit will now be suspended by the DCS# and
CSR# control
DCKE
Q1 - Q25
QCS#
Data ouputs that are suspended by the DCS# and CSR# control
Data output that will not be suspended by the DCS# and CSR# control
Data output that will not be suspended by the DCS# and CSR# control
Data output that will not be suspended by the DCS# and CSR# control
Partial parity out indicates off parity of inputs D1 - D25.
1.8V CMOS
1.8V CMOS
1.8V CMOS
1.8V CMOS
1.8V CMOS
SSTL_18 input
QODT
QCKE
PPO
PAR_IN
Parity input arrives one clock cycle after the corresponding data input
Output error bit-generated one clock cycle after the corresponding data
output
Open drain
output
QERR#
1054A—01/28/05
4
ICSSSTUA32866B
Block Diagram for 1:1 mode (positive logic)
RST#
CK
CK#
VREF
DCKE
D
C1
C1
QCKEA
QODTA
R
D
DODT
DCS#
CSR#
R
1D
C1
QCSA#
R
D1
0
1
1D
Q1A
C1
Q1B*
R
To 21 Other Channels
*Note: Disabled in 1:1 configuration
1054A—01/28/05
5
ICSSSTUA32866B
Block Diagram for 1:2 mode (positive logic)
RST#
CK
CK#
VREF
DCKE
1D
C1
QCKEA
QCKEB*
R
DODT
DCS#
CSR#
1D
QODTA
C1
QODTB*
R
1D
QCSA#
C1
QCSB#*
R
D1
0
1
1D
Q1A
C1
Q1B*
R
To 10 Other Channels
*Note: Disabled in 1:1 configuration
1054A—01/28/05
6
ICSSSTUA32866B
2. Device standard (cont'd)
G2
RST#
H1
CK
J1
CK#
LPS0
(internal node)
D2•D3,
D5•D6,
D8-D25
22
D2•D3,
Q2•Q3,
D5•D6,
D8•D25
CE
D
A3, T3
22
V
Q5•Q6,
Q8•Q25
REF
CK
Q
22
R
D2•D3,
D5•D6,
D8•D25
22
Parity
Generator
G5
C1
1
0
0
A2
PPO
D
Q
1
D
R
Q
D
R
Q
CK
CK
CE
CK
R
G1
G6
PAR_IN
D2
QERR#
C0
CK
0
1
2•Bit
Counter
R
LPS1
(internal node)
D
R
Q
CK
Figure 6 — Parity logic diagram for 1:1 register configuration (positive logic); C0=0, C1=0
1054A—01/28/05
7
ICSSSTUA32866B
2. Device standard (cont'd)
G2
RST#
H1
CK
J1
CK#
LPS0
(internanlode)
D2 D3,
D5 D6,
D8-D14
Q2A Q3A,
Q5A Q6A,
Q8A Q14A
11
D2 D3,
D5 D6,
D8 D14
11
11
CE
CK
D
R
A3, T3
V
REF
Q
11
Q2B Q3B,
Q5B Q6B,
Q8B Q14B
D2 D3,
D5 D6,
D8 D14
11
Parity
Generator
G5
C1
1
0
0
A2
PPO
D
R
Q
1
D
R
Q
D
Q
CK
CK
CE
CK
R
G1
G6
PAR_IN
D2
QERR#
C0
CK
0
1
2 Bit
Counter
R
LPS1
(internal node)
D
R
Q
CK
Figure 7 — Parity logic diagram for 1:2 register-A configuration (positive logic); C0=0, C1=1
Figure 7 — Parity logic diagram for 1:2 register-A configuration (positive logic); C0=0, C1=1
1054A—01/28/05
8
ICSSSTUA32866B
2. Device standard (cont'd)
G2
RST#
H1
CK
J1
CK#
LPS0
(internal node)
D1•D6,
D8-D13
11
11
Q1A•Q6A,
Q8A•Q13A
D1•D6,
D8•D13
CE
D
A3, T3
V
REF
CK
Q
11
11
R
Q1B•Q6B,
Q8B•Q13B
D1•D6,
11
D8•D13
Parity
Generator
G5
C1
1
0
A2
PPO
D
R
Q
1
0
D
R
Q
D
Q
CK
CK
CE
CK
R
G1
G6
PAR_IN
D2
QERR#
C0
CK
2•Bit
Counter
R
0
1
LPS1
(internal node)
D
R
Q
CK
Figure 8 — Parity logic diagram for 1:2 register-B configuration (positive logic); C0=1, C1=1
1054A—01/28/05
9
ICSSSTUA32866B
2. Device standard (cont'd)
RST#
DCS#
CSR#
n
n + 1
n + 2
n + 3
n + 4
CK
CK#
t
su
t
t
h
act
†
D1•D25
t
, t
pdm pdmss
CK to Q
Q1•Q25
PAR_IN
t
t
su
h
†
t
pd
CK to PPO
PPO
t
t
, t
PHL PLH
PHL
CK to QERR#
CK to QERR#
‡
Data to QERR# Latency
QERR#
H, L, or X
H or L
Figure — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0;
9
RST# Switches from L to H
RST#
is switched fro low to high, al data and PAR_IN inputs signals must be se and held lo for a minimum time of tACT
†
‡
After
max, to avoid false error.
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse.
1054A—01/28/05
10
ICSSSTUA32866B
2. Device standard (cont'd)
RST#
DCS#
CSR#
CK
n
n + 1
n + 2
n + 3
n + 4
CK#
t
t
su
h
D1•D25
t
, t
CK to
pdm pdmss
Q1•Q25
t
t
su
h
PAR_IN
PPO
t
pd
CK to PPO
t
or t
PLH
PHL
Data to PPO Latency
CK to QERR#
†
QERR#
Data to QERR# Latency
Output signal is dependent on
the prior unknown input event
Unknown input
event
H or L
Figure 10 — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0;
RST# being held high
†
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse. If an error occurs and the QERR# output is driven low, it stays latched low for a minimum of two clock cycles or
until RST# is driven low.
1054A—01/28/05
11
ICSSSTUA32866B
2. Device standard (cont'd)
RST#
t
inact
†
†
DCS#
CSR#
†
†
CK
CK#
†
D1•D25
t
RPHL
RST# to Q
Q1•Q25
PAR_IN
†
t
RPHL
RST# to PPO
PPO
QERR#
t
RPLH
RST# to QERR#
H, L, or X
H or L
Figure 11 — Timing diagram fo SSTU32866 used as a single device; C0=0, C1=0;
RST# switches from H to L
†
After RST# is itched from high to low, all data and clock inputs signals must be set and held at valid logic levels (not floating) for
sw
a minimum time of tINACT max
1054A—01/28/05
12
ICSSSTUA32866B
2. Device standard (cont'd)
RST#
DCS#
CSR#
n
n + 1
n + 2
n + 3
n + 4
CK
CK#
t
su
t
t
h
act
†
D1•D14
t
, t
pdm pdmss
CK to Q
Q1•Q14
PAR_IN
t
t
su
h
†
t
pd
CK to PPO
PPO
t
t
, t
PHL PLH
PHL
CK to QERR#
CK to QERR#
‡
QERR#
(not used)
Data to QERR#
Latency
H, L, or X
H or L
Figure 12 — Timing diagram for the firs SSTU32866 (1:2 register-A configration) device used in
pair; C0 = 0, C1 = 1; RST# switches from L to H
After
RST#
is switched
†
‡
fro low to high, al data and PAR_IN inputs signals must be se and held lo for a minimum time of tACT
max, to avoid false error
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+1 clock pulse, and it will be valid on
the n+2 clock pulse.
1054A—01/28/05
13
ICSSSTUA32866B
2. Device standard (cont'd)
RST#
DCS#
CSR#
n
n + 1
n + 2
n + 3
n + 4
CK
CK#
t
t
su
h
D1•D14
t
, t
pdm pdmss
CK to Q
Q1•Q14
PAR_IN
t
t
su
h
t
pd
CK to PPO
PPO
t
or t
PLH
PHL
CK to QERR#
Data to PPO
Latency
†
QERR#
(not used)
Data to QERR#
Latency
Output signal is dependent on
the prior unknown input event
Unknown input
event
H or L
Figure 13 — Timing diagram for the firs SSTU32866 (1:2 register-A configration) device used in
pair; C0 = 0, C1 = 1; RST# bein held high
†
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+1 clock pulse, and it will be valid on
the n+2 clock pulse. If an error occurs and the QERR# output is driven low, it stays latched low for a minimum of two clock cycles or
until RST# is driven low.
1054A—01/28/05
14
ICSSSTUA32866B
2. Device standard (cont'd)
RST#
t
inact
†
†
DCS#
CSR#
†
†
CK
CK#
†
D1•D14
t
RPHL
RST# to Q
Q1•Q14
PAR_IN
†
t
RPHL
RST# to PPO
PPO
QERR#
(not used)
t
RPLH
RST# to QERR#
H, L, or X
H or L
Figure 14 — Timing diagram for the firs SSTU32866 (1:2 register-A configration) device used in
pair; C0 = 0, C1 = 1; RST# switches from H to L
†
RST# is switched from high to low, all data and clock inputs signals must be held at valid logic levels (not floating) for a
After
minimum time of tINACT max
1054A—01/28/05
15
ICSSSTUA32866B
2. Device standard (cont'd)
RST#
DCS#
CSR#
n
n + 1
n + 2
n + 3
n + 4
CK
CK#
t
t
t
h
su
act
†
D1•D14
Q1•Q14
t
, t
pdm pdmss
CK to Q
t
t
su
h
†‡
PAR_IN
t
pd
CK to PPO
PPO
(not used)
t
t
, t
PHL
CK to QERR#
PHL PLH
CK to QERR#
§
QERR#
Data to QERR# Latency
H, L, or X
H or L
Figure 15 — Timing diagram for the second SSTU32866 (1:2 register-B configration) device used in
pair; C0 = 1, C1 = 1; RST# switches from L to H
†
After
switched fro low to high, al data and PAR_IN inputs signals must be se and held lo for a minimum time of tACT
RST#
max, to avoid false error
‡
§
PAR_IN is driven from PPO of the first SSTU32866 device
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse.
1054A—01/28/05
16
ICSSSTUA32866B
2. Device standard (cont'd)
RST#
DCS#
CSR#
n
n + 1
n + 2
n + 3
n + 4
CK
CK#
t
su
t
h
D1 D14
t
, t
pdm pdmss
CK to Q
Q1 Q14
PAR_IN
t
su
t
h
t
pd
CK to PPO
PPO
t
or t
PLH
PHL
CK to QERR#
Data to PPO
Latency
†
QERR#
(not used)
Data to QERR#
Latency
Output signal is dependent on
the prior unknown input event
Unknown input
event
H or L
Figure 16 — Timing diagram for the second SSTU32866 (1:2 register-B configration) device used in
pair; C0 = 1, C1 = 1; RST# being held high
†
PAR_IN is driven from PPO of the first SSTU32866 device
‡
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse. If an error occurs and the QERR# output is driven low, it stays latched low for a minimum of two clock cycles or
until RST# is driven low.
1054A—01/28/05
17
ICSSSTUA32866B
2. Device standard (cont'd)
RST#
t
inact
†
DCS#
†
†
CSR#
CK
†
†
CK#
D1•D14
Q1•Q14
PAR_IN
t
RPHL
RST# to Q
†
t
RPHL
RST# to PPO
PPO
(not used)
QERR#
t
RPLH
RST# to QERR#
H, L, or X
H or L
Figure 17 — Timing diagram for the second SSTU32866 (1:2 register-B configration) device used in
pair; C0 = 1, C1 = 1; RST# switches from H to L
†
from high to low, all data and clock input signals must be held at valid logic levels (not floating) fo a
RST# is switched
After
minimum time of tINACT max
1054A—01/28/05
18
ICSSSTUA32866B
* Register Configurations
DATA INPUT:
DATA OUTPUT:
CO
CI
D2, D3, D5, D6, D2, D3, D5, D6,
D8 - D25 D8 - D25
0
0
D2, D3, D5, D6, D2, D3, D5, D6,
0
1
1
1
D8 - D14
D8 - D14
D1 - D6, D8 -
D1 - D6, D8 -
D10, D12, D13
D10, D12, D13
1054A—01/28/05
19
ICSSSTUA32866B
Absolute Maximum Ratings
Notes:
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 2.5V
Input Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +2.5V
Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V
Input Clamp Current . . . . . . . . . . . . . . . . . . . . 50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . 50mA
Continuous Output Current. . . . . . . . . . . . . . . 50mA
VDD or GND Current/Pin . . . . . . . . . . . . . . . . 100mA
1. The input and output negative voltage
ratings may be excluded if the input
andoutputclampratingsareobserved.
2. This value is limited to 2.5V maximum.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Package Thermal Impedance3 . . . . . . . . . . . . . . . 36°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Recommended Operating Conditions
DESCRIPTION
PARAMETER
VDDQ
VREF
VTT
MIN
1.7
TYP
1.8
MAX
1.9
UNITS
I/O Supply Voltage
Reference Voltage
0.49 x VDD 0.5 x VDD
0.51 x VDD
VREF + 0.04
VDDQ
Termination Voltage
VREF - 0.04
0
VREF
VI
Input Voltage
VIH (DC)
VIH (AC)
VIL (DC)
VIL (AC)
VIH
DC Input High Voltage
AC Input High Voltage
DC Input Low Voltage
AC Input Low Voltage
Input High Voltage Level
Input Low Voltage Level
Common mode Input Range
Differential Input Voltage
High-Level Output Current
Low-Level Output Current
VREF + 0.125
VREF + 0.250
Data Inputs
V
VREF - 0.125
VREF - 0.250
RST#,
C0, C1
0.65 x VDDQ
VIL
0.35 x VDDQ
1.125
VICR
0.675
0.600
CK, CK#
VID
IOH
-8
8
mA
°C
IOL
Operating Free-Air Temperature
TA
0
70
1Guaranteed by design, not 100% tested in production.
Note: Rst# and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. The
differential inputs must not be floating unless Rst# is low.
1054A—01/28/05
20
ICSSSTUA32866B
Electrical Characteristics - DC
TA = 0 - 70°C; VDD = 1.8 +/-0.1V (unless otherwise stated)
CONDITIONS
SYMBOL
PARAMETERS
VDD
MIN
1.2
-5
TYP MAX
-1.2
UNITS
V
VIK
VOH
VOL
II
II = -18mA
IOH = -6mA
IOL = 6mA
1.7V
1.7V
1.9V
0.5
5
100
All Inputs
Standby (Static)
VI = VDD or GND
RESET# = GND
VI = VIH(AC) or VIL(AC)
RESET# = VDD
µA
µA
IDD
,
1.9V
1.8V
Operating (Static)
mA
40
RESET# = VDD
,
Dynamic operating
(clock only)
µ/clock
MHz
VI = VIH(AC) or VIL(AC)
,
39
CLK and CLK# switching
50% duty cycle.
IO = 0
RESET# = VDD
,
Dynamic Operating
(per each data input)
1:1 mode
IDDD
VI = VIH(AC) or VIL (AC)
,
19
35
CLK and CLK# switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
µA/ clock
MHz/data
Dynamic Operating
(per each data input)
1:2 mode
Data Inputs
CLK and CLK#
RESET#
VI = VREF 350mV
2.5
2
3.5
3
pF
Ci
V
ICR = 1.25V, VI(PP) = 360mV
VI = VDD or GND
2.5
Notes:
1 - Guaranteed by design, not 100% tested in production.
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
V
MIN
1
DD = 1.8V 0.1V
PARAMETER
UNIT
MAX
dV/dt_r
4
4
1
V/ns
V/ns
V/ns
dV/dt_f
1
1
∆
dV/dt_
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
1054A—01/28/05
21
ICSSSTUA32866B
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
VDD = 1.8V 0.1V
UNITS
SYMBOL
PARAMETERS
MIN
MAX
410
-
fclock
tW
Clock frequency
-
MHz
ns
Pulse duration, CK, CK HIGH or LOW
1
tACT
Differential inputs active time (See Notes 1 and 2)
Differential inputs inactive time (See Notes 1 and 3)
-
-
10
15
ns
ns
tINACT
DSR# before CK↑, CK#↓,
CSR# high
CSR# before CK↑, CK#↓,
DCS# high
tsu
tsu
tsu
Setup time
Setup time
Setup time
0.7
0.7
0.5
ns
ns
ns
DCS# before CK , CK# ,
↑
↓
CSR# low
DODT, DCKE and data before
CK↑, CK#↓
tsu
tsu
Setup time
Setup time
Hold time
0.5
0.5
ns
ns
ns
ns
PAR_IN before CK , CK#
↑
↓
DCS#, DODT, DCKE and Q
after CK↑, CK#↓
0.50
0.50
tH
PAR_IN after CK↑, CK#↓
Hold time
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
Notes:
4 - CLK/CLK# signal input slew rate of 1V/ns.
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Measurement
Conditions
Symbol
Parameter
MIN
MAX Units
fmax
Max input clock frequency
410
MHz
Propagation delay, single
bit switching
Propagation delay
Low to High propagation
delay
tPDM
tPD
CK to CK# QN
1.1
0.5
1.2
1.9
1.8
3
ns
ns
ns
↑
↓
CK to CK# to PPO
↑ ↓
tLH
CK to CK# to QERR#
↑ ↓
High to low propagation
delay
Propagation delay
simultaneous switching
High to low propagation
delay
High to low propagation
delay
Low to High propagation
delay
tHL
tPDMSS
tPHL
CK to CK# to QERR#
1
-
2.4
2
ns
ns
ns
ns
ns
↑
↓
CK to CK# QN
↑
↓
Rst# to QN
3
↓
↓
tPHL
Rst# to PPO
3
↓
↓
tPLH
Rst# to QERR#
3
↓
↑
2. Guaranteed by design, not 100% tested in production.
1054A—01/28/05
22
ICSSSTUA32866B
VDD
DUT
RL = 1000•Ω
TL=350ps, 50Ω
TL=50•Ω
CK#
CK
Out
Test Point
CK Inputs
CL = 30 pF
(see Note 1)
RL = 1000Ω•
Test Point
RL = 100Ω•
LOAD CIRCUIT
Test Point
VCMOS
RST#
Input
VDD
0 V
tact
90%
VID
VDD/2
VDD/2
CK
CK
VICR
VICR
tinact
tPLH
tPHL
IDD
(see
Note 2)
10%
VOH
VOL
Output
VTT
VTT
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
VOLTAGE WAVEFORMS – PROPAGATION DELA TIMES
VID
tw
Input
VICR
VICR
VOLTAGE WAVEFORMS – PULSE DURATION
VID
LVCMOS
RST#
Input
VIH
VIL
VDD/2
CK
VICR
tRPHL
CK
VOH
VOL
th
tsu
Output
VTT
VIH
VIL
Input
VREF
VREF
VOLTAGE WAVEFORMS – PROPAGATION DELA TIMES
VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES
Figure 6— Parameter Measurement Information (V = 1.8 V 0.1 V)
DD
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz,
Zo=50Ω, input slew rate = 1 V/ns 20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VREF = VDD/2
6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. VID = 600 mV
9. tPLH and tPHL are the same as tPDM
.
1054A—01/28/05
23
ICSSSTUA32866B
VDD
DUT
RL = 50Ω
Test Point
Out
CL = 10 pF
(see Note 1)
LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT
Output
VOH
80%
20%
dt_f
VOL
dv_f
VOLTAGE WAVEFORMS – HIGH-TO-LOW SLEW-RATE MEASUREMENT
DUT
Out
Test Point
CL = 10 pF
(see Note 1)
RL = 50Ω
LOAD CIRCUIT – LOW-TO-HIGH SLEW-RATE MEASUREMENT
dt_r
dv_r
VOH
80%
20%
Output
VOL
VOLTAGE WAVEFORMS – LOW-TO-HIGH SLEW-RATE MEASUREMENT
Figure 7 — Output Slew-RateMeasurement Information (VDD = 1.8 V 0.1 V)
Notes: 1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO
50Ω, input slew rate = 1 V/ns 20% (unless otherwise specified).
=
1054A—01/28/05
24
ICSSSTUA32866B
3 Test circuits and switching waveforms (cont’d)
3.3 Error output load circuit and voltage measurement information (V = 1.8 V 0.1 V)
DD
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz;
Z = 50 ; input slew rate = 1 V/ns 20%, unless otherwise specified.
Ω
o
V
DD
DUT
R
= 1K
Ω
L
Out
Test Point
C
= 10 pF
L
(see Note 1)
LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT
(1) C includes probe and jig capacitance.
L
Figure 28 — Load circuit, error output measurements
LVCMOS
RST#
V
CC
V
/2
CC
Input
0 V
V
t
PLH
OH
Output
Waveform 2
0.15 V
_ _ _ _ _ _ _ _ _ _ _
0 V
Voltage waveforms, open-drain output low-to-high transition time with respect to reset input
Figure 29 —
V
I
(PP)
Timing
Inputs
V
V
ICR
ICR
t
PHL
_ _ _ _ _ _ _ _ _ _ _
V
Output
Waveform 1
V
CC
OL
/2
CC
V
Figure 30
—
Voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs
V
I
(PP)
Timing
Inputs
V
ICR
V
ICR
t
PHL
V
0
OH
V
Output
Waveform 2
0.15 V
—
Figure 31
Voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs
1054A—01/28/05
25
ICSSSTUA32866B
Test circuits and switching waveforms (cont’d)
3.4 Partial-parity-out load circuit and voltage measurement information (V = 1.8 V ± 0.1 V)
DD
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz;
Ω
Z = 50 input slew rate = 1 V/ns ± 20%, unless otherwise specified.
o
DUT
Out
Test Point
5 pF
C
=
L
R
L
1 k
Ω
=
(see Note A)
(1) CL includes probe and jig capacitance.
Figure 32 — Partial-parity-out load circuit,
CK
V
V
V
ICR
ICR
i(p-p)
V
CK
t
t
PHL
PLH
OH
V
OUTPUT
TT
V
OL
002aaa375
VTT = VDD/2
tPLH an tPHL are the same as tPD
.
V
I(PP) = 600 mV
Figure 33 — Partial-parity-out voltage waveforms; propagation delay times with respect to clock inputs
LVCMOS RST#
V
IH
INPUT
V
/2
DD
V
V
V
IL
t
PHL
OH
OL
OUTPUT
V
TT
002aaa376
VTT = VDD/2
tPLH an tPHL are the same as tPD
.
V
V
IH = VREF + 250 mV (AC voltage levels for differential inputs. VIH = VDD for LVCMOS inputs.
IL = VREF 250 mV (A voltag levels) for differential inputs. VIL = VDD for LVCMOS inputs.
Figure 34 — Partial-parity-out voltage waveforms; propagation delay times with respect to reset input
1054A—01/28/05
26
ICSSSTUA32866B
C
Seating
Plane
Numeric Designations
for Horizontal Grid
A1
b
REF
T
3 2 1
4
A
B
C
D
Alpha Designations
for Vertical Grid
(Letters I, O, Q & S
not used)
D
d TYP
D1
- e - TYP
TOP VIEW
E
c
REF
TYP
- e -
h
TYP
E1
0.12
C
ALL DIMENSIONS IN MILLIMETERS
----- BALL GRID -----
Max.
REF. DIMENSIONS
D
E
T
e
HORIZ
VERT
TOTAL
d
h
b
c
Min/Max
Min/Max
Min/Max
13.50 Bsc
11.50 Bsc
5.50 Bsc
5.00 Bsc
1.30/1.50
/1.20
0.80 Bsc
0.65 Bsc
6
6
16
16
96
96
0.40/0.50
0.38/0.48
0.25/0.41
0.27/0.37
0.75
0.875
0.75
0.875
Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.
* Source Ref.: JEDEC Publication 95,
MO-205
10-0055C
Ordering Information
ICSSSTUA32866Bz(LF)T
Example:
ICS XXXX y z (LF) T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
H = LFBGA (standard size: 5.5 x 13.50)
HM = TFBGA (reduced size: 5.0 x 11.50)
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
1054A—01/28/05
27
相关型号：
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