IDT100474S10DF [IDT]
Standard SRAM, 1KX4, 7ns, CDIP24;型号: | IDT100474S10DF |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Standard SRAM, 1KX4, 7ns, CDIP24 CD 静态存储器 内存集成电路 |
文件: | 总7页 (文件大小:88K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
IDT10474, IDT10A474
IDT100474, IDT100A474
IDT101474, IDT101A474
HIGH-SPEED BiCMOS
ECL STATIC RAM
4K (1K x 4-BIT) SRAM
Integrated Device Technology, Inc.
These devices are part of a family of asynchronous four-
bit-wide ECL SRAMs. This device is available in both the
traditional corner-power pinout, and "revolutionary" center-
power pin configurations. Because they are manufactured in
BiCMOS technology, power dissipation is greatly reduced
over equivalent bipolar devices. Low power operation pro-
vides higher system reliability and makes possible the use of
the plastic SOJ package for high-density surface mount
assembly.
The fast access time and guaranteed Output Hold time
allowgreatermarginforsystemtimingvariation. DataINsetup
time specified with respect to the trailing edge of Write Pulse
eases write timing allowing balanced Read and Write cycle
times.
FEATURES:
• 1024-words x 4-bit organization
• Address access time: 2.7/3/3.5/4/4.5/5/7/8/10/15 ns
• Low power dissipation: 1000mW (typ.)
• Guaranteed Output Hold time
• Fully compatible with ECL logic levels
• Separate data input and output
• Corner and Center power pin pinouts
• Standard through-hole and surface mount packages
• Guaranteed-performance die available for MCMs/hybrids
• MIL-STD-883, Class B product available
DESCRIPTION:
The IDT10474(10A474), IDT100474(100A474) and
IDT101474(101A474)are4,096-bithigh-speedBiCMOSECL
static random access memories organized as 1Kx4, with
separate data inputs and outputs. All I/Os are fully compatible
with ECL levels.
FUNCTIONAL BLOCK DIAGRAM
A
0
V
V
CC
EE
4,096-BIT
MEMORY
ARRAY
DECODER
A
9
D
D
D
D
0
1
2
Q
Q
Q
Q
0
1
2
SENSE AMPS
AND READ/WRITE
CONTROL
3
3
WE
CS
2760 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
OCTOBER 1992
1992 Integrated Device Technology, Inc.
DSC-8022/3
1
IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474
HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
PACKAGES
D1
D2
D3
Q0
1
24
23
22
21
20
19
18
17
D0
CS
WE
A9
VCC
A
1
24
23
22
21
20
19
18
17
VCC
2
3
4
Q
Q
A
2
3
2
3
4
Q
Q
1
0
0
1
D3
D2
D1
D
0
Q1
VCC
VCCA
Q2
5
6
A8
A
A
5
6
A7
2
3
7
VEE
A6
A
7
8
9
10
11
12
CS
A
4
5
8
9
10
11
12
NC
A5
A4
Q3
A0
16
15
WE
A9
A8
A
NC
16
15
300-Mil-Wide
PLASTIC SOJ PACKAGE
SO24-4
400-Mil-Wide
CERDIP PACKAGE
D24-3
A1
A2
14
13
A
6
14
13
A3
VEE
A7
2760 drw 03
2760 drw 04
Center Power
"A"
Top View
Corner Power
"Non-A"
Top View
2760 drw 02a
2760 drw 02b
PIN DESCRIPTIONS
Symbol
Pin Name
Address Inputs
A0 through A9
D0 through D3
Q0 through Q3
WE
Data Inputs
Data Outputs
Hi-Rel Die
For Hybrid and MCM
Applications
Write Enable Input
CS
Chip Select Input (Internal pull down)
More Negative Supply Voltage
Less Negative Supply Voltage
2760 drw 05
VEE
VCC
2760 tbl 01
LOGIC SYMBOL
CAPACITANCE (TA = +25°C, f = 1.0MHz)
D0 D1 D2 D3
DIP
Typ.
SOJ
Symbol Parameter
Max.
—
Typ.
Max. Unit
A0
A1
A2
CIN
Input
Capacitance
4
6
3
3
—
—
pF
COUT
Output
Q0
Q1
A3
Capacitance
—
pF
A4
A5
2760 tbl 02
Q2
Q3
A6
A7
A8
A9
TRUTH TABLE(1)
DataOUT
Function
Deselected
Read
CS
H
WE
X
L
RAM Data
L
L
H
CS WE
L
L
Write
NOTE:
1. H = HIGH, L = LOW, X = Don’t Care
2760 tbl 03
2760 drw 06
2
IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474
HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM
COMMERCIAL TEMPERATURE RANGE
(1)
ABSOLUTE MAXIMUM RATINGS
AC/DC ELECTRICAL OPERATING RANGES
Symbol
Rating
Value
Unit
I/O
VEE
TA
10K
100K
–5.2V ± 5%
–4.5V ± 5%
0 to +75°C, air flow exceeding 2 m/sec
0 to +85°C, air flow exceeding 2 m/sec
VTERM
Terminal Voltage
With Respect to GND
+0.5 to –7.0
V
TA
Operating
Temperature
10K
100K
101K
0 to +75
0 to +85
0 to +75
°C
101K –4.75V to –5.46V 0 to +75°C, air flow exceeding 2 m/sec
2760 tbl 05
TBIAS
TSTG
Temperature Under Bias
–55 to +125
°C
°C
Storage Ceramic
Temperatuure Plastic
Power Dissipation
–65 to +150
–55 to +125
PT
1.5
W
IOUT
DC Output Current
(Output High)
–50
mA
NOTE:
2760 tbl 04
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (1)
10K
100K/101K
Min.
Symbol
Parameter
Min.
Max.
TA
Max.
Unit
VOH
Output HIGH Voltage
(VIN= VIH(Max) or VIL(Min))
–1000
–960
–900
–840
–810
–720
0°C
25°C
75°C
–1025
–1810
–1035
—
–880
mV
VOL
VOHC
VOLC
VIH
VIL
Output LOW Voltage
(VIN= VIH(Max) or VIL(Min))
–1870
–1850
–1830
–1665
–1650
–1625
0°C
25°C
75°C
–1620
—
mV
mV
mV
mV
mV
Output Threshold HIGH Voltage
(VIN= VIH(Min) or VIL(Max))
–1020
–980
–920
—
—
—
0°C
25°C
75°C
Output Threshold LOW Voltage
(VIN= VIH(Min) or VIL(Max))
—
—
—
–1645
–1630
–1605
0°C
25°C
75°C
–1610
–880
–1475
Input HIGH Voltage
(Guaranteed Input Voltage
High for All Inputs)
–1145
–1105
–1045
–840
–810
–720
0°C
25°C
75°C
–1165
–1810
Input LOW Voltage
(Guaranteed Input Voltage
Low for All Inputs)
–1870
–1850
–1830
–1490
–1475
–1450
0°C
25°C
75°C
IIH
Input HIGH Current
VIN= VIH(Max)
CS
Others
—
—
220
110
—
—
—
—
220
110
µA
µA
IIL
Input LOW Current
VIN= VIL(Min)
CS
Others
0.5
–50
170
90
—
—
0.5
–50
170
90
µA
µA
IEE
Supply Current
–210
—
—
–190 (100K)
–210 (101K)
—
—
mA
NOTE:
1. RL = 50Ω to -2V, air flow exceeding 2 m/sec.
2760 tbl 05
3
IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474
HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM
COMMERCIAL TEMPERATURE RANGE
AC TEST LOAD CONDITION
AC TEST INPUT PULSE
VCC (GND)
DATAOUT
–0.9V
–1.7V
80%
20%
50Ω
C*
tR
tF
tR = tF = 1.5ns typ.
0.01µF
–2.0V
VEE
Note: All timing measurements are
referenced to 50% input levels.
*Includes probe and jig capacitance.
C < 5pF (2.7,3.0, 3.5nS speed grades)
C < 30pF (all other speed grades)
2760 drw 08
2760 drw 07
RISE/FALL TIME
Symbol Parameter
Min.
—
Typ.
1.5
Max.
—
Unit
ns
tR
tF
Output Rise Time
Output Fall Time
—
1.5
—
ns
2760 tbl 06
FUNCTIONAL DESCRIPTION
WRITE TIMING
The IDT10474(10A474), IDT100474(100A474), and
To write data to the device, a Write Pulse need be formed
IDT101474(101A474) BiCEMOS ECL static RAMs provide on the Write Enable input (WE) to control the write to the
highspeedwithlowpowerdissipationtypicalofBiCMOSECL. SRAM array. While CS and ADDR must be set-up when WE
These devices are available in both the traditional corner- goes low, DataIN can settle after the falling edge ofWE, giving
power pinout and the "revolutionary" center-power pinout for the data path extra margin. Data is written to the memory cell
reduced noise and improved system performance.
at the end of the Write Pulse, and addresses and Chip Select
must be held after the rising edge of the Write Pulse to ensure
satisfactory completion of the cycle.
DataOUT is disabled (held LOW) during the Write Cycle. If
CS is held LOW (active) and addresses remain unchanged,
the Data OUT pins will output the written data after "Write
Recovery time" (tWR).
READ TIMING
The read timing on these asynchronous devices is straight-
forward. DataOUT is held LOW until the device is selected by
Chip Select (CS). The Address (ADDR) settles and data
appears on the output after time tAA. Note that DataOUT is
held for a short time (tOH) after the address begins to change
for the next access, then ambiguous data is on the bus until a
new time tAA.
Because of the very short Write Pulse requirement, these
devices can be cycled as quickly for Writes as for Reads.
4
IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474
HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range)
S2.7
S3
S3.5
S4
S4.5
S5
S7,8,10,15
(1)
Symbol Parameter
Read Cycle
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tACS
tRCS
tAA
Chip Select Access Time
Chip Select Recovery Time
Address Access Time
—
—
2.0
2.0
2.7
—
—
—
2.0
2.0
3.0
—
—
—
2.5
2.5
3.5
—
—
—
2.5
2.5
4.0
—
—
—
2.5
2.5
4.5
—
—
—
3.0
3.0
5.0
—
—
—
3.5 ns
3.5 ns
7.0 ns
—
—
—
—
—
—
—
tOH
Data Hold from Address
Change
1.0
1.0
1.0
1.0
1.0
1.0
1.0
—
ns
NOTE:
2760 tbl 07
1. Input and Output reference level is 50% point of waveform.
2. Output load capacitance, C < 5pF (2.7, 3.0, 3.5ns speed grades only), see "AC Test Load Condition" on previous page.
READ CYCLE GATED BY CHIP SELECT (1, 2)
CS
tACS
tRCS
DATAOUT
2670 drw 09
READ CYCLE GATED BY ADDRESS (1, 3)
ADDR
tAA
tOH
DATAOUT
2670 drw 10
NOTE:
1. WE is HIGH for read cycle.
2. Address valid prior to or minimum tAA-tACS before CS active.
3. CS active prior to or minimum tAA-tACS after address valid.
5
IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474
HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range)
S2.7
S3.0
S3.5
S4
S4.5
S5
S7,8,10,15
(1)
Symbol Parameter
Write Cycle
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tW
Write Pulse Width
(tWSA = minimum)
2.5
—
2.5
—
3.0
—
3.0
—
3.5
—
4.0
—
6.0
—
ns
tWSD
tWSD2
tWSA
Data Set-up Time
0
2.0
0
—
—
—
0
2.0
0
—
—
—
0
2.0
0
—
—
—
0
2.0
0
—
—
—
0
2.0
0
—
—
—
0
3.0
0
—
—
—
0
5.0
0
—
—
—
ns
ns
ns
(2)
Data Set-up Time to WE HIGH
Address Set-up Time
(tW = minimum)
tWSCS
tWHD
Chip Select Set-up Time
Data Hold Time
0
—
—
0
—
—
0
—
—
0
—
—
0
—
—
0
—
—
0
—
—
—
—
ns
ns
ns
ns
1.0
1.0
1.0
—
1.0
1.0
1.0
—
1.0
1.0
1.0
—
1.0
1.0
1.0
—
1.0
1.0
1.0
—
1.0
1.0
1.0
—
1.0
1.0
1.0
—
tWHA
tWHCS
tWS
Address Hold Time
Chip Select Hold Time
Write Disable Time
Write Recovery Time
—
—
—
—
—
—
—
—
—
—
—
—
2.7
2.7
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
5.0 ns
5.0 ns
2760 tbl 08
(3)
tWR
—
—
—
—
—
—
—
NOTE:
1. Input and Output reference level is 50% point of waveform.
2. tWSD is specified with respect to the falling edge of WE for compatibility with bipolar part specifications, but this device actually only requires tWSD2 with
respect to rising edge of WE.
3. tWR is defined as the time to reflect the newly written data on the Data Outputs (Q0 to Q3) when no new Address Transition occurs.
WRITE CYCLE TIMING DIAGRAM
CS
tWSCS
tWSA
tWSD
tWHCS
tWHA
ADDR
DATAIN
WE
tWHD
tWSD2
tW
tWS
tWR
DATAOUT
2670 drw 11
6
IDT10474, IDT100474, IDT101474, IDT10A474, IDT100A474, IDT101A474
HIGH-SPEED BiCMOS ECL STATIC RAM 4K (1K x 4-BIT) SRAM
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
nnnnn
aa
nn
a
a
IDT
Device Type Architecture
Speed Package
Process/
Temp. Range
Blank
B(1)
Commercial
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
DF
U(1)
Y
CERDIP
Hi-Rel Die for MCMs and/or Hybrids
Plastic SOJ
2.7
3
3.5
4
4.5
5
Speed in Nanoseconds
Standard Architecture
7
8
10
15
S
10474
4K (1K x 4-bits) BiCMOS ECL-10K
Corner-Power Pin Static RAM
10A474 4K (1K x 4-bits) BiCMOS ECL-10K
Center-Power Pin Static RAM
100474 4K (1K x 4-bits) BiCMOS ECL-100K
Corner-Power Pin Static RAM
100A474 4K (1K x 4-bits) BiCMOS ECL-100K
Center-Power Pin Static RAM
101474 4K (1K x 4-bits) BiCMOS ECL-101K
Corner-Power Pin Static RAM
101A474 4K (1K x 4-bits) BiCMOS ECL-101K
Center-Power Pin Static RAM
NOTE:
1. Please contact your IDT Sales Representative for more information on
specifications and availability of Military and Die products.
2760 drw 12
Integrated Device Technology, Inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible product.
Integrated Device Technology, Inc.
2975 Stender Way, Santa Clara, CA 95054-3090
Telephone: (408) 727-6116
FAX 408-492-8674
7
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