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IDT2308-1HPGGI8

更新时间：2024-09-18 14:25:11
品牌：IDT
描述：PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, TSSOP-16

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IDT2308-1HPGGI8 概述

PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, TSSOP-16 时钟驱动器

IDT2308-1HPGGI8 规格参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP16,.25针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.02
系列：2308输入调节：STANDARD
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：5 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
最大I（ol）：0.012 A湿度敏感等级：1
功能数量：1反相输出次数：
端子数量：16实输出次数：8
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.2 ns
座面最大高度：1.2 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：4.4 mm最小 fmax：133.3 MHz
Base Number Matches：1

IDT2308-1HPGGI8 数据手册

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3.3V ZERO DELAY  
CLOCK MULTIPLIER  
IDT2308  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution for Applications ranging  
from 10MHz to 133MHz operating frequency  
• Distributes one clock input to two banks of four outputs  
• Separate output enable for each output bank  
• External feedback (FBK) pin is used to synchronize the outputs  
to the clock input  
The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is  
designedtoaddresshigh-speedclockdistributionandmultiplicationapplica-  
tions.Thezerodelayisachievedbyaligningthephasebetweentheincoming  
clockandtheoutputclock,operablewithintherangeof10to133MHz.  
TheIDT2308hastwobanksoffouroutputseachthatarecontrolledviatwo  
selectaddresses.Byproperselectionofinputaddresses,bothbankscanbe  
putintri-statemode.Intestmode,thePLListurnedoff,andtheinputclockdirectly  
drivestheoutputsforsystemtestingpurposes.Intheabsenceofaninputclock,  
theIDT2308enterspowerdown,andtheoutputsaretri-stated.Inthismode,  
the device willdrawless than25µA.  
• Output Skew <200 ps  
• Low jitter <200 ps cycle-to-cycle  
• 1x, 2x, 4x output options (see table):  
– IDT2308-1 1x  
– IDT2308-2 1x, 2x  
– IDT2308-3 2x, 4x  
– IDT2308-4 2x  
– IDT2308-1H / -5H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
TheIDT2308isavailableinsixuniqueconfigurationsforbothpre-scaling  
andmultiplicationoftheInputREFClock.(Seeavailableoptions table.)  
ThePLLisclosedexternallytoprovidemoreflexibilitybyallowingtheuser  
tocontrolthedelaybetweentheinputclockandtheoutputs.  
TheIDT2308ischaracterizedforbothIndustrialandCommercialoperation.  
• Available in SOIC and TSSOP packages  
FUNCTIONALBLOCKDIAGRAM  
(-3, -4)  
16  
2
FBK  
REF  
2
CLKA1  
PLL  
1
2
(-5)  
3
CLKA2  
14  
CLKA3  
15  
CLKA4  
8
9
S2  
S1  
Control  
Logic  
2
(-2, -3)  
6
CLKB1  
CLKB2  
CLKB3  
CLKB4  
7
10  
11  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
NOVEMBER 2001  
1
c
2001 Integrated Device Technology, Inc.  
DSC 5173/3  
IDT2308  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
PINCONFIGURATION  
ABSOLUTEMAXIMUMRATINGS(1)  
Symbol  
Rating  
Max.  
–0.5to+4.6  
–0.5to+5.5  
–0.5to  
Unit  
V
VDD  
SupplyVoltageRange  
InputVoltageRange(REF)  
InputVoltageRange  
(except REF)  
(2)  
VI  
V
1
2
16  
15  
14  
13  
12  
REF  
FBK  
VI  
V
CLKA1  
CLKA4  
CLKA3  
VDD  
VDD+0.5  
–50  
3
IIK (VI < 0)  
IOK  
InputClampCurrent  
TerminalVoltagewithRespect  
mA  
mA  
CLKA2  
VDD  
±50  
4
5
6
SO16-8  
SO16-10  
(VO < 0 or VO > VDD) to GND (inputs VIH 2.5, VIL 2.5)  
GND  
CLKB1  
CLKB2  
GND  
IO  
ContinuousOutputCurrent  
±50  
mA  
(VO = 0 to VDD)  
VDD or GND  
TA = 55°C  
CLKB4  
CLKB3  
S1  
11  
10  
9
ContinuousCurrent  
±100  
0.7  
mA  
W
7
8
MaximumPowerDissipation  
(3)  
(instillair)  
S2  
TSTG  
StorageTemperatureRange  
CommercialTemperature  
Range  
–65to+150  
0 to +70  
° C  
° C  
Operating  
Temperature  
Operating  
Temperature  
NOTES:  
SOIC/ TSSOP  
TOP VIEW  
IndustrialTemperature  
Range  
-40to+85  
° C  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
PINDESCRIPTION  
2. The input and output negative-voltage ratings may be exceeded if the input and output  
clamp-current ratings are observed.  
Pin Number  
FunctionalDescription  
REF (1)  
CLKA1(2)  
CLKA2(2)  
VDD  
1
2
InputReferenceClock,5VoltTolerantInput  
Clock Output for Bank A  
Clock Output for Bank A  
3.3V Supply  
3. The maximum package power dissipation is calculated using a junction temperature  
of 150°C and a board trace length of 750 mils.  
3
4
GND  
5
Ground  
CLKB1(2)  
CLKB2(2)  
S2(3)  
6
Clock Output for Bank B  
Clock Output for Bank B  
SelectInput, Bit2  
APPLICATIONS:  
• SDRAM  
• Telecom  
7
8
S1(3)  
9
SelectInput, Bit1  
• Datacom  
• PC Motherboards/Workstations  
• Critical Path Delay Designs  
CLKB3(2)  
CLKB4(2)  
GND  
10  
11  
12  
13  
14  
15  
16  
Clock Output for Bank B  
Clock Output for Bank B  
Ground  
VDD  
3.3V Supply  
CLKA3(2)  
CLKA4(2)  
FBK  
Clock Output for Bank A  
Clock Output for Bank A  
PLLFeedbackInput  
NOTES:  
1. Weak pull down.  
2. Weak pull down on all outputs.  
3. Weak pull ups on these inputs.  
2
IDT2308  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
FUNCTION TABLE(1)SELECTINPUTDECODING  
S2  
S1  
CLK A  
Tri-State  
Driven  
Driven  
Driven  
CLK B  
Tri-State  
Tri-State  
Driven  
Output Source  
PLL Shut Down  
L
L
PLL  
PLL  
REF  
PLL  
Y
N
Y
N
L
H
L
H
H
H
Driven  
NOTE:  
1. H = HIGH Voltage Level  
L = LOW Voltage Level  
AVAILABLEOPTIONSFORIDT2308  
Device  
IDT2308-1  
IDT2308-1H  
IDT2308-2  
IDT2308-2  
IDT2308-3  
IDT2308-3  
IDT2308-4  
IDT2308-5H  
FeedbackFrom  
Bank A or Bank B  
Bank A or Bank B  
Bank A  
BankAFrequency  
BankBFrequency  
Reference  
Reference  
Reference  
Reference  
Reference  
Reference/2  
Bank B  
2xReference  
2xReference  
4xReference  
2xReference  
Reference/2  
Reference  
(1)  
Bank A  
ReferenceorReference  
2 x Reference  
2 x Reference  
Reference/2  
Bank B  
Bank A or Bank B  
Bank A or Bank B  
NOTE:  
1. Output phase is indeterminant (0° or 180° from input clock).  
3
IDT2308  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
ZERO DELAY AND SKEW CONTROL  
Toclose the feedbackloopofthe IDT2308,the FBKpincanbe drivenfromanyofthe eightavailable outputpins.The outputdrivingthe FBKpinwill  
be drivinga totalloadof7pFplus anyadditionalloadthatitdrives.The relative loadingofthis output(withrespecttothe remainingoutputs)canadjust  
theinput-outputdelay.  
Forapplications requiringzeroinput-outputdelay, alloutputs includingthe one providingfeedbackshouldbe equallyloaded. Ifinput-outputdelay  
adjustmentsarerequired,usetheOutputLoadDifferenceCharttocalculateloadingdifferencesbetweenthefeedbackoutputandremainingoutputs.Ensure  
the outputs are loadedequally,forzerooutput-outputskew.  
REF TO CLKA/CLKB DELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN FBK PIN AND CLKA/CLKB PINS  
1500  
1000  
500  
0
-30  
-25  
-20  
-10  
0
5
30  
-15  
-5  
10  
15  
20  
25  
-500  
-1000  
-1500  
OUTPUT LOAD DIFFERENCE BETWEEN FBK PIN AND CLKA/CLKB PINS ( pF)  
4
IDT2308  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
OPERATINGCONDITIONS-COMMERCIAL  
Symbol  
VDD  
TA  
Parameter  
Test Conditions  
Min.  
3
Max.  
3.6  
70  
Unit  
V
SupplyVoltage  
OperatingTemperature(AmbientTemperature)  
LoadCapacitancebelow100MHz  
LoadCapacitancefrom100MHzto133MHz  
InputCapacitance(1)  
0
°C  
pF  
CL  
—
—
—
30  
15  
pF  
CIN  
7
pF  
NOTE:  
1. Applies to both REF and FBK.  
DCELECTRICALCHARACTERISTICS-COMMERCIAL  
Symbol  
Parameter  
Conditions  
Min.  
—
2
Typ.(1)  
—
Max.  
0.8  
—
Unit  
V
VIL  
InputLOWVoltageLevel  
Input HIGH Voltage Level  
InputLOWCurrent  
Input HIGH Current  
OutputLOWVoltage  
VIH  
—
V
IIL  
VIN = 0V  
—
—
—
—
50  
µ A  
µ A  
V
IIH  
VIN = VDD  
—
100  
0.4  
VOL  
IOL = 8mA (-1, -2, -3, -4)  
IOL = 12mA (-1H, -5H)  
IOH = -8mA (-1, -2, -3, -4)  
IOH = -12mA (-1H, -5H)  
REF = 0MHz (S2 = S1 = H)  
—
VOH  
OutputHIGHVoltage  
Power Down Current  
2.4  
—
—
V
IDD_PD  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12  
45  
70  
32  
50  
18  
30  
µ A  
100MHz CLKA (-1, -2, -3, -4)  
100MHz CLKA (-1H, -5H)  
66MHz CLKA (-1, -2, -3, -4)  
66MHz CLKA (-1H, -5H)  
33MHz CLKA (-1, -2, -3, -4)  
33MHz CLKA (-1H, -5H)  
IDD  
SupplyCurrent  
UnloadedOutputs  
mA  
Select Inputs at VDD or GND  
5
IDT2308  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
SWITCHINGCHARACTERISTICS-COMMERCIAL  
Symbol  
Parameter  
Conditions  
Min.  
10  
Typ.  
Max.  
100  
Unit  
MHz  
MHz  
MHz  
%
t1  
t1  
t1  
OutputFrequency  
30pFLoad,alldevices  
OutputFrequency  
20pF Load, -1H, -5H Devices(1)  
15pF Load, -1, -2, -3, -4 devices  
Measured at 1.4V, FOUT = 66.66MHz  
30pFLoad  
10  
133.3  
133.3  
60  
OutputFrequency  
10  
Duty Cycle = t2 ÷ t1  
(-1, -2, -3, -4, -1H, -5H)  
40  
50  
50  
Duty Cycle = t2 ÷ t1  
Measured at 1.4V, FOUT = 50MHz  
15pFLoad  
45  
55  
%
(-1, -2, -3, -4, -1H, -5H)  
Rise Time (-1, -2, -3, -4)  
Rise Time (-1, -2, -3, -4)  
Rise Time (-1H, -5H)  
t3  
t3  
t3  
t4  
t4  
t4  
t5  
Measuredbetween0.8Vand2V,30pFLoad  
Measuredbetween0.8Vand2V,15pFLoad  
Measuredbetween0.8Vand2V,30pFLoad  
Measuredbetween0.8Vand2V,30pFLoad  
Measuredbetween0.8Vand2V,15pFLoad  
Measuredbetween0.8Vand2V,30pFLoad  
Alloutputsequallyloaded  
2.2  
1.5  
1.5  
2.2  
1.5  
1.25  
200  
ns  
ns  
ns  
ns  
ns  
ns  
ps  
Fall Time (-1, -2, -3, -4)  
Fall Time (-1, -2, -3, -4)  
Fall Time (-1H, -5H)  
OutputtoOutputSkewonsame Bank  
(-1, -2, -3, -4)  
Output to Output Skew (-1H, -5H)  
Output Bank A to Output Bank B (-1, -4, -5H)  
Output Bank A to Output Bank B Skew (-2, -3)  
Alloutputsequallyloaded  
Alloutputsequallyloaded  
Alloutputsequallyloaded  
200  
200  
400  
ps  
ps  
ps  
t6  
t7  
t8  
Delay, REF Rising Edge to FBK Rising Edge  
Device to Device Skew  
MeasuredatVDD/2  
0
0
±250  
700  
ps  
ps  
Measured at VDD/2 on the FBK pins of devices  
Measured between 0.8V and 2V on -1H, -5H device  
usingTestCircuit2  
OutputSlewRate  
1
V/ns  
tJ  
Cycle to Cycle Jitter  
(-1, -1H, -4, -5H)  
Measuredat66.67MHz,loadedoutputs,15pFLoad  
Measuredat66.67MHz,loadedoutputs,30pFLoad  
Measuredat133.3MHz,loadedoutputs,15pFLoad  
Measuredat66.67MHz,loadedoutputs,30pFLoad  
Measuredat66.67MHz,loadedoutputs,15pFLoad  
Stable Power Supply, valid clocks presented  
on REF and FBK pins  
200  
200  
100  
400  
400  
1
ps  
ps  
tJ  
Cycle to Cycle Jitter  
(-2,-3)  
tLOCK  
PLLLockTime  
ms  
NOTE:  
1. IDT2308-5H has maximum input frequency of 133.33 MHz and maximum output of 66.67MHz.  
6
IDT2308  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
OPERATINGCONDITIONS-INDUSTRIAL  
Symbol  
VDD  
TA  
Parameter  
Test Conditions  
Min.  
3
Max.  
3.6  
+85  
30  
Unit  
V
SupplyVoltage  
OperatingTemperature(AmbientTemperature)  
LoadCapacitancebelow100MHz  
LoadCapacitancefrom100MHzto133MHz  
InputCapacitance(1)  
-40  
—
—
—
°C  
pF  
CL  
15  
pF  
CIN  
7
pF  
NOTE:  
1. Applies to both REF and FBK.  
DCELECTRICALCHARACTERISTICS-INDUSTRIAL  
Symbol  
Parameter  
Conditions  
Min.  
—
2
Typ.(1)  
—
Max.  
0.8  
—
Unit  
V
VIL  
InputLOWVoltageLevel  
Input HIGH Voltage Level  
InputLOWCurrent  
Input HIGH Current  
OutputLOWVoltage  
VIH  
—
V
IIL  
VIN = 0V  
—
—
—
—
50  
µ A  
µ A  
V
IIH  
VIN = VDD  
—
100  
0.4  
VOL  
IOL = 8mA (-1, -2, -3, -4)  
IOL = 12mA (-1H, -5H)  
IOH = -8mA (-1, -2, -3, -4)  
IOH = -12mA (-1H, -5H)  
REF = 0MHz (S2 = S1 = H)  
—
VOH  
OutputHIGHVoltage  
Power Down Current  
2.4  
—
—
V
IDD_PD  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25  
45  
70  
32  
50  
18  
30  
µ A  
100MHz CLKA (-1, -2, -3, -4)  
100MHz CLKA (-1H, -5H)  
66MHz CLKA (-1, -2, -3, -4)  
66MHz CLKA (-1H, -5H)  
33MHz CLKA (-1, -2, -3, -4)  
33MHz CLKA (-1H, -5H)  
IDD  
SupplyCurrent  
UnloadedOutputs  
mA  
Select Inputs at VDD or GND  
7
IDT2308  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
SWITCHINGCHARACTERISTICS-INDUSTRIAL  
Symbol  
Parameter  
Conditions  
Min.  
10  
Typ.  
Max.  
100  
Unit  
MHz  
MHz  
MHz  
%
t1  
t1  
t1  
OutputFrequency  
30pFLoad,alldevices  
OutputFrequency  
20pF Load, -1H, -5H Devices(1)  
15pF Load, -1, -2, -3, -4 devices  
Measured at 1.4V, FOUT = 66.66MHz  
30pFLoad  
10  
133.3  
133.3  
60  
OutputFrequency  
10  
Duty Cycle = t2 ÷ t1  
(-1, -2, -3, -4, -1H, -5H)  
40  
50  
50  
Duty Cycle = t2 ÷ t1  
Measured at 1.4V, FOUT = 50MHz  
15pFLoad  
45  
55  
%
(-1, -2, -3, -4, -1H, -5H)  
Rise Time (-1, -2, -3, -4)  
Rise Time (-1, -2, -3, -4)  
Rise Time (-1H, -5H)  
t3  
t3  
t3  
t4  
t4  
t4  
t5  
Measuredbetween0.8Vand2V,30pFLoad  
Measuredbetween0.8Vand2V,15pFLoad  
Measuredbetween0.8Vand2V,30pFLoad  
Measuredbetween0.8Vand2V,30pFLoad  
Measuredbetween0.8Vand2V,15pFLoad  
Measuredbetween0.8Vand2V,30pFLoad  
Alloutputsequallyloaded  
2.2  
1.5  
1.5  
2.5  
1.5  
1.25  
200  
ns  
ns  
ns  
ns  
ns  
ns  
ps  
Fall Time (-1, -2, -3, -4)  
Fall Time (-1, -2, -3, -4)  
Fall Time (-1H, -5H)  
OutputtoOutputSkewonsame Bank  
(-1, -2, -3, -4)  
Output to Output Skew (-1H, -5H)  
Output Bank A to Output Bank B (-1, -4, -5H)  
Output Bank A to Output Bank B Skew (-2, -3)  
Alloutputsequallyloaded  
Alloutputsequallyloaded  
Alloutputsequallyloaded  
200  
200  
400  
ps  
ps  
ps  
t6  
t7  
t8  
Delay, REF Rising Edge to FBK Rising Edge  
Device to Device Skew  
MeasuredatVDD/2  
0
0
±250  
700  
ps  
ps  
Measured at VDD/2 on the FBK pins of devices  
Measured between 0.8V and 2V on -1H, -5H device  
usingTestCircuit2  
OutputSlewRate  
1
V/ns  
tJ  
Cycle to Cycle Jitter  
(-1, -1H, -4, -5H)  
Measuredat66.67MHz,loadedoutputs,15pFLoad  
Measuredat66.67MHz,loadedoutputs,30pFLoad  
Measuredat133.3MHz,loadedoutputs,15pFLoad  
Measuredat66.67MHz,loadedoutputs,30pFLoad  
Measuredat66.67MHz,loadedoutputs,15pFLoad  
Stable Power Supply, valid clocks presented  
on REF and FBK pins  
200  
200  
100  
400  
400  
1
ps  
ps  
tJ  
Cycle to Cycle Jitter  
(-2,-3)  
tLOCK  
PLLLockTime  
ms  
NOTE:  
1. IDT2308-5H has maximum input frequency of 133.33 MHz and maximum output of 66.67MHz.  
8
IDT2308  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
SWITCHINGWAVEFORMS  
t1  
t2  
1.4V  
1.4V  
1.4V  
Duty Cycle Timing  
3.3V  
0V  
0.8V  
t3  
0.8V  
2V  
2V  
Output  
t4  
All Outputs Rise/Fall Time  
1.4V  
Output  
1.4V  
Output  
t5  
Output to Output Skew  
V
DD/2  
Input  
FBK  
VDD/2  
t6  
Input to Output Propagation Delay  
VDD/2  
FBK, Device 1  
FBK, Device 2  
V
DD/2  
t7  
Device to Device Skew  
9
IDT2308  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2308-1, 2, 3, AND 4  
Duty Cycle vs VDD  
Duty Cycle vs VDD  
(for 30pf loads over frequency - 3.3V, 25C)  
(for 15pF loads over frequency - 3.3V, 25C)  
60  
58  
56  
60  
58  
56  
54  
52  
54  
52  
33MHz  
33MHz  
50  
48  
46  
44  
50  
48  
46  
44  
66MHz  
100MHz  
66MHz  
100MHz  
133MHz  
42  
40  
42  
40  
3
3.4  
3
3.4  
3.1  
3.3  
3.5  
3.6  
3.1  
3.3  
3.5  
3.6  
3.2  
3.2  
VDD (V)  
VDD (V)  
Duty Cycle vs Frequency  
(for 30pf loads over temperature - 3.3V)  
Duty Cycle vs Frequency  
(for 15pF loads over temperature - 3.3V)  
60  
58  
56  
60  
58  
56  
54  
52  
54  
52  
-40C  
-40C  
0C  
25C  
70C  
85C  
50  
48  
46  
44  
0C  
50  
48  
46  
44  
25C  
70C  
85C  
42  
40  
42  
40  
20  
40  
80  
100  
120  
140  
60  
20  
40  
80  
100  
120  
140  
60  
Frequency (MHz)  
Frequency (MHz)  
IDD vs Number of Loaded Outputs  
(for 30pf loads over frequency - 3.3V, 25C)  
IDD vs Number of Loaded Outputs  
(for 15pF loads over frequency - 3.3V, 25C)  
140  
120  
140  
120  
100  
80  
100  
80  
60  
33MHz  
33MHz  
66MHz  
100MHz  
66MHz  
100MHz  
60  
40  
20  
0
40  
20  
0
0
2
4
8
0
2
6
4
8
6
Number of Loaded Outputs  
Number of Loaded Outputs  
NOTES:  
1. Duty Cycle is taken from typical chip measured at 1.4V.  
2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the Unloaded Current (n = Number of Outputs; C = Capacitance Load per Output (F); V = Voltage Supply(V);  
f = Frequency (Hz).  
10  
IDT2308  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
TYPICAL DUTY CYCLE(1) AND IDD TRENDS(2) FOR IDT2308-1H AND 5H  
Duty Cycle vs VDD  
Duty Cycle vs VDD  
(for 30pf loads over frequency - 3.3V, 25C)  
(for 15pF loads over frequency - 3.3V, 25C)  
60  
58  
56  
60  
58  
56  
54  
52  
54  
52  
33MHz  
33MHz  
50  
48  
46  
44  
50  
48  
46  
44  
66MHz  
100MHz  
66MHz  
100MHz  
133MHz  
42  
40  
42  
40  
3
3.4  
3
3.4  
3.1  
3.3  
3.5  
3.6  
3.1  
3.3  
3.5  
3.6  
3.2  
3.2  
VDD (V)  
VDD (V)  
Duty Cycle vs Frequency  
(for 30pf loads over temperature - 3.3V)  
Duty Cycle vs Frequency  
(for 15pF loads over temperature - 3.3V)  
60  
58  
60  
58  
56  
56  
54  
52  
54  
52  
-40C  
-40C  
50  
48  
46  
44  
0C  
50  
48  
46  
44  
0C  
25C  
70C  
85C  
25C  
70C  
85C  
42  
40  
42  
40  
20  
40  
80  
100  
120  
140  
60  
20  
40  
80  
100  
120  
140  
60  
Frequency (MHz)  
Frequency (MHz)  
IDD vs Number of Loaded Outputs  
(for 30pf loads over frequency - 3.3V, 25C)  
IDD vs Number of Loaded Outputs  
(for 15pF loads over frequency - 3.3V, 25C)  
160  
140  
160  
140  
120  
120  
100  
80  
100  
80  
33MHz  
33MHz  
66MHz  
66MHz  
100MHz  
100MHz  
60  
60  
40  
20  
0
40  
20  
0
0
2
4
8
0
2
6
4
8
6
Number of Loaded Outputs  
Number of Loaded Outputs  
NOTES:  
1. Duty Cycle is taken from typical chip measured at 1.4V.  
2. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the Unloaded Current (n = Number of Outputs; C = Capacitance Load per Output (F); V = Voltage Supply(V);  
f = Frequency (Hz).  
11  
IDT2308  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
TESTCIRCUITS  
TEST CIRCUIT 1  
TEST CIRCUIT 1  
VDD  
VDD  
1KΩ  
1KΩ  
CLK  
OUT  
10pF  
CLK  
OUT  
0.1µ F  
0.1µ F  
0.1µ F  
OUTPUTS  
OUTPUTS  
C
LOAD  
VDD  
GND  
VDD  
0.1µ F  
GND  
GND  
GND  
Test Circuit for t8, Output Slew Rate On -1H, -5H Device  
Test Circuit for all Parameters Except t8  
12  
IDT2308  
3.3VZERODELAYCLOCKMULTIPLIER  
COMMERCIALANDINDUSTRIALTEMPERATURERANGES  
ORDERINGINFORMATION  
XXXXX  
XX  
X
IDT  
Package Process  
Device Type  
Blank  
I
Commercial (0oC to +70oC)  
Industrial (-40oC to +85oC)  
DC  
PG  
Small Outline (SO16-8)  
Thin Shrink Small Outline Package (SO16-10)  
2308-1  
2308-2  
2308-3  
2308-4  
2308-1H  
2308-5H  
Zero Delay Clock Buffer With Standard Drive  
}
}
Zero Delay Clock Buffer with High Drive  
Ordering Code  
PackageType  
OperatingRange  
Commercial  
Industrial  
IDT2308-1DC  
IDT2308-1DCI  
IDT2308-1HDC  
IDT2308-1HDCI  
IDT2308-1HPG  
IDT2308-1HPGI  
IDT2308-2DC  
IDT2308-2DCI  
IDT2308-3DC  
IDT2308-3DCI  
IDT2308-4DC  
IDT2308-4DCI  
IDT2308-5HDC  
IDT2308-5HDCI  
IDT2308-5HPG  
IDT2308-5HPGI  
16-Pin SOIC  
16-Pin SOIC  
16-Pin SOIC  
16-Pin SOIC  
16-Pin TSSOP  
16-Pin TSSOP  
16-Pin SOIC  
16-Pin SOIC  
16-Pin SOIC  
16-Pin SOIC  
16-Pin SOIC  
16-Pin SOIC  
16-Pin SOIC  
16-Pin SOIC  
16-Pin TSSOP  
16-Pin TSSOP  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
CORPORATE HEADQUARTERS  
2975StenderWay  
Santa Clara, CA 95054  
for SALES:  
for Tech Support:  
logichelp@idt.com  
(408) 654-6459  
800-345-7015 or 408-727-6116  
fax: 408-492-8674  
www.idt.com  
13  

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