IDT23S08T-1DCG [IDT]
PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, GREEN, SOIC-16;
| 型号： | IDT23S08T-1DCG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, GREEN, SOIC-16 光电二极管 |
| 文件： | 总6页 (文件大小：59K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5V ZERO DELAY CLOCK
MULTIPLIER, SPREAD
SPECTRUM COMPATIBLE
IDT23S08T
ADVANCE
INFORMATION
FEATURES:
DESCRIPTION:
• Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the outputs
to the clock input
TheIDT23S08Tis ahigh-speedphase-lockloop(PLL)clockmultiplier.It
isdesignedtoaddresshigh-speedclockdistributionandmultiplicationapplica-
tions.Thezerodelayisachievedbyaligningthephasebetweentheincoming
clockandtheoutputclock,operablewithintherangeof10to133MHz.
TheIDT23S08Thastwobanksoffouroutputseachthatarecontrolledvia
twoselectaddresses.Byproperselectionofinputaddresses,bothbankscan
beputintri-statemode.Intestmode,thePLListurnedoff,andtheinputclock
directlydrives theoutputs forsystemtestingpurposes.Intheabsenceofan
inputclock,theIDT23S08Tenterspowerdown.Inthismode,thedevicewill
drawlessthan12µA,andtheoutputsaretri-stated.
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1/2x, 1x, 2x, 4x output options (see table):
– IDT23S08T-1 1x
– IDT23S08T-2 1x, 2x
– IDT23S08T-3 2x, 4x
– IDT23S08T-4 2x
The IDT23S08T is available in six unique configurations for both pre-
scaling and multiplication of the Input REF Clock. (See available options
table.)
– IDT23S08T-5 1/2x
• No external RC network required
• Operates at 2.5V VDD
ThePLLisclosedexternallytoprovidemoreflexibilitybyallowingtheuser
tocontrolthedelaybetweentheinputclockandtheoutputs.
TheIDT23S08TischaracterizedforCommercialoperation.
• Spread spectrum compatible
• Available in SOIC package
FUNCTIONALBLOCKDIAGRAM
(-3, -4)
16
2
FBK
REF
2
CLKA1
PLL
1
2
3
(-5)
CLKA2
14
CLKA3
15
CLKA4
8
9
S2
S1
Control
Logic
2
(-2, -3)
6
CLKB1
CLKB2
CLKB3
CLKB4
7
10
11
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
MARCH 2006
1
c
2006 Integrated Device Technology, Inc.
DSC - 6510/6
IDT23S08T
2.5VZERODELAYCLOCKMULTIPLIER
COMMERCIALTEMPERATURERANGE
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
Rating
Max.
–0.5to+4.6
–0.5to+5.5
–0.5to
Unit
V
VDD
SupplyVoltageRange
InputVoltageRange(REF)
InputVoltageRange
(exceptREF)
(2)
VI
V
1
2
16
15
14
13
12
REF
FBK
VI
V
CLKA1
CLKA4
CLKA3
VDD
VDD+0.5
–50
3
IIK (VI < 0)
IO
InputClampCurrent
ContinuousOutputCurrent
mA
mA
CLKA2
±50
4
5
6
VDD
(VO = 0 to VDD)
VDD or GND
TA = 55°C
GND
CLKB1
CLKB2
GND
ContinuousCurrent
±100
0.7
mA
W
MaximumPowerDissipation
CLKB4
CLKB3
S1
11
10
9
(3)
(instillair)
7
8
TSTG
StorageTemperatureRange
CommercialTemperature
Range
–65to+150
0 to +70
° C
° C
Operating
Temperature
NOTES:
S2
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
SOIC
TOP VIEW
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
PINDESCRIPTION
Pin Number
FunctionalDescription
REF (1)
CLKA1(2)
CLKA2(2)
VDD
1
2
InputReferenceClock,3.3VTolerantInput
Clock Output for Bank A
Clock Output for Bank A
2.5V Supply
3
4
GND
5
Ground
CLKB1(2)
CLKB2(2)
S2(3)
6
Clock Output for Bank B
Clock Output for Bank B
SelectInput, Bit2
APPLICATIONS:
• SDRAM
• Telecom
7
8
S1(3)
9
SelectInput, Bit1
• Datacom
• PC Motherboards/Workstations
• Critical Path Delay Designs
CLKB3(2)
CLKB4(2)
GND
10
11
12
13
14
15
16
Clock Output for Bank B
Clock Output for Bank B
Ground
VDD
2.5V Supply
CLKA3(2)
CLKA4(2)
FBK
Clock Output for Bank A
Clock Output for Bank A
PLLFeedbackInput
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
2
IDT23S08T
2.5VZERODELAYCLOCKMULTIPLIER
COMMERCIALTEMPERATURERANGE
FUNCTION TABLE(1)SELECTINPUTDECODING
S2
L
S1
L
CLK A
Tri-State
Driven
Driven
Driven
CLK B
Tri-State
Tri-State
Driven
Output Source
PLL Shut Down
PLL
PLL
REF
PLL
Y
N
Y
N
L
H
L
H
H
H
Driven
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
AVAILABLEOPTIONSFORIDT23S08T
Device
FeedbackFrom
Bank A or Bank B
Bank A
BankAFrequency
BankBFrequency
IDT23S08T-1
Reference
Reference
Reference
Reference/2
(1)
IDT23S08T-2
(1)
IDT23S08T-2
Bank B
2xReference
2xReference
4xReference
2xReference
Reference/2
Reference
(1)
(2)
IDT23S08T-3
Bank A
ReferenceorReference
2 x Reference
2 x Reference
Reference/2
(1)
IDT23S08T-3
Bank B
(1)
IDT23S08T-4
Bank A or Bank B
Bank A or Bank B
(1)
IDT23S08T-5
NOTES:
1. Contact factory for availability.
2. Output phase is indeterminant (0° or 180° from input clock).
SPREAD SPECTRUM COMPATIBLE
Manysystems beingdesignednowuse a technologycalledSpreadSpectrumFrequencyTimingGeneration. This productis designednottofilter
offtheSpreadSpectrumfeatureofthereferenceinput,assumingitexists. WhenazerodelaybufferisnotdesignedtopasstheSpreadSpectrumfeature
through,the resultis a significantamountoftrackingskew,whichmaycause problems insystems requiringsynchronization.
ZERO DELAY AND SKEW CONTROL
Toclose the feedbackloopofthe IDT23S08T, the FBKpincanbe drivenfromanyofthe eightavailable outputpins. The outputdrivingthe FBKpin
willbedrivingatotalloadof7pFplus anyadditionalloadthatitdrives.Therelativeloadingofthis output(withrespecttotheremainingoutputs)canadjust
theinput-outputdelay.
Forapplications requiringzeroinput-outputdelay,alloutputs includingtheoneprovidingfeedbackshouldbeequallyloaded. Ensuretheoutputs are
loadedequally,forzerooutput-outputskew.
OPERATINGCONDITIONS
Symbol
VDD
TA
Parameter
Test Conditions
Min.
2.3
0
Max.
2.7
70
Unit
V
SupplyVoltage
OperatingTemperature(AmbientTemperature)
LoadCapacitance from10MHzto133MHz
InputCapacitance(1)
°C
pF
CL
—
—
15
CIN
7
pF
NOTE:
1. Applies to both REF and FBK.
3
IDT23S08T
2.5VZERODELAYCLOCKMULTIPLIER
COMMERCIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICS
Symbol
VIL
Parameter
Conditions
Min.
—
1.7
—
—
—
2
Typ.(1)
—
Max.
0.7
—
50
Unit
V
InputLOWVoltageLevel
Input HIGH Voltage Level
InputLOWCurrent
Input HIGH Current
OutputLOWVoltage
OutputHIGHVoltage
Power Down Current
VIH
—
V
IIL
VIN = 0V
—
µ A
µ A
V
IIH
VIN = VDD
IOL = 8mA
IOH = -8mA
—
100
0.3
—
12
VOL
VOH
IDD_PD
—
—
V
REF = 0MHz (S2 = S1 = H)
—
—
—
—
—
µ A
100MHz CLKA
66MHz CLKA
—
45
IDD
SupplyCurrent
UnloadedOutputs
—
32
mA
Select Inputs at VDD or GND 33MHz CLKA
—
18
SWITCHINGCHARACTERISTICS
Symbol Parameter
Conditions
Min.
10
Typ.
—
Max.
133.3
60
Unit
t1
OutputFrequency
15pFLoad
MHz
%
Duty Cycle = t2 ÷ t1
Measured at VDD/2, FOUT = 66.66MHz, 15pF Load
Measuredbetween0.7Vand1.7V,15pFLoad
Measuredbetween0.7Vand1.7V,15pFLoad
Alloutputsequallyloaded
40
50
t3
t4
t5
RiseTime
—
—
—
—
2.5
ns
FallTime
—
2.5
ns
OutputtoOutputSkewonsame Bank
(-1, -2, -3, -4, -5)
—
200
ps
Output Bank A to Output Bank B (-1, -4, -5)
Output Bank A to Output Bank B Skew (-2, -3)
Alloutputsequallyloaded
Alloutputsequallyloaded
—
—
—
—
200
400
ps
ps
t6
t7
tJ
Delay, REF Rising Edge to FBK Rising Edge
Device to Device Skew
MeasuredatVDD/2
—
—
—
—
—
—
0
±350
700
200
200
400
1
ps
ps
ps
Measured at VDD/2 on the FBK pins of devices
Measuredat66.67MHz,loadedoutputs,15pFLoad
Measuredat133.3MHz,loadedoutputs,15pFLoad
Measuredat66.67MHz,loadedoutputs,15pFLoad
Stable Power Supply, valid clocks presented
on REF and FBK pins
0
Cycle to Cycle Jitter (-1, -4, -5)
—
—
—
—
tJ
Cycle to Cycle Jitter (-2, -3)
PLLLockTime
ps
tLOCK
ms
4
IDT23S08T
2.5VZERODELAYCLOCKMULTIPLIER
COMMERCIALTEMPERATURERANGE
SWITCHINGWAVEFORMS
t1
t2
VDD/2
VDD/2
VDD/2
Duty Cycle Timing
2.5V
0V
0.7V
t3
0.7V
1.7V 1.7V
Output
t4
All Outputs Rise/Fall Time
VDD/2
VDD/2
t5
Input
Output
Output
VDD/2
VDD/2
FBK
t6
Input to Output Propagation Delay
Output to Output Skew
VDD/2
TESTCIRCUIT
FBK, Device 1
FBK, Device 2
VDD/2
VDD
t7
CLKOUT
0.1μF
0.1μF
OUTPUTS
Device to Device Skew
CLOAD
VDD
GND
GND
Test Circuit for all Parameters
5
IDT23S08T
2.5VZERODELAYCLOCKMULTIPLIER
COMMERCIALTEMPERATURERANGE
ORDERINGINFORMATION
XXXXX
XX
X
IDT
Package Process
Device Type
o
o
Blank
Commercial (0 C to +70 C)
DC
DCG
Small Outline
SOIC - Green
23S08T-1
23S08T-2
23S08T-3
23S08T-4
23S08T-5
2.5V Zero Delay Clock Buffer, Spread
Spectrum Compatible
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
clockhelp@idt.com
www.idt.com
6
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