概述
规格参数
数据手册IDT29FCT52ADB 概述
FAST CMOS OCTAL REGISTERED TRANSCEIVERS 快速CMOS八路注册收发器 总线驱动器/收发器
IDT29FCT52ADB 规格参数
| 是否无铅： | 含铅 | 是否Rohs认证： | 不符合 |
| 生命周期： | Obsolete | 零件包装代码： | DIP |
| 包装说明： | DIP, DIP24,.3 | 针数： | 24 |
| Reach Compliance Code： | not_compliant | HTS代码： | 8542.39.00.01 |
| 风险等级： | 5.86 | Is Samacsys： | N |
| 其他特性： | INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; CLOCK ENABLE | 控制类型： | INDEPENDENT CONTROL |
| 计数方向： | BIDIRECTIONAL | 系列： | FCT |
| JESD-30 代码： | R-GDIP-T24 | JESD-609代码： | e0 |
| 长度： | 32.004 mm | 负载电容（CL）： | 50 pF |
| 逻辑集成电路类型： | REGISTERED BUS TRANSCEIVER | 最大I（ol）： | 0.048 A |
| 位数： | 8 | 功能数量： | 1 |
| 端口数量： | 2 | 端子数量： | 24 |
| 最高工作温度： | 125 °C | 最低工作温度： | -55 °C |
| 输出特性： | 3-STATE | 输出极性： | TRUE |
| 封装主体材料： | CERAMIC, GLASS-SEALED | 封装代码： | DIP |
| 封装等效代码： | DIP24,.3 | 封装形状： | RECTANGULAR |
| 封装形式： | IN-LINE | 峰值回流温度（摄氏度）： | 225 |
| 电源： | 5 V | Prop。Delay @ Nom-Sup： | 11 ns |
| 传播延迟（tpd）： | 11 ns | 认证状态： | Not Qualified |
| 筛选级别： | 38535Q/M;38534H;883B | 座面最大高度： | 5.08 mm |
| 子类别： | Bus Driver/Transceivers | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 4.5 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | NO | 技术： | CMOS |
| 温度等级： | MILITARY | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | THROUGH-HOLE | 端子节距： | 2.54 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | 20 |
| 翻译： | N/A | 触发器类型： | POSITIVE EDGE |
| 宽度： | 7.62 mm | Base Number Matches： | 1 |
IDT29FCT52ADB 数据手册
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PDF下载IDT29FCT52A/B/C
IDT29FCT53A/B/C
FAST CMOS
OCTAL REGISTERED
TRANSCEIVERS
Integrated Device Technology, Inc.
FEATURES:
• Equivalent to AMD’s Am2952/53 and National’s
29F52/53 in pinout/function
• IDT29FCT52A/53A equivalent to FAST speed
• IDT29FCT52B/53B 25% faster than FAST
• IDT29FCT52C/53C 37% faster than FAST
• IOL = 64mA (commercial) and 48mA (military)
• IIH and IIL only 5µA max.
DESCRIPTION:
The IDT29FCT52A/B/C and IDT29FCT53A/B/C are 8-bit
registered transceivers manufactured using an advanced
dual metal CMOS technology. Two 8-bit back-to-back regis-
ters store data flowing in both directions between two bidirec-
tional buses. Separate clock, clock enable and 3-state output
enable signals are provided for each register. Both A outputs
and B outputs are guaranteed to sink 64mA.
• CMOS power levels (2.5mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
The IDT29FCT52A/B/C is a non-inverting option of the
IDT29FCT53A/B/C.
• Available in 24-pin DIP, SOIC, 28-pin LCC with JEDEC
standard pinout
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAM(1)
CPA
CEA
OEB
CE CP
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
B
B
B
B
B
B
B
B
0
1
2
3
4
5
6
7
D
D
D
D
D
D
D
D
0
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
1
2
3
4
3
4
A
Reg.
5
6
7
5
6
7
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
6
7
D0
D1
D2
D3
D4
D5
D6
D7
B
Reg.
CE CP
OEA
CPB
CEB
NOTE:
2533 drw 01
1. IDT29FCT52 function is shown.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MAY 1992
1992 Integrated Device Technology, Inc.
7.1
DSC-4605/3
1
IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
1
24
Vcc
B
B
B
B
B
B
B
B
OEB
CPA
CEA
GND
7
6
5
4
3
2
1
0
23
22
2
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
4
3
2
28 27 26
3
5
25
24
23
22
21
20
19
A
A
A
5
4
3
B
B
B
4
3
2
1
P24-1, 21
4
6
D24-1,
E24-1
&
5
20
19
18
17
16
15
14
13
7
6
NC
NC
8
L28-1
7
SO24-2
9
A
A
A
2
1
0
B
B
1
0
8
10
11
9
OEB
10
11
12
OEA
CPB
CEB
12 13 14 15 16 17 18
DIP/CERPACK/SOIC
TOP VIEW
LCC
TOP VIEW
2533 drw 02
PIN DESCRIPTION
Name
I/O
I/O
I/O
I
Description
A0-7
Eight bidirectional lines carrying the A Register inputs or B Register outputs.
Eight bidirectional lines carrying the B Register inputs or A Register outputs.
B0-7
CPA
Clock for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition
of the CPA signal.
CEA
I
Clock Enable for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH
transition of the CPA signal. When CEA is HIGH, the A Register holds its contents, regardless of CPA signal
transitions.
OEB
CPB
CEB
I
I
I
OutputEnablefortheARegister. WhenOEB isLOW, theARegisteroutputsareenabledontotheB0-7 lines. When
OEB is HIGH, the B0-7 outputs are in the high-impedance state.
Clock for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition
of the CPB signal.
Clock Enable for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH
transition of the CPB signal. When CEB is HIGH, the B Register holds its contents, regardless of CPB signal
transitions.
OEA
I
OutputEnablefortheBRegister. WhenOEA isLOW, theBRegisteroutputsareenabledontotheA0-7 lines. When
OEA is HIGH, the A0-7 outputs are in the high-impedance state.
2533 tbl 01
REGISTER FUNCTION TABLE(1)
(Applies to A or B Register)
OUTPUT CONTROL(1)
Internal
Y-Outputs
Inputs
Internal
Q
X
L
52
Z
53
Function
OE
D
X
L
CP
X
Q
NC
L
Function
Hold Data
Load Data
CE
H
H
Z
H
L
Disable Outputs
Enable Outputs
L
L
L
↑
L
H
H
H
↑
L
H
NOTE:
2533 tbl 03
2533 tbl 02
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
NC = No Change
↑ = LOW-to-HIGH Transition
7.1
2
IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) Conditions
Typ. Max. Unit
Symbol
Rating
Commercial
Military
Unit
(2)
VTERM
Terminal Voltage
with Respect
to GND
–0.5 to +7.0 –0.5 to +7.0
V
CIN
Input
VIN = 0V
6
8
10
pF
Capacitance
(3)
CI/O
I/O
VOUT = 0V
12
pF
VTERM
Terminal Voltage
with Respect
to GND
–0.5 to VCC –0.5 to VCC
V
Capacitance
NOTE:
2533 tbl 05
1. This parameter is guaranteed by characterization data and not tested.
TA
Operating
0 to +70
–55 to +125 °C
Temperature
TBIAS
TSTG
Temperature
Under Bias
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
Storage
Temperature
PT
Power Dissipation
DC Output Current
0.5
0.5
W
mA
IOUT
120
120
NOTES:
2533 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed +0.5V unless otherwise noted.
2. Inputs and VCC terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
VIH
Parameter
Test Conditions(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Min.
2.0
—
Typ.(2)
Max.
—
Unit
V
Input HIGH Level
Input LOW Level
Input HIGH Current
(Except I/O Pins)
Input LOW Current
(Except I/O Pins)
Input HIGH Current
(I/O Pins Only)
—
VIL
—
0.8
5
5(4)
–5(4)
–5
V
IIH
VCC = Max.
VI =VCC
—
—
µA
VI = 2.7V
VI = 0.5V
VI = GND
VI = VCC
VI = 2.7V
VI = 0.5V
VI = GND
—
—
IIL
IIH
IIL
—
—
—
—
VCC = Max.
—
—
15
µA
—
—
15(4)
–15(4)
–15
–1.2
—
Input LOW Current
(I/O Pins Only)
—
—
—
—
VIK
IOS
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
Vcc = Min., IN = –18mA
Vcc = Max.(3), VO = GND
—
–0.7
–120
VCC
VCC
4.0
4.0
GND
GND
0.3
0.3
V
mA
V
–60
VHC
VHC
2.4
2.4
—
VOH
Vcc = 3V, VIN = VLC or VHC, IOH = –32µA
—
Vcc = Min.
IOH = –300µA
—
VIN = VIH or VIL
IOH = –15mA MIL.
IOH = –24mA COM’L.
—
—
VOL
Output LOW Voltage
Vcc = 3V, VIN = VLC or VHC, IOL = 300µA
VLC
V
(4)
Vcc = Min.
IOL = 300µA
—
VLC
VIN = VIH or VIL
IOL = 48mA MIL.(5)
IOL = 64mA COM’L.(5)
—
0.55
0.55
—
NOTES:
2533 tbl 06
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. These are maximum IOL values per output, for 8 outputs turned on simultaneously. Total maximum IOL (all outputs) is 512mA for commercial and
384mA for military. Derate IOL for number of outputs exceeding 8 turned on simultaneously.
7.1
3
IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC – 0.2V
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
ICC
Quiescent Power Supply
Current
VCC = Max.
VIN ≥ VHC; VIN ≤ VLC
—
0.5
1.5
µA
∆ICC
Quiescent Power Supply
Current TTL Inputs HIGH
Vcc = Max.
—
—
0.5
2.0
mA
VIN = 3.4V(3)
ICCD
Dynamic Power Supply
Current(4)
Vcc = Max.
Outputs Open
VIN ≥ VHC
VIN ≤ VLC
0.15
0.25
mA/
MHz
OEA or OEB= GND
One Input Toggling
50% Duty Cycle
IC
Total Power Supply
Current(6)
Vcc = Max.
Outputs Open
fCP = 10MHz
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
2.0
4.0
mA
50% Duty Cycle
OEA or OEB= GND
One Bit Toggling
at fi = 5MHz
VIN = 3.4V
VIN = GND
—
—
2.5
4.3
6.0
50% Duty Cycle
VCC = Max.
Outputs Open
fCP = 10MHz
VIN ≥ VHC
VIN ≤ VLC
(FCT)
7.8(5)
50% Duty Cycle
OEA or OEB = GND
Eight Bits Toggling
at fi = 2.5MHz
VIN = 3.4V
VIN = GND
—
6.5
16.8(5)
50% Duty Cycle
NOTES:
2533 tbl 07
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
7.1
4
IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT29FCT52A/53A
IDT29FCT52B/53B
IDT29FCT52C/53C
Com’l.
Mil.
Com’l.
Mil.
Com’l.
Mil.
(2)
(2)
(2)
(2)
(2)
(2)
Symbol
Parameter
Condition(1) Min.
Max. Min.
Max. Min.
Max. Min.
Max. Min.
Max. Min.
Max. Unit
tPLH
tPHL
Propagation Delay
CPA, CPB to An, Bn
CL = 50pF
RL = 500Ω
2.0 10.0 2.0 11.0 2.0
1.5 10.5 1.5 13.0 1.5
7.5
8.0
2.0
8.0
2.0
1.5
6.3 2.0
7.0 1.5
7.3
ns
tPZH
tPZL
Output Enable Time
OEA or OEB to
1.5
1.5
8.5
8.0
8.0
ns
An or Bn
tPHZ
tPLZ
Output Disable Time
OEA or OEB to
1.5 10.0 1.5 10.0 1.5
7.5
1.5
6.5 1.5
7.5
ns
An or Bn
tSU
tH
Set-up Time HIGH
or LOW An, Bn to
CPA, CPB
2.5
2.0
3.0
2.0
3.0
—
—
—
—
—
2.5
2.0
3.0
2.0
3.0
—
—
—
—
—
2.5
1.5
3.0
2.0
3.0
—
—
—
—
—
2.5
1.5
3.0
2.0
3.0
—
—
—
—
—
2.5
1.5
3.0
2.0
3.0
—
—
—
—
—
2.5
1.5
3.0
2.0
3.0
—
—
—
—
—
ns
ns
ns
ns
Hold Time HIGH
or LOW An, Bn to
CPA, CPB
tSU
tH
Set-up Time HIGH
or LOW CEA, CEB to
CPA, CPB
Hold Time HIGH
or LOW CEA, CEB to
CPA, CPB
Pulse Width, HIGH(3)
or LOW CPA or CPB
tW
ns
NOTES:
2533 tbl 08
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
7.1
5
IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC
SWITCH POSITION
Test
Switch
Closed
Open
7.0V
Open Drain
Disable Low
Enable Low
500Ω
VOUT
VIN
Pulse
Generator
D.U.T.
All Other Tests
50pF
CL
500Ω
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
2533 tbl 09
R T
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
1.5V
0V
DATA
INPUT
tSU
t H
LOW-HIGH-LOW
1.5V
3V
1.5V
0V
TIMING
INPUT
PULSE
t W
ASYNCHRONOUS CONTROL
t REM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
3V
1.5V
0V
t H
tSU
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
3V
CONTROL
INPUT
1.5V
0V
SAME PHASE
INPUT TRANSITION
1.5V
0V
tPZL
tPLZ
tPHL
tPLH
3.5V
1.5V
3.5V
OUTPUT
NORMALLY
LOW
VOH
SWITCH
CLOSED
OUTPUT
1.5V
0.3V
0.3V
VOL
VOH
tPZH
tPHZ
VOL
tPLH
tPHL
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
3V
1.5V
0V
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
0V
NOTES
2533 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
7.1
6
IDT29FCT52A/B/C, IDT29FCT53A/B/C
FAST CMOS OCTAL REGISTERED TRANSCEIVERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT29FCT
XXX
X
X
Package
Device
Type
Process/
Temperature
Range
Blank
B
Commercial (0°C to +70°C)
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
P
Plastic DIP
D
CERDIP
E
L
SO
CERPACK
Leadless Chip Carrier
Small Outline IC
52A
53A
52B
53B
52C
53C
Non-Inverting Octal Registered Transceiver
Inverting Octal Registered Transceiver
Fast Non-Inverting Octal Registered Transceiver
Fast Inverting Octal Registered Transceiver
Super Fast Non-Inverting Octal Registered Transceiver
Super Fast Inverting Octal Registered Transceiver
2533 drw 03
7.1
7
IDT29FCT52ADB 相关器件
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| IDT29FCT52AE | IDT | FAST CMOS OCTAL REGISTERED TRANSCEIVERS | 获取价格 |
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| IDT29FCT52ALB | IDT | FAST CMOS OCTAL REGISTERED TRANSCEIVERS | 获取价格 |
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| IDT29FCT52AP | IDT | FAST CMOS OCTAL REGISTERED TRANSCEIVERS | 获取价格 |
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| IDT29FCT52APQ | IDT | Registered Bus Transceiver, 1-Func, 8-Bit, True Output, CMOS, PDIP24 | 获取价格 |
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| IDT29FCT52ASO | IDT | FAST CMOS OCTAL REGISTERED TRANSCEIVERS | 获取价格 |
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