IDT49C3466PQF [IDT]
Error Detection And Correction Circuit, 49C Series, 64-Bit, CMOS, PQFP208, PLASTIC, QFP-208;
| 型号： | IDT49C3466PQF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Error Detection And Correction Circuit, 49C Series, 64-Bit, CMOS, PQFP208, PLASTIC, QFP-208 先进先出芯片 逻辑集成电路 |
| 文件： | 总28页 (文件大小：443K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V 64-BIT FLOW-THRU
ERROR DETECTION
IDT49C3466
AND CORRECTION UNIT
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 64-bit wide Flow-thruEDC™
The IDT49C3466 64-bit Flow-thruEDC is a high-speed
error detection and correction unit that ensures data integrity
in memorysystems. Theflow-thruarchitecture,withseparate
system and memory data buses, is ideally suited for pipelined
memory systems.
• Separate System and Memory Data Input/Output Buses
• — Error Detect Time: 20ns
— Error Correct Time: 22ns
• Corrects all single bit errors; Detects all double bit errors
and some multiple bit errors
• Configurable 16-deep bus read/write FIFOs with flags
• Simultaneouscheckbitgenerationandcorrectionofmemory
data
• Supports partial word writes on byte boundaries
• Low noise output
Implementing a modified Hamming code, the
IDT49C3466 corrects all single bit hard and soft errors, and
detects all double bit errors. The read/write FIFOs can store
up to sixteen words. FIFO full and empty flags indicate
whether additional data can be written to or read from the
EDC.
• Sophisticated error diagnostics and error logging
• Parity generation on system data bus
• VCC = 3.3V ±0.3V
Check bit generation for partial word writes on byte bound-
aries is supported on the IDT49C3466.
Diagnostic features include a check bit register, syndrome
registers, a four bit error counter which logs up to 15 errors,
andanerrordataregisterwhichstoresthecompleteerrordata
word. Parity can be generated and checked on the system
bus by the IDT49C3466.
• 208-pin Plastic Quad Flatpack
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
DIAGNOSTIC
& STATUS
REGISTERS
MD
CHK-BIT
LATCH
CHECK-BIT
COMPARATOR &
SYNDROME
GENERATOR &
ERROR
ERR
CBI0-7
MERR
MD
CHECK-BIT
GENERATOR
READ BUFFER
16 WORDS BY
64
DETECTOR
M
U
X
M
U
X
MD
LATCH
IN
ERROR
CORRECT
MD
LATCH
OUT
SD0-63
WRITE BACK PATH
MD0-63
SD
LATCH
IN
B
Y
T
E
SD
LATCH
OUT
M
U
X
WRITE
BUFFER
16 WORDS BY
72
M
U
X
SD
SD
CHK-BIT
LATCH
CHECK-BIT
GENERATOR
CBSYN0-7
PARITY
GENERATE &
PARITY CHECK
PARITY
P0-7
3268 drw 01
The IDT logo is a registered trademark and Flow-thruEDC is a trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGE
JULY 1998
©1998 Integrated Device Technology, Inc.
11.9
DSC-9038/-1
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IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
C h e c k B i t I n j e c t i o n M o d e
M U X
BYTE MUX
MUX
MUX
M U X
M U X
D E M U X
WBFF
WBEF
M U X
3268 drw 02
11.9
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IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
157
156
208
1
GND
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
SDOLE
MOE
GND
SD46
SD45
SD44
BE5
P5
SD43
SD42
SD41
SD40
SD39
SD38
SD37
SD36
BE4
GND
P4
SD35
SD34
SD33
SD32
PERR
MCLK
MDOLE
RS1
MEN
GND
RS_0
SDILE
SCLK
SOE
PQ208-2
MDILE
MD31
GND
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
GND
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
VCC
SD31
SD30
SD29
SD28
BE3
P3
SD27
SD26
SD25
SD24
SD23
SD22
SD21
SD20
BE2
P2
SD19
SD18
SD17
SD16
105
104
GND
52
53
PQFP
Top View
3268 drw 03
11.9
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IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name
SD0-63
I/O
Description
I/O
SystemDataBus:isabidirectional64-bitbusinterfacingtothesystemorCPU. WhenSystemOutput
Enable, SOE, isHIGHorByteEnable, BE0-7, isLOW, datacanbeinput. WhenSystemOutputEnable,
SOE, is LOW and Byte Enable, BE0-7, is HIGH, the SD bus output drivers are enabled.
MD0-63
I/O
Memory Data Bus: is a bidirectional 64-bit bus interfacing to the memory. During a read cycle, (MOE
HIGH) memory data is input for error detection and correction. Data is output on the Memory Data
Bus, when MOE is LOW.
CBI0-7
I
Check Bit Inputs: interface to the check bit memory.
CBSYN0-7
O
Check Bit/Syndrome Output: When MOE is LOW the generated check bits are output. When
CBSEL is HIGH and MOE is HIGH, the syndrome bits are output. The bus is tristated when MOE =
1 and CBSEL = 0.
P0-7
I/O
Parityforbytes0to7: ThesepinsareparityinputswhenthecorrespondingByteEnable(BE)isLOW
orSOEis HIGH, and are used to generate the parity error signal (PERR). These pins are outputs when
the corresponding Byte Enable (BE) is HIGH and SOE is LOW.
Control Inputs
SOE
I
I
System Output Enable: enables system data bus output drivers if the corresponding Byte Enable
(BE0-7) is HIGH.
BE0-7
Byte Enable: is used along with SOE, to enable the System Data outputs for a particular byte. For
example, if BE1 is HIGH, the System data outputs for byte 1 (SD8-15) are enabled. The BE0-7 pins also
control the byte mux. If a particular BE is HIGH during a memory read cycle, that byte is fed back to
thememorydatabus. Thisisusedduringpartialwordwriteoperationsandwritingcorrecteddataback
to memory.
MOE
I
Memory Output Enable: when LOW, enables the output buffers of the memory data bus (MD) and
CBSYN bus. It also controls the CBSYN mux. When LOW, checkbits are selected, when HIGH,
syndrome is selected.
MDILE
MDOLE
SDOLE
SDILE
I
I
I
I
I
Memory Data Input Latch Enable: on the HIGH-to-LOW transition, latches MD and CBI in MD input
latch and MD check bit latch respectively. The latches are transparent when MDILE is HIGH.
Memory Data Output Latch Enable: latches data in the MD output latch on the LOW-to-HIGH
transition of MDOLE. When MDOLE is LOW, the MD output latch is transparent.
System Data Output Latch Enable: latches data in the SD output latch and the SD checkbit latch
on the LOW-to-HIGH transition of SDOLE. The latch is transparent when SDOLE is LOW.
System Data Input Latch Enable: latches SD in the SD input latch on the HIGH-to-LOW transition.
When SDILE is HIGH, the SD input latch is transparent.
WBSEL
Write FIFO Select: when HIGH, the write FIFO is selected. When WBSEL is LOW, the SD input latch
is selected.
WBEN
I
I
WriteFIFOEnable:whenLOW,allowsSDdatatobewrittentothewriteFIFOontheSCLKrisingedge.
WBREN
Write FIFO Read Enable: when LOW, allows data to be read from the the write FIFO on MCLK rising
edge.
RS0-1
I
Reset and Select pins (read and write FIFO FIFOs)
RS1
0
0
1
1
RS0
0
1
0
1
Function
Reset 16-deep FIFO or first 8-deep FIFO
Reset second 8-deep FIFO
Select 16-deep FIFO or first 8-deep FIFO
Select second 8-deep FIFO
3268 tbl 01
11.9
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IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (Continued)
Pin Name
RBSEL
I/O
Description
I
Read FIFO Select: when HIGH, read FIFO is selected (data goes through read FIFO, not MD output
latch). When LOW, the MD output latch is selected.
RBEN
RBREN
CBSEL
MEN
I
I
I
I
Read FIFO Enable: when LOW, allows data to be written into the read FIFO on the LOW-to-HIGH
transition of the memory clock.
Read FIFO Enable: when LOW, allows data to be read from the read FIFO on the LOW-to-HIGH
transition of SCLK
Checkbit Syndrome Output Enable: Controls the CBSYN output buffer.When HIGH, the buffer is
enabled. When CBSEL is LOW, MOE controls the buffer.
Mode Enable Input: when LOW, SD0-15 is loaded into the EDC mode register on the LOW-to-HIGH
transitionoftheSCLK.ThispinmustbeheldLOWfortheentireSCLKHIGHperiod,asshowninFigure
4.
Clock Inputs
MCLK
I
I
I
Memory Clock: on the LOW-to-HIGH transition of MCLK, memory data is written to the read FIFO
when RBEN is LOW. Data is read from the write FIFO when WBREN is LOW, on the LOW-to-HIGH
transition of MCLK.
SCLK
System Clock: on the LOW-to-HIGH transition of the SCLK, data is read from the read FIFO when
RBREN is LOW. Data on the system data bus is written into the write FIFO when WBEN is LOW on
the LOW-to-HIGH transition of SCLK. Clocks data into mode register when MEN is LOW.
SYNCLK
Syndrome Clock: Used to load diagnostic registers. When an error occurs, Error Counter is
incremented on the rising SYNCLK edge (up to 15 errors). On the first error after a diagnostic reset,
SYNCLK rising edge clocks data into Check Bit, Syndrome, Error Type and Error Data registers. One
of the syndrome registers has new data clocked in on every SYNCLK rising edge.
Status Outputs
WBEF
O
Write FIFO Empty Flag: when LOW, indicates that the write FIFO is empty. After a reset, the WBEF
goes LOW.
WBFF
RBEF
O
O
WriteFIFOFullFlag:whenLOW, indicatesthatthewriteFIFOisfull. Afterareset,WBFFgoesHIGH.
Read FIFO Empty Flag: when LOW, indicates that the read FIFO is empty. After a reset, the RBEF
goes LOW.
RBHF
O
Read FIFO Half-full Flag: when LOW, indicates that there are eight or more data words (in the 16-
deepconfiguration)orfourormoredatawords(inthedual8-deepconfiguration)inthereadFIFO. The
flag will return HIGH when less than eight (or four) data words are in the FIFO.
RBFF
ERR
O
O
O
Read FIFO Full Flag: when LOW, indicates that the read FIFO is full. After a reset, RBFFgoes HIGH.
Error Flag: when ERR is LOW, a data error is indicated. The ERR is not latched internally.
MERR
Multiple Error Flag: when MERRis LOW, a multiple data error is indicated. The MERRis not latched
internally.
PERR
O
Parity Error Flag: when LOW, indicates a parity error on the system data bus input.
Power Supply
VCC
P
P
Power Supply Voltage.
GND
Ground.
3268 tbl 02
11.9
5
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
DETAILED DESCRIPTION —
(1, 2)
64-BIT MODIFIED HAMMING CODE - CHECKBIT ENCODING CHART
Generated
Participating Data Bits
Checkbits
CB0
Parity
0
1
X
X
2
X
X
3
4
5
6
7
8
X
X
9
10
11
12
X
13
14
15
Even (XOR)
Even (XOR)
Odd (XNOR)
Odd (XNOR)
Even (XOR)
Even (XOR)
Even (XOR)
Even (XOR)
X
X
X
X
X
CB1
X
X
X
X
X
X
X
X
CB2
X
X
X
X
X
X
X
X
X
X
CB3
X
X
X
X
X
X
X
X
CB4
X
X
X
X
X
X
CB5
X
X
X
X
CB6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CB7
3268 tbl 03
Generated
Checkbits
CB0
Participating Data Bits
Parity
16
17
X
18
X
19
20
21
22
23
24
X
25
26
27
28
X
29
30
31
Even (XOR)
Even (XOR)
Odd (XNOR)
Odd (XNOR)
Even (XOR)
Even (XOR)
Even (XOR)
Even (XOR)
X
X
X
X
X
CB1
X
X
X
X
X
X
X
X
X
X
X
CB2
X
X
X
X
X
X
X
X
X
CB3
X
X
X
X
X
X
X
CB4
X
X
X
X
X
X
X
X
X
CB5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CB6
CB7
X
3268 tbl 04
Generated
Checkbits
CB0
Participating Data Bits
Parity
32
X
33
X
34
35
36
X
37
38
X
39
40
41
42
X
43
44
X
45
46
47
Even (XOR)
Even (XOR)
Odd (XNOR)
Odd (XNOR)
Even (XOR)
Even (XOR)
Even (XOR)
Even (XOR)
X
X
X
CB1
X
X
X
X
X
X
X
CB2
X
X
X
X
X
X
X
X
X
X
X
X
X
CB3
X
X
X
X
X
X
X
X
X
X
X
X
CB4
X
X
X
X
X
X
X
X
CB5
X
X
X
X
X
X
X
X
CB6
X
X
X
X
X
CB7
X
X
3268 tbl 05
Generated
Checkbits
CB0
Participating Data Bits
Parity
48
X
49
X
50
51
52
X
53
54
X
55
56
57
58
X
59
60
X
61
62
63
Even (XOR)
Even (XOR)
Odd (XNOR)
Odd (XNOR)
Even (XOR)
Even (XOR)
Even (XOR)
Even (XOR)
X
X
X
CB1
X
X
X
X
X
X
X
CB2
X
X
X
X
X
X
X
X
X
X
X
X
CB3
X
X
X
X
X
X
X
X
CB4
X
X
X
X
X
X
X
X
CB5
X
X
X
X
X
X
X
X
X
X
X
X
CB6
CB7
X
X
X
X
X
X
X
X
NOTES:
3268 tbl 06
1. The table indicates the data bits participating in the checkbit generation. For example, checkbit CB0 is the Exclusive-OR function of the 64 data input bits
marked with an X.
2. The checkbit is generated as either an XOR or an XNOR of the 64 data bits noted by an “X” in the table.
11.9
6
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
DETAILED DESCRIPTION —
(1)
64-BIT SYNDROME DECODE TO BIT-IN-ERROR
HEX
S7
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
A
1
0
1
0
B
1
0
1
1
C
1
1
0
0
D
1
1
0
1
E
1
1
1
0
F
1
1
1
1
S6
Syndrome
Bits
S5
S4
HEX S3 S2 S1 S0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
C0
C1
T
C4 C5
T
C6
T
T
M
34
T
T
M
56
T
62 C7
T
M
50
T
T
M
40
T
46
T
T
M
M
T
M
T
T
2
M
T
T
30
M
T
1
T
T
T
T
14
M
T
T
T
T
T
2
T
T
T
3
18
T
8
M
T
M
T
M
T
M
T
24
T
4
C2
T
T
15
T
35
T
57
T
51
T
41
T
M
T
T
3
31
T
5
19
20
T
9
M
M
T
63
M
T
M
M
T
47
M
T
25
26
T
6
T
10
T
T
T
T
T
T
T
4
T
7
M
C3
T
M
M
T
36
37
T
58
59
T
52
53
T
42
43
T
M
M
T
T
T
5
M
M
T
8
T
T
T
T
T
T
T
9
21
22
T
11
12
T
M
33
T
M
M
T
M
49
T
M
M
T
27
28
T
A
T
T
T
T
T
T
T
6
T
B
17
T
M
T
38
T
60
T
54
T
44
T
1
T
7
M
T
C
23
T
13
T
M
T
M
T
M
T
M
T
T
29
T
D
M
16
T
M
M
T
39
M
T
61
M
T
55
M
T
45
M
T
M
0
T
T
M
M
M
E
F
T
T
T
T
T
T
T
M
M
32
M
48
M
T
M
T
NOTES:
3268 tbl 07
1. Thetableindicatesthedecodingoftheeightsyndromebitstoidentifythebit-in-errorforasingle-biterror,orwhetheradoubleortriple-biterrorwasdetected.
The all-zero case indicates no error detected.
* = No errors detected
# = The number of the single data bit-in-error
T = Two errors detected
M = Three or more detected
C# = The number of the single checkbits in error
partial word write or byte merge is discussed later. Here it is
IDT49C3466 OPERATION
assumed that all 64 bits are being written. Consequently,
The EDC is involved in two types of operation — memory
BE0-7 must all be LOW.
reads and memory writes. With the IDT49C3466, both these
The data is fed to the SD Checkbit generator where
can be accomplished by utilizing either of two possible data
appropriate checkbits are generated. Both system data and
paths — one incorporating the FIFO and the other without the
thegenerated checkbitscanbe latchedbypullingthe SDOLE
FIFO. These operations are treated separately below.
signal HIGH. Asserting MOE enables the MD output buffer
Memory Write
and data is output to the Memory Data (MD) bus. CBSEL (=1)
or MOE(=0) need to be asserted to enable the CBSYN output
buffer and output checkbits on CBSYN0-7.
The involvement of the EDC in this type of operation is
relatively minimalsince itdoesnot callfor anyerrorchecking.
It only generates the check bits associated with each 64-bit
wide data word. The EDC can be in generate-detect or normal
mode for this operation.
When a write operation is performed, it must be ensured
that the SD output buffer (enabled by SOE and BE0-7) is
disabledsothatnoattemptismadetosimultaneouslytransfer
read data onto the System Data (SD) Bus.
When the write FIFO is selected (WBSEL = 1), instead of
asserting SDILE, WBEN is asserted and data is clocked into
the write FIFO on the rising edge of SCLK. WBFFis asserted
when the WFIFO is full and this inhibits further write attempts
(see section on "Clock Skew" and "R/W FIFO Operation at
Boundaries") to the WFIFO. When WBREN is asserted, data
can be clocked out of the write FIFO on the rising edge of
MCLK. WBEFis asserted when the WFIFO is empty and this
inhibits further read attempts (see section on "Clock Skew")
from the WFIFO.
When the write FIFO (WFIFO) is bypassed (WBSEL
LOW), datapassesthroughtheSDLatchIn. Tolatchdata, the
SDILE signal should be pulled LOW. The special case of a
11.9
7
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
BEn = 0 => Path A
BEn = 1 => Path B
MD
LATCH
OUT
MD BUS
64
PATH B
64
SD
BYTE
MUX
64
LATCH OUT
PATH A
SD
LATCH IN
64
M
U
X
64
64
64
WRITE BUFFER
WBSEL
BE0-7
M
U
X
8
3268 drw 04
Figure 1. Byte Merge
Memory Read
Clock Skew
A skew between the read and write clocks, as specified by
During a memory read, data and the corresponding input
checkbits are read from the MD bus and CBI0-7, respectively. tskew, is recommended. This specification is not a stringent
The memory and checkbit data may both be latched as they one, in the manner of setup and hold times, but is important in
come in (MD Latch In and MD Checkbit latch) by the MDILE preempting latencies at FIFO boundaries. For example –
signal. Memory data is sent to the MD checkbit generator When a word is written to an empty FIFO, there is a finite delay
(where checkbits corresponding to the input data are gener- before the FIFO is recognized as no longer being empty and
ated)andtotheerrorcorrectcircuitry.Thegeneratedcheckbits hence allowing a read from the same FIFO. Similarly when a
are X-ORed with the input checkbits to produce the syndrome wordisreadfromafullFIFO,thereisadelaybeforeawrite can
word. This is sent to the error correction circuitry which successfully be attempted. The tskew specification accounts
generates the corrected data (normal mode). The corrected for these cases. During cycles other than on full/empty FIFO
data is output to the SD bus via either of two data paths. When boundaries, the clock skew is not required and the device
RBSEL is LOW, data flows through MD Latch Out. Pulling functions correctly even when the reads and writes occur
MDOLE HIGH latches this data. The output buffer is enabled simultaneously. IfthetskewspecificationisignoredandSCLK
by asserting SOE(=0) and BE0-7 (=1). Corrected data can be and MCLK were permanently tied together, there is an extra
written back to memory by enabling the MD output buffer. In cycle latency in the cases mentioned above. Clock skew
order to ensure selection of the write back path (Path B in violation is illustrated in Figure 13.
figure 1) at the byte mux, BEO-7 should be all 1's while
WBSEL = 0. If WBSEL = 1, buffered BEO-7 from the output FIFO Write Latency
of the write FIFO controls the byte mux.
The first data written to either of the (read or write) FIFOs,
If the read FIFO (RFIFO) is selected (RBSEL HIGH), data after the FIFO is reset, suffers a single clock latency. Data that
is clocked into the FIFO (Read_FIFO Write) when RBEN is is set-up with respect to the first clock is ignored and the data
LOW, on the rising edge of MCLK. RBFFis asserted when the that is set-up with respect to the second clock edge after the
RFIFO is full and this inhibits further write attempts to the reset, is stored as the first data in the FIFO (Refer to Figures
RFIFO (see section on "Clock Skew" and "R/W FIFO opera- 9and10).Theempty-flagisdeassertedafterthissecondclock
tion at Boundaries"). Data is clocked out of the FIFO edge and 15 more data words (in a 16 deep configuration) can
(Read_FIFO Read) when RBREN is LOW on the rising edge be written to the FIFO after this.
of SCLK. RBEFis asserted when the RFIFO is empty and this
inhibits further read attempts (see section on "Clock Skew") "dummy" or "set-up" clock edge before the actual write to the
from the RFIFO. FIFO. The dummy write clock can be provided any time after
Note: In case of multiple error SD should be ignored in correct reset and before the next buffer write operation takes place.
The latency can be reduced or eliminated by providing a
mode.
The latency described here (shown in Figures 10 and 13)
occurs only after a FIFO reset. In other cases where the FIFO
becomes empty there is no latency.
11.9
8
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
R/W FIFO Operation At Boundaries
overwritten and the FIFO output changes from AA to the data
just written, namely QQ.
In the 49C3466 the write pointer is incremented on every
FIFO write. Similarly the read pointer is incremented on every
FIFO read. In most cases on a FIFO read, the last data read
remains at the output of the FIFO, until the read pointer is
further incremented. On the last (the write that fills the FIFO)
FIFO write after the FIFO read, however, this last read data is
overwrittenbythe16thwritefollowingtheemptyconditionand
consequently the data at the FIFO output is liable to change.
The situation is depicted in the diagram below.
This operation needs to be taken into account in the design
of the system. In case of a burst operation where FIFO data
is output at a much slower rate than the rate at which data is
input and the full flag is expected to inhibit further writes, the
user cannot expect the FIFO output to remain static through
the 16th write of the burst. If this is a requisite to the design,
the FIFO output should be latched. In the case of the write
FIFO this can be accomplished on-chip by latching the FIFO
WP
FIFO
(empty)
reset
RP
WP
WRITE1
(data = AA)
FIFO
RP
WP
READ1
(data = AA)
FIFO
(empty)
RP
WP
No READs
(data = AA)
WRITE1
(data = BB)
FIFO
RP
WP
WRITE2
(data =CC)
No READs
(data = AA)
FIFO
RP
WP
WRITE15
(data = PP)
No READs
(data = AA)
FIFO
RP
WP
WRITE16
(data = QQ)
FIFO
(full)
No READs
(data = QQ)
Figure 2. R/W FIFO Operation
The diagram in figure 2 progresses from the FIFO output in the SD output latch. For the read FIFO, the FIFO
initialization(reset) through a sequence of write operations. output must be latched externally to accomplish the same
After the first write, a read is executed which establishes the thing, since there is no latch on-chip following the FIFO. If this
data at the FIFO output(AA). On the last write to the FIFO(the cannotbedoneandthesituationdescribedaboveisexpected
write that fills the FIFO), the location of the last read data is to occur in normal operation, the write must be inhibited one
cycle before the FIFO becomes full.
11.9
9
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
Partial Word Write/Byte Merge
MODE REGISTER CONFIGURATION
Writing a word shorter than 64 bits to memory is treated
as a special case. The checkbits generated for a data word
shorter than 64 bits and written to a particular memory location
differ from the checkbits that would be generated by the entire
64-bit data word at the same location. Hence, the byte merge
operation requires reading of the contents of the memory
location to be written to, merging the byte/bytes being written
(from SD side) with the other component bytes previously at
that memory location (from MD side), generating a checkbit
word for this composite word and writing both the composite
data word and the generated checkbits to memory. The BEn
bits supplied by the user determine the bytes that come from
SD and those that come from MD, as illustrated in Figure 1.
15
7
6
5
4
3
2
0
UNUSED RMODE PSEL
RWBD
CLEAR EDCM0-2
EDCM2 EDCM1 EDCM0
OPERATION
ERROR-DATA OUTPUT MODE
DIAGNOSTIC-OUTPUT MODE
GENERATE-DETECT MODE
NORMAL MODE
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
CHECKBIT-INJECTION MODE
RMODE
OPERATION
0
NOP
1
READ MODE REGISTER ON SD BUS
RWBD
OPERATION
EDC Modes
0
1
DUAL FIFOS (8)
SINGLE FIFO (16)
The IDT49C3466 has 5 modes of operation. Refer to table
below for a description of the modes.
The Error Data Output mode is useful for memory initial-
ization as described below. In Checkbit Injection mode, the
MD Checkbit Latch is loaded with data from the System Bus.
This serves to verify the functioning of the EDC. Any discrep-
ancy between the injected checkbits and generated checkbits
should result in assertion of the ERR, MERR signals.
These modes and certain other features such as clear,
buffer configuration, etc., can be selected by appropriately
loading the Mode Register. The Mode Register can be written
to by asserting MEN. Then SD0-15 is clocked into the mode
register on the rising edge of SCLK.
CLEAR
OPERATION
NOP
CLEAR ALL DIAGNOSTIC REGISTERS
0
1
PSEL
OPERATION
EVEN PARITY
ODD PARITY
0
1
3268drw 05
OPERATING MODE DESCRIPTION
Mode
Description
MODE 0
Error-Data Output Mode: This mode allows the uncorrected data captured from an error event by the Error-Data
Register to be read by the system for diagnostic purposes. The Error-Data Register is cleared by setting the mode
register "'clear"-bit.
MODE 1
Diagnostic-Output Mode: In this mode, contents of latch and five internal registers are read by the system for
diagnostic and error logging purposes. Internal data paths allow output from the CBI LATCH to be read directly by the
system bus for diagnostic purposes. The contents of the internal diagnostic checkbit register, syndrome registers, error
count register and error-type register are also output on the SD bus.
MODE 2
MODE 3
MODE 4
Generate-Detect Mode: (Detect-Only) The EDC performs checkbit generation during a memory write, and performs
error detection only during a memory read.
Normal Mode: The EDC performs checkbit generation during memory writes and error detection and correction during
memory reads.
Checkbit-Injection Mode: In this mode, the checkbit latch is loaded with desired 8-bit data from the SD bus.This eight
bit data passes through SD Latch in or write FIFO to the MD check bit latch. By inserting various checkbit values,
correct functioning of the EDC can be verified “on-board”. The rest of the operation is similar to regular memory
reads. The EDC compares the injected checkbits against the internally generated checkbits. Any discrepancy in the
injected checkbits and the internally generated checkbits will cause the ERR / MERR to go LOW.
3268 tbl 08
Memory Initialization
Memory initialization involves clearing all memory data locations and writing the corresponding checkbits (checkbits
corresponding to all zero data = $0C) to checkbit memory. This can be done using the 49C3466 to first create an "all-zero-
data" source. This is done by setting the CLEAR bit in the mode register. This clears all diagnostic registers. Then this data
can be written back to memory in the Error-Data output (Mode 0) mode. In order to wrap the all-zero data back to the MD bus,
BE0-7 should be high and WBSEL =0.
11.9
10
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
CLEAR
MODE BIT 0
Diag. Regs.
Error Data Regs.
SYNCLK
64
BE0-7
WFIFO
BE0-7
WBSEL
Fig 3. Memory Initialization using Diagnostic Output/Error Data Output Mode
DIAGNOSTIC OUTPUT DATA FORMAT
TO SD BUS
10
6 5
4
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
9
8
7
3 2 1 0
37 36 35 34 33 32 31
Error
Checkbit
(from checkbit latch)
Error
Count
Syndrome
(on 1st error)
Checkbit
(on 1st error only)
Syndrome
(on every error)
Type
(on
1st
error
only)
* Bit #28 = 1 If "Error" condition
FROM DIAGNOSTIC REGISTERS
Bit #29 = 1 If "Multiple bit Error" condition
3268 drw 06
Diagnostics
The diagnostic ability of the IDT49C3466 rests on a set of
6 registers that provide error logging information. These
include the checkbit register, error count register, error type
register, 2 syndrome registers and the error data register.
Data is clocked into each of these registers by SYNCLK. The
error data register, checkbit register, error type register and
one of the syndrome registers are reloaded only in the case of
the first error after a clear. The other syndrome register and
the error count register are reloaded on every error condition
SYNCLK edge. The contents of the Error Data register can be
readonlyinErrorDataOutputmode.Thecontentsoftheother
diagnostic registers as well as the checkbit latch can be read
in Diagnostic Output mode.
CONDITION
OUTPUT
LOADED
BY
DIAG.
REGISTER
CHECKBIT
SYNCLK ↑
SYNCLK ↑
ONLY ON 1st
ERROR
SD8-15
SYNDROME
(On 1st ERR)
ONLY ON 1st
ERROR
SD16-23
ERR CNT
SYNCLK ↑
ON EVERY
ERROR (Up to
15 ERRORS)
SD24-27
ERR TYPE
SYNCLK ↑
SYNCLK ↑
ONLY ON 1st
ERROR
SD28-29
SD30-37
Parity
The IDT49C3466 provides a parity check and generation
facility. On a memory read the EDC generates parity bits for
each data byte and outputs the parity byte on the parity bus,
P0-7. During a memory write, parity is checked by comparing
the parity bits input on P0-7 and the parity bits generated from
theinputdataword. Adiscrepancybetweenthesetwocauses
thePERRflagtobeasserted. Inthecaseofpartialwordwrites,
the PERR flag is based on the parity bits Px and data bytes
input on SD bus.
SYNDROME
(On every
ERROR)
ON EVERY
ERROR
11.9
11
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0 MHz)
Symbol
Parameter(1)
Input
Conditions
Typ. Unit
Symbol
Rating
Commercial
Unit
(2)
(3)
(4)
CIN
VIN = 0V
5
pF
V
V
V
TERM
TERM
TERM
Terminal Voltage with
Respect to GND
–0.5 to +4.6
V
Capacitance
Output
Terminal Voltage with
Respect to GND
–0.5 to +4.6
V
V
COUT
VOUT = 0V
7
pF
Capacitance
Terminal Voltage with
Respect to GND
–0.5 to
NOTE:
1. This parameter is sampled and not 100% tested.
3268 tbl 10
V
CC + 0.5
T
STG
Storage Temperature
DC Output Current
–65 to +150
30
°C
I
OUT
mA
3268 tbl 09
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGSmaycausepermanentdamagetothedevice. Thisisastressrating
only and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
11.9
12
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
The following conditions apply unless otherwise specified:
Commercial: TA = 0°C to +70°C, VCC = 3.3V ±0.3V
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max. Unit
VIH
Input HIGH Level (Input pins)
Guaranteed Logic HIGH Level
2.0
—
3.6
VCC+0.5
0.8
V
Input HIGH Level (I/O pins)
Input LOW Level
2.0
—
—
VIL
Guaranteed Logic LOW Level
–0.5
V
(Input and I/O pins)
IIH
Input HIGH Current
VCC = Max.
VCC = Max.
VI = VCC
—
—
—
—
—
—
—
—
—
±1
±1
±1
±1
IIL
Input LOW Current
VI = GND
VO = VCC
VO = GND
IOZH
IOZL
IOS
High Impedance Output Current
(3-State Output pins)
Short Circuit Current(4)
µA
VCC = Max.(3)
VOUT = 0V
mA
V
VOH
VOL
VH
Output HIGH Voltage
VCC = Min.
VIN = VIH or VIL
VCC = Min.
IOH = –1mA
IOL = 4mA
2.4(5)
—
3.0
0.3
100
—
0.5
—
Output LOW Voltage
V
VIN = VIH or VIL
Input Hysteresis on input control lines
—
mV
3268 tbl 11
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC –0.6V at rated current.
POWER SUPPLY CHARACTERISTICS
The following conditions apply unless otherwise specified:
Commercial: TA = 0°C to +70°C, VCC = 3.3V ±0.3V
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
ICCQC
Quiescent Power Supply Current VIN = VCC, or VIN = GND
VCC = Max.
—
—
—
3.0
1.5
—
15
100
—
mA
ICCQT
ICCD
Quiescent Power Supply Current
TTL Input Levels
VIN = VCC –0.6
VCC = Max.
µA/
Input
Dynamic Power Supply Current
VIN = VCC, or VIN = GND
mA
VCC = Max. f = 10MHz Correct Mode
NOTES:
3268 tbl 12
1. For conditions shown as Min. or Max., use appropriate Vcc value.
2. Typical values are at VCC = 3.3V, +25°C ambient temperature.
11.9
13
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
AC PARAMETERS
PROPAGATION DELAY TIMES
Description
To Output
Number
Parameter
From Input(1)
Max.
Unit
GENERATE (WRITE) PARAMETERS
Without Write FIFO:
1
tBC
BEn
BEn
Pxin
SDin
SDin
SDin
CBSYN (chkbit)
MDOUT
20
16
10
22
22
16
ns
ns
ns
ns
ns
ns
2
tBM
tPPE
tSC
3
PERR
4
CBSYN (chkbit)
MDout
5
tSM
tSPE
6
PERR
With Write FIFO:
7
8
9
tMC
MCLK (Lo-Hi)
MCLK (Lo-Hi)
WBSEL
CBSYN (chkbit)
MDout
25
25
18
ns
ns
ns
tMMD
tWBSEL
MDout
DETECT (READ) PARAMETERS
Without Read FIFO:
10
tWYC
tME
SYNCLK (Lo-Hi)
CBSYN (syndr)
ERR
16
20
22
13
13
ns
ns
ns
ns
ns
11
MDin
MDin
CBI
12
tMME
tCE
MERR
13
ERR
14
tCME
CBI
MERR
With Read FIFO:
15
16
tSSD
SCLK (Lo-Hi)
RBSEL
SDout
SDout
22
18
ns
ns
tRBSEL
CORRECT (READ) PARAMETERS
Without Read FIFO:
17
tCS
tMP
tMS
CBI
SDout
Pxout
SDout
20
22
22
ns
ns
ns
18
MDin
MDin
19
With Read FIFO:
20
tSP
SCLK (Lo-Hi)
Pxout
22
ns
3268 tbl 13
NOTE:
*
PRELIMINARY.
1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa.
11.9
14
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
PROPAGATION DELAY TIMES
FROM LATCH ENABLES
Description
Number
21
Parameter
tMLE
From Input(1)
MDILE (Lo-Hi)
MDILE (Lo-Hi)
MDILE (Lo-Hi)
MDILE (Lo-Hi)
MDOLE (Hi-Lo)
MDOLE (Hi-Lo)
SDILE (Lo-Hi)
SDILE (Lo-Hi)
SDOLE (Hi-Lo)
SDOLE (Hi-Lo)
To Output
ERR
Max.
16
18
24
22
18
18
20
20
12
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
22
tMLME
tMLP
MERR
23
Px (Detect Mode)
SDout (Detect Mode)
SDout
24
tMLS
25
tMOLS
tMOLP
tSLC
26
Px
27
CBSYN (chkbit)
MDout
28
tSLM
29
tSOLC
tSOLM
CBSYN (chkbit)
MDout
30
3268 tbl 14
NOTE:
PRELIMINARY.
•
1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa.
R/W FIFO TIMES
Description
To Output
Number
Parameter
From Input(1)
RS1 (Hi-Lo)
Min.
Max.
Unit
31
tRSF
EF (Hi-Lo)/FF (Lo-Hi)
—
16
ns
during SCLK LOW
32
33
34
35
39
tSKEW1
tSKEW2
tEF
RCLK (Lo-Hi)
(SCLK or MCLK)
WCLK (Lo-Hi)
(SCLK or MCLK)
10
10
—
—
—
—
—
15
15
15
ns
ns
ns
ns
ns
WCLK (Lo-Hi)
(SCLK or MCLK)
RCLK (Lo-Hi)
(SCLK or MCLK)
R/WCLK (Lo-Hi)
(SCLK or MCLK)
EF
FF
HF
tFF
R/WCLK (Lo-Hi)
(SCLK or MCLK)
tHFF
R/WCLK (Lo-Hi)
(SCLK or MCLK)
3268 tbl 15
NOTE:
•
PRELIMINARY.
1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa.
11.9
15
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
BYTE MERGE TIMES
Description
Number
36
Parameter
tSCM
From Input(1)
SCLK (Lo-Hi)
MDOLE (Hi-Lo)
RBSEL
To Output
MDout
Max.
25
Unit
ns
37
tMDM
MDout
18
ns
38
tRBM
MDout
23
ns
3268 tbl 16
NOTE:
PRELIMINARY.
*
1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa.
ENABLE AND DISABLE TIMES
Description
To Output
Number
40
Parameter
tBESZx
tBESxZ
tBEPZx
tBEPxZ
tSEPZx
tSEPxZ
tCECZx
tCECxZ
tMEMZx
tMEMxZ
tSESZx
tSESxZ
From Input(1)
BEN = High
Low
Min.
—
—
—
—
—
—
—
—
—
—
—
—
Max.
22
22
15
15
14
14
12
10
22
18
16
20
Unit
SDout
*
ns
41
Hi-Z
*
42
BEN = High
Low
Pout
ns
ns
ns
ns
ns
43
Hi-Z
*
44
SOE = Low
High
Pout
45
Hi-Z
*
46
MOE = Low
High
CBSYN
MDout
SDout
47
Hi-Z
*
48
MOE = Low
High
49
Hi-Z
*
50
SOE = Low
High
51
Hi-Z
NOTES:
3268 tbl 17
*
PRELIMINARY.
1. (High-Z) indicates high impedence.
2. * indicates delay to both edges.
11.9
16
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
SET-UP AND HOLD TIMES
Description
Number
52
Parameter
tCMLS
From Input(1)
CBI Set-up
CBI Hold
To Output
Min.
2
Unit
ns
ns
ns
ns
1ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
before MDILE =
after MDILE =
before MDILE =
after MDILE =
before MDOLE =
after MDOLE =
before MDOLE =
before MDOLE =
after MDOLE =
after MDOLE =
before MCLK =
after MCLK =
Hi-Lo
Hi-Lo
Hi-Lo
Hi-Lo
Lo-Hi
Lo-Hi
Lo-Hi
Lo-Hi
Lo-Hi
Lo-Hi
Lo-Hi
Lo-Hi
Hi-Lo
Hi-Lo
Lo-Hi
Lo-Hi
Lo-Hi
Lo-Hi
Lo-Hi
Lo-Hi
Lo-Hi
Lo-Hi
Lo-Hi
Lo-Hi
Lo-Hi
Lo-Hi
Lo-Hi
53
tCMLH
tMMLS
tMMLH
tCMOLS
tCMOLH
tMMOLS
tMMOLS
tMMOLH
tMMOLH
tMMCS
tMMCH
tSSLS
6
54
MDIN Set-up
MDIN Hold
2
55
6
56
CBI Set-up (Correct)
CBI Hold (Correct)
MDIN Set-up (Detect)
MDIN Set-up (Correct)
MDIN Hold (Detect)
MDIN Hold (Correct)
MDIN Set-up
10
2
57
58a
58b
59a
59b
60
10
10
4
4
10
4
61
MDIN Hold
62
SDIN Set-up
before SDILE =
after SDILE =
before SCLK
5
63
tSSLH
SDIN Hold
3
64
tSSCS
SDIN Set-up
2
65
tSSCH
SDIN Hold
after SCLK
6
66
tSSOLS
tSSOLH
tSCSD
SDIN Set-up
before SDOLE =
after SDOLE =
before SDOLE =
before SDOLE =
before S/M CLK =
after S/M CLK =
R/WCLK =
8
67
SDIN Hold
0
68
SCLK (Lo-Hi)
14
14
4
69
tMCSD
tENS
MCLK (Lo-Hi)
70
R/W FIFO Enable Set-up
R/W FIFO Enable Hold
RS1 (Lo-Hi)
71
tENH
4
72
tRSS
6
73
tMODS
tMODH
tMENS
tMENH
Mode Data Set-up
Mode Data Hold
Mode Enable Set-up
Mode Enable Hold
before SCLK =
after SCLK =
4
74
4
75
before SCLK =
after SCLK =
4
76
4
77
78
tMSDS
tMSDH
MDIN Set-Up
MDIN Hold
before SDOLE =
after SDOLE =
Lo-Hi
Lo-Hi
22
0
ns
ns
93
94
tBSCS
tBSCH
BE Set-up
BE Hold
before SCLK =
after SCLK =
Lo-Hi
Lo-Hi
1
6
ns
ns
DIAGNOSTIC SET-UP AND HOLD TIMES
79
80
tCSCS
tMSCS
tMLSCS
tCSCH
tMSCH
tMLSCH
CBI Set-up
4
10
10
6
ns
ns
ns
ns
ns
ns
MDIN Set-up
before SYNCLK =
After SYNCLK=
Lo-Hi
Lo-Hi
81
MDILE = Lo-Hi Set-up
CBI Hold
82
83
MDIN Hold
6
84
MDILE = Lo-Hi Hold
6
3268 tbl 18
NOTE:
*
PRELIMINARY.
1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa.
11.9
17
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
MINIMUM PULSE WIDTH
Description
Number
86
Parameter
tRS
From Input(1)
Condition
Min.
6
Unit
ns
Min. RS1 LOW time
to reset buffers
—
87
tMLE
Min. MDILE HIGH time
Min. MDOLE LOW time
Min. SDILE HIGH time
Min. S/MCLK HIGH time
Min. SYNCLK HIGH time
Min. SDOLE LOW time
to strobe new data
to strobe new data
to strobe new data
to clock in new data
to clock in new data
to clock in new data
MD, CBI = Valid
6
ns
88
tMDOLE
tSLE
—
SD = Valid
EN signal LOW
—
6
ns
89
6
ns
90
tCLK
6
ns
91
tSYNCLK
tSDOLE
6
ns
92
—
6
ns
3268 tbl 19
NOTE:
*
PRELIMINARY.
11.9
18
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
AC Test Conditions
Input Pulse Levels
GND to 3.0V
1V/ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
See Figure 15
2617 tbl 21
SD0-15
SDin (Mode)
t
MODH
t
MODS
SCLK
t
MENH
t
MENS
MEN
3268 drw 07
Figure 4. Mode Enable Timing
WBSEL
SOE
write
SCLK
(WCLK)
tSSCS
tSSCH
SD0-63
SDin
tENH
tENS
WBEN
t
FF
t
FF
WBFF
tSKEW1
read
MCLK
(RCLK)
3268 drw 08
WBREN
Figure 5. WFIFO Write Timing (Write Cycle)
11.9
19
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
read
MCLK
(RCLK)
tENH
tENS
______
WBREN
tEF
tEF
_____
WBEF
WBSEL
tMCSD
______
SDOLE
t MEMxZ
____
MOE
tMMD
t MEMZx
MDout D1
MD0-63
tCECZx
tMC
Valid Checkbits out
CBSYN0-7
tSKEW2
write
SCLK
(WCLK)
3268 drw 09
Figure 6. WFIFO Read and Checkbit Generate Timing (Write Cycle)
11.9
20
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
RBSEL
____
MOE
tMEMxZ
MD0-63
CBI0-7
MDin
MDout
t MMLH
t MMLS
Checkbits in
tCMLS
tCMLH
MDILE
tMMCS
t MMCH
write
MCLK
(WCLK)
tENH
tENS
_____
RBEN
tFF
_____
RBFF
tSKEW1
SCLK
(RCLK)
read
3268 drw 10
Figure 7. RFIFO Write Timing (Read Cycle)
11.9
21
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
read
SCLK
(RCLK)
tENH
tENS
______
RBREN
tEF
_____
RBEF
tEF
write
MCLK
(WCLK)
tSKEW2
RBSEL
tSSD
____
SOE
tSESZx
BE0-7
SD0-6
tBESZx
SDout (corrected data)
tSEPZx
tBEPZx
P0-7
Parity out
3268 drw 11
Figure 8. RFIFO Read Timing (Read Cycle)
11.9
22
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
RS1
t RS
tRSS
WCLK
(SCLK / MCLK)
t RSF
dummy write
__
EF
tRSF
__
FF
3268 drw 12
Figure 9. FIFO (WFIFO/RFIFO) Reset Timing
DATA
(SD/MD)
dataxx
data1
tSSCS
tSSCH
dummy write
write
WCLK
(SCLK/MCLK)
tENS
BUFFER ENABLE
_____ _____
(WBEN/ RBEN)
tRSF
FIFO RESET
(RS1)
tEF
BUFFER
EMPTY FLAG
_____ ____
(WBEF/ RBEF)
3268 drw 13
Figure 10. FIFO (WFIFO/RFIFO) Write Latency Timing
11.9
23
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
Valid BE0-7
BE0-7
SOE
SDin Dy
SD0-63
t
SSCS
t
SSCH
SDILE
SDOLE
external tristate
MDin Dx
MDout Dxy
MD0-63
t
MEMXZ
t
MEMZX
MOE
t
MMOEmin
1
t
MDILE
t
MMOLS
MMOLH
MDOLE
RBSEL
WBSEL
3268 drw 14
Figure 11. Partial Word Write/Byte Merge Timing
NOTE:
1. tMMOE is not a propagation delay. For partial word write operations tMMOE MIN= tMDM.
11.9
24
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
tBM
Valid BE0-7
BE0-7
tSESXZ
SOE
SD
Data xx
tSSCS
tSSCH
read
data
dummy
write
write
data
SCLK
MCLK
tENS
tENH
WBEN
tENS
tENH
WBREN
tCSM = tMMD
WBSEL
MD
tMMCS
tMMCH
Data yy
Merged Data xx+yy
RBEN
tENH
tENS
tENS
tENH
RBREN
RBSEL
tMEMXZ
MOE
3268 drw 15
Figure 12. Partial Word Write/Byte Merge Timing using both RFIFO and WFIFO
11.9
25
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
invalid data
SD0-63
SDin 1
SDin 2
dummy write
t SSCS
tSSCH
SCLK
(WCLK)
1
2
tRSS
RS1
tRSF
tEF
_____
WBEF
MCLK
(RCLK)
1
ignored
(no skew)
_____
WBREN
3268 drw 16
Figure 13. Write FIFO Write Timing with Clock Skew Violation
tMSCH
MD0-63
CB0-7
MDin
tMSCS
tCSCH
CBin
tCSCS
MDILE
tMLSCH
tMLSCS
SYNCLK
tSYNCLK
3268 drw 17
Figure 14. Diagnostic Timing
11.9
26
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
6V
←
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
V
CC
Open
GND
6V
500Ω
500Ω
V OUT
GND
V
IN
Pulse
Generator
D.U.T.
Open
2617 tbl 20
50pF
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
R
T
C
L
3268 drw 18
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
INPUT
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
t
H
tSU
1.5V
1.5V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
t
REM
PRESET
3V
1.5V
0V
CLEAR
HIGH-LOW-HIGH
PULSE
ETC.
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
CLEAR
tSU
t
H
CLOCK ENABLE
ETC.
3268 drw 20
3268 drw 19
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
t
PLH
t
t
PHL
PHL
t
PZL
tPLZ
V
OH
OUTPUT
3V
1.5V
3V
1.5V
OUTPUT
NORMALLY
LOW
SWITCH
6V
V
OL
t
PLH
0.3V
0.3V
V
OL
3V
1.5V
0V
t
PZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
V
OH
OUTPUT
NORMALLY
HIGH
SWITCH
GND
1.5V
0V
0V
3268 drw 21
3268 drw 22
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
3. If VCC is below 3V, input voltage swings should be adjusted not to exceed
VCC.
11.9
27
IDT49C3466 Flow-thruEDC™
ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT 49C466
Device Type
XX
Package
PQF
Plastic Quad Flatpack
49C3466 3.3V 64-Bit Flow-thru™ EDC
3268 drw 23
11.9
28
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