IDT49FCT805 [IDT]
FAST CMOS BUFFER/CLOCK DRIVER; 快速CMOS缓冲器/时钟驱动器
| 型号： | IDT49FCT805 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS BUFFER/CLOCK DRIVER |
| 文件： | 总7页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT49FCT805/A
IDT49FCT806/A
FAST CMOS
BUFFER/CLOCK DRIVER
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• Guaranteed low skew < 700ps (max.)
• Low duty cycle distortion < 1ns (max.)
• Low CMOS power levels
• TTL compatible inputs and outputs
• Rail-to-rail output voltage swing
• High drive: -24mA IOH, 64mA IOL
• Two independent output banks with 3-state control
• 1:5 fanout per bank
The IDT49FCT805/A and IDT49FCT806/A are clock
drivers built using advanced dual metal CMOS technology.
The IDT49FCT805/A is a non-inverting clock driver and the
IDT49FCT806/A is an inverting clock driver. Each device
consists of two banks of drivers. Each bank drives five output
buffers from a standard TTL compatible input. The devices
feature a "heartbeat" monitor for diagnostics and PLL driving.
The MON output is identical to all other outputs and complies
with the output specifications in this document. The
IDT49FCT805/A and IDT49FCT806/A offer low capacitance
inputs with hysteresis. Rail-to-rail output swing improves
noise margin and allows easy interface with CMOS inputs.
• ‘Heartbeat’ monitor output
• Available in DIP, SOIC, SSOP (805 only), QSOP (805
only), Cerpack and LCC packages
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAMS
IDT49FCT805
IDT49FCT806
OEA
OEA
5
5
INA
INA
OA1-OA5
OA1-OA5
5
5
INB
INB
OB1-OB5
OB1-OB5
OEB
OEB
MON
MON
2574 drw 02
2574 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEPTEMBER 1996
1996 Integrated Device Technology, Inc.
9.1
DSC-2574/10
1
IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT49FCT805
INDEX
VCCB
OB1
VCCA
OA1
1
2
20
19
3
2
20 19
OB2
OA2
1
3
4
18
17
OA
3
4
5
6
7
8
18
17
16
15
14
OB
2
3
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
OA3
OB3
GND
A
OB
OA
OA
NC(1)
4
GNDB
GNDA
L20-2
GNDB
16
15
14
13
12
11
5
6
5
OB
4
5
OA4
OA5
OB4
OB5
MON
OB
E20-1
7
9 10 11 12 13
NC(1)
8
OEB
INB
OEA
INA
9
10
LCC
TOP VIEW
2574 drw 04
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
2574 drw 03
IDT49FCT806
VCCA
1
20
VCCB
INDEX
OA1
OA2
2
3
19
18
OB1
OB2
3
2
20 19
1
OA3
GNDA
OA4
4
17
OB3
OA
3
4
18
17
16
15
14
OB
OB
2
3
P20-1
D20-1
SO20-2
&
GND
A
5
6
7
8
GNDB
5
16
15
14
13
12
11
GND
B
OA
OA
NC(1)
4
5
L20-2
OB4
OB5
MON
6
E20-1
OB
OB
4
5
OA5
7
NC (1)
9
10 11 12 13
8
OEA
INA
9
OEB
INB
10
LCC
TOP VIEW
2574 drw 06
DIP/SOIC/CERPACK
TOP VIEW
2574 drw 05
PIN DESCRIPTION
Pin Names
Description
OE
A
,
OE
B
3-State Output Enable Inputs (Active LOW)
Clock Inputs
IN
A
, INB
OA
n
n
, OB
OB
n
Clock Outputs (FCT805)
Clock Outputs (FCT806)
Monitor Output (FCT805)
OA
,
n
MON
MON
Monitor Output (FCT806
NOTE:
2574 tbl 01
1. Pin 8 is not internally connected on devices with a "K" prefix in the date
code. On older devices, pin 8 is internally connected to GND. To insure
compatibility with all products, pin 8 should be connected to GND at the
board level.
9.1
2
IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Typ. Max. Unit
Symbol
Description
Max.
Unit
(2)
VTERM
Terminal Voltage with Respect to –0.5 to +7.0
GND
V
CIN
Input
Capacitance
Output
VIN = 0V
4.5
5.5
6.0
pF
(3)
VTERM
Terminal Voltage with Respect to
GND
–0.5 to
VCC +0.5
V
COUT
VOUT = 0V
8.0
pF
Capacitance
2574 lnk 04
NOTE:
TSTG
IOUT
Storage Temperature
–65 to +150 °C
1. This parameter is measured at characterization but not tested.
DC Output Current
–60 to +120 mA
2574 lnk 03
NOTES:
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
FUNCTION TABLE(1)
Outputs
Inputs
49FCT805
49FCT806
A,
B
INA, INB OAn, OBn MON
n,
n
OE OE
OA OB
MON
2. Input and VCC terminals.
3. Output and I/O terminals.
L
L
H
L
L
H
Z
Z
L
H
L
H
L
H
L
H
L
Z
Z
H
H
H
H
L
NOTE:
2574 tbl 02
1. H = HIGH, L = LOW, Z = High Impedance
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
0.8
±1
±1
±1
±1
–1.2
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
V
µA
µA
µA
µA
V
II H
Input HIGH Current(5)
Input LOW Current(5)
Off State (HIGH Z)(5)
Output Current(5)
VCC = Max.
VCC = Max.
VCC = Max.
VI = VCC
VI = GND
VO = VCC
VO = GND
—
—
II L
—
—
IOZH
IOZL
VIK
IOS
VOH
—
—
—
—
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
VCC = Min., IIN= –18mA
VCC = Max.(3), VO = GND
—
–0.7
–120
VCC
VCC
4.3
–60
VHC
VHC
3.6
mA
V
VCC = 3V, VIN = VLC or VHC, IOH = –32µA
—
VCC = Min.
IOH = –300µA
—
VIN = VIH or VIL
IOH = –12mA MIL.
IOH = –15mA COM'L.
IOH = -24mA MIL.
—
2.4
3.8
—
IOH = -24mA COM'L.
VOL
Output LOW Voltage
VCC = 3V, VIN = VLC or VHC, IOL= 300µA
—
—
—
GND
VLC
V
(4)
VCC = Min.
IOH = 300µA
GND VLC
VIN = VIH or VIL
IOL = 48mA MIL.
IOL = 64mA COM'L.
0.3
0.55
VH
Input Hysteresis for all inputs
—
—
—
200
5
—
mV
ICC
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
500
µA
NOTES:
2574 tbl 05
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
9.1
3
IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
Quiescent Power Supply Current
TTL Inputs HIGH
V
V
CC = Max.
IN = 3.4V(3)
—
1.0
2.5
mA
∆ICC
I
CCD
Dynamic Power Supply Current(4)
Total Power Supply Current(6)
V
CC = Max.
V
IN = VCC
—
0.15
0.20
mA/
MHz/bit
Outputs Open
OE = OE = GND
50% Duty Cycle
CC = Max.
VIN = GND
A
B
IC
V
VIN = VCC
—
—
1.5
2.0
2.5
3.8
mA
Outputs Open
fo= 10MHz
VIN = GND
50% Duty Cycle
V
V
IN = 3.4V
IN = GND
OE
Mon. Output Toggling
CC = Max.
A = OEB =VCC
V
VIN = VCC
—
—
4.1
5.1
6.0(5)
8.5(5)
Outputs Open
fo = 2.5MHz
VIN = GND
50% Duty Cycle
OEA = OEB = GND
V
V
IN = 3.4V
IN = GND
Eleven Outputs
Toggling
2574 tbl 06
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fONO)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fO= Output Frequency
NO= Number of Outputs at fO
All currents are in milliamps and all frequencies are in megahertz.
9.1
4
IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
IDT49FCT805/806
IDT49FCT805A/806A
Com'l.
Mil.
Com'l.
Mil.
(2)
(2)
(2)
(2)
Condition(1)
CL = 50pF
RL = 500Ω
Unit
Min.
Max. Min.
Max. Min.
Max. Min.
Max.
Symbol
tPLH
Parameter
Propagation Delay
INA to OAn, INB to OBn
Output Rise Time
Output Fall Time
1.5
5.6
1.5
6.3
1.5
5.3
1.5
6.0
ns
tPHL
tR
tF
—
—
—
1.5
1.5
0.7
—
—
—
1.5
1.5
0.9
—
—
—
1.5
1.5
0.7
—
—
—
1.5
1.5
0.9
ns
ns
ns
tSK(o) Output skew: skew between outputs of all
banks of same package (inputs tied together)
tSK(p) Pulse skew: skew between opposite
transitions of same output (|tPHL-tPLH|)
—
—
1.0
1.5
—
—
1.1
1.5
—
—
1.0
1.5
—
—
1.1
1.5
ns
ns
tSK(t) Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
tPZL
tPZH
Output Enable Time
OEA to OAn, OEB to OBn
1.5
1.5
8.0
7.0
1.5
1.5
8.5
7.5
1.5
1.5
8.0
7.0
1.5
1.5
8.5
7.5
ns
tPLZ
tPHZ
Output Disable Time
OEA to OAn, OEB to OBn
ns
2574 tbl 07
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay
limits do not imply skew.
9.1
5
IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIME
SWITCH POSITION
VCC
7.0V
Test
Disable LOW
Enable LOW
Switch
Closed
500Ω
V OUT
VIN
Disable HIGH
Enable HIGH
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Open
Pulse
Generator
D.U.T.
2574 lnk 11
50pF
C L
500Ω
R T
Generator.
2574 drw 07
PACKAGE DELAY
OUTPUT SKEW - tSK(o)
3V
3V
1.5V
0V
1.5V
0V
INPUT
t
PLH1
tPHL1
INPUT
VOH
tPLH
tPHL
1.5V
V
OH
V
OL
OUTPUT 1
OUTPUT 2
2.0V
t
SK(o)
tSK(o)
1.5V
VOH
0.8V
VOL
1.5V
OUTPUT
VOL
tF
t
PLH2
t
R
tPHL2
t
SK(o) = |tPLH2 -
tPLH1
|
or |tPHL2 -
tPHL1
|
2574 drw 08
2574 drw 09
PACKAGE SKEW - tSK(t)
PULSE SKEW - tSK(p)
3V
1.5V
0V
3V
INPUT
1.5V
0V
t
PHL1
tPLH1
INPUT
VOH
t
PHL
1.5V
t
PLH
V
OH
VOL
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
1.5V
V
t
SK(t)
t
SK(t)
VOH
OL
OUTPUT
1.5V
VOL
t
SK(p) = |tPHL - tPLH|
t
PLH2
t
PHL2
2574 drw 10
t
SK(t) = |tPLH2 -
tPLH1
|
or |tPHL2 -
t
PHL1
|
Package 1 and Package 2 are same device type and speed grade
2574 drw 11
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
CONTROL
INPUT
1.5V
0V
t
PZL
t PLZ
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
t PHZ
t
PZH
OUTPUT
NORMALLY
HIGH
0.3V VOH
0V
SWITCH
OPEN
1.5V
0V
2574 drw 12
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
9.1
6
IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT49FCT
XXX
XX
X
Package
Process/
Device Type
Temperature
Range
Blank
B
Commercial (0°C to +70°C)
MIL-STD-883, Class B (–55°C to +125°C)
P
Plastic DIP
D
CERDIP
E
L
SO
PY
Q
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline IC
Quarter-size Small Outline IC
805
Non-Inverting Buffer/Clock Driver
Inverting Buffer/Clock Driver
806
805A
806A
2574 drw 17
9.1
7
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