IDT54FCT16646ATPV [IDT]
FAST CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS (3-STATE); FAST CMOS 16位总线收发器/寄存器（三态）
| 型号： | IDT54FCT16646ATPV |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS (3-STATE) |
| 文件： | 总9页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT16646T/AT/CT/ET
IDT54/74FCT162646T/AT/CT/ET
FAST CMOS 16-BIT BUS
TRANSCEIVER/
REGISTERS (3-STATE)
Integrated Device Technology, Inc.
74FCT162646T/AT/CT/ET 16-bit registered transceivers are
built using advanced dual metal CMOS technology. These
high-speed, low-power devices are organized as two inde-
pendent 8-bit bus transceivers with 3-state D-type registers.
The control circuitry is organized for multiplexed transmission
of data between A bus and B bus either directly or from the
internal storage registers. Each 8-bit transceiver/register fea-
tures direction control (xDIR), over-riding Output Enable con-
trol (xOE) and Select lines (xSAB and xSBA) to select either
real-time data or stored data. Separate clock inputs are
provided for A and B port registers. Data on the A or B data
bus, or both, can be stored in the internal registers by the
LOW-to-HIGH transitions at the appropriate clock pins. Flow-
through organization of signal pins simplifies layout. All inputs
are designed with hysteresis for improved noise margin.
The IDT54/74FCT16646T/AT/CT/ET are ideally suited for
driving high-capacitance loads and low-impedance
backplanes. The output buffers are designed with power off
disable capability to allow "live insertion" of boards when used
as backplane drivers.
FEATURES:
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for
ABT functions
– Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage ≤1µA (max.)
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
– VCC = 5V ±10%
• Features for FCT16646T/AT/CT/ET:
– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25°C
• Features for FCT162646T/AT/CT/ET:
– Balanced Output Drivers: ±24mA (commercial),
±16mA (military)
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
The IDT54/74FCT162646T/AT/CT/ET have balanced
output drive with current limiting resistors. This offers low
ground bounce, minimal undershoot, and controlled output
fall times–reducing the need for external series terminating
resistors. The IDT54/74FCT162646T/AT/CT/ET are plug-in
replacements for the IDT54/74FCT16646T/AT/CT/ET and
54/74ABT16646 for on-board bus interface applications.
DESCRIPTION:
The IDT54/74FCT16646T/AT/CT/ET and IDT54/
FUNCTIONAL BLOCK DIAGRAM
1OE
2OE
1DIR
2DIR
1CLKBA
1SBA
2
CLKBA
SBA
CLKAB
2
1CLKAB
2
1SAB
2SAB
B REG
B REG
D
D
C
C
A REG
2B1
1B1
A REG
1A1
2A1
D
D
C
C
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
2540 drw 01
2540 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1996
1996 Integrated Device Technology, Inc.
5.13
DSC-4231/9
1
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1DIR
1
56
1OE
1CLKBA
1SBA
GND
1B1
1DIR
1CLKAB
1SAB
GND
1A1
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE
2
1CLKBA
1CLKAB
1SAB
GND
1A1
2
55
3
1SBA
GND
1B1
3
54
4
4
53
5
5
52
1A2
6
1B2
1A2
6
51
1B2
VCC
7
VCC
1B3
VCC
1A3
7
50
VCC
1B3
1A3
8
8
49
1A4
9
1B4
1A4
9
48
1B4
1A5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1B5
1A5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
47
1B5
GND
1A6
GND
1B6
GND
1A6
46
GND
1B6
45
1A7
1B7
1A7
44
1B7
1A8
1B8
SO56-1
SO56-2
SO56-3
1A8
E56-1 43
1B8
2A1
2B1
2A1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2B1
2A2
2B2
2A2
2B2
2A3
2B3
2A3
2B3
GND
2A4
GND
2B4
GND
2A4
GND
2B4
2A5
2B5
2A5
2B5
2A6
2B6
2A6
2B6
VCC
VCC
2B7
VCC
2A7
VCC
2B7
2A7
2A8
2B8
2A8
2B8
GND
2SAB
2CLKAB
2DIR
GND
2SBA
2CLKBA
GND
2SAB
2CLKAB
2DIR
GND
2SBA
2CLKBA
2OE
2OE
2540 drw 03
SSOP/
TSSOP/TVSOP
TOP VIEW
2540 drw 04
CERPACK
TOP VIEW
5.13
2
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input
Conditions
Typ. Max. Unit
Pin Names
Description
Data Register A Inputs
CIN
VIN = 0V
3.5
6.0
pF
xAx
Capacitance
I/O
Capacitance
Data Register B Outputs
Data Register B Inputs
Data Register A Outputs
CI/O
VOUT = 0V
3.5
8.0
pF
xBx
2540 tbl 02
NOTE:
xCLKAB, xCLKBA Clock Pulse Inputs
1. This parameter is measured at characterization but not tested.
xSAB, xSBA
xDIR, xOE
Output Data Source Select Inputs
Output Enable Inputs
2540 tbl 01
FUNCTION TABLE(2)
Inputs
Data I/O(1)
Operation or Function
x
xDIR
xCLKAB xCLKBA
xSAB
xSBA
xAx
xBx
OE
H
H
X
X
H or L
↑
H or L
↑
X
X
X
X
Input
Input
Isolation
Store A and B Data
L
L
L
L
L
L
X
X
X
H or L
X
X
X
L
L
Output
Input
Input
Real Time B Data to A Bus
Stored B Data to A Bus
Real Time A Data to B Bus
Stored A Data to B Bus
H
X
X
H
H
X
Output
H or L
X
H
NOTES:
2540 tbl 03
1. The data output functions may be enabled or disabled by various signals at the xOEor xDIR inputs. Data
inputfunctionsarealwaysenabled,i.e.dataatthebuspinswillbestoredoneveryLOW-to-HIGHtransition
on the clock inputs.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
↑ = LOW-to-HIGH Transition
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max.
Unit
(2) Terminal Voltage with Respect to
VTERM
–0.5 to +7.0
V
GND
(3) Terminal Voltage with Respect to
GND
VTERM
–0.5 to
VCC +0.5
V
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150 °C
–60 to +120 mA
2540 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
abovethoseindicatedintheoperationalsectionsofthisspecificationisnot
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
5.13
3
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUS
A
BUS
B
BUS
A
BUS
B
2540 drw 06
2540 drw 05
xCLKAB
X
xDIR
L
xOE
L
xDIR
H
xOE
L
xCLKAB
X
xCLKBA
X
xSAB
L
xSBA
X
xCLKBA
X
xSAB
xSBA
L
X
REAL-TIME TRANSFER
BUS A TO B
REAL-TIME TRANSFER
BUS B TO A
BUS
A
BUS
B
BUS
A
BUS
B
2540 drw 08
2540 drw 07
xDIR
xOE
xCLKAB
X
xCLKBA
H or L
X
xSAB
xSBA
xDIR
H
xOE
L
xCLKAB
xCLKBA
xSAB
xSBA
X
↑
X
X
↑
X
X
X
L
L
L
X
H
H
X
L
L
X
↑
H
H or L
↑
X
H
X
STORAGE FROM
A AND/OR B
TRANSFER STORED
DATA TO A AND/OR B
NOTE:
1. Cannot transfer data to A bus and B bus simultaneously.
5.13
4
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
—
—
—
—
–80
—
—
—
—
—
0.8
±1
V
VIL
II H
Input LOW Level
Guaranteed Logic LOW Level
V
Input HIGH Current (Input pins)(5)
Input HIGH Current (I/O pins)(5)
Input LOW Current (Input pins)(5)
Input LOW Current (I/O pins)(5)
High Impedance Output Current
(3-State Output pins)(5)
VCC = Max.
VI = VCC
—
µA
—
±1
II L
VI = GND
—
±1
—
±1
IOZH
IOZL
VIK
VCC = Max.
VO = 2.7V
VO = 0.5V
—
±1
µA
—
±1
Clamp Diode Voltage
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
—
–0.7
–140
100
5
–1.2
–225
—
V
IOS
VH
Short Circuit Current
mA
mV
µA
Input Hysteresis
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
500
2540 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16646T
Symbol
Parameter
Test Conditions(1)
VCC = Max., VO = 2.5V(3)
Min. Typ.(2) Max.
Unit
IO
Output Drive Current
–50
2.5
2.4
—
3.5
3.5
–180
—
mA
VOH
Output HIGH Voltage
VCC = Min.
IOH = –3mA
V
V
VIN = VIH or VIL
IOH = –12mA MIL.
IOH = –15mA COM'L.
IOH = –24mA MIL.
IOH = –32mA COM'L.(4)
IOL = 48mA MIL.
—
2.0
—
3.0
0.2
—
—
0.55
±1
V
V
VOL
Output LOW Voltage
VCC = Min.
VIN = VIH or VIL
IOL = 64mA COM'L.
IOFF
Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤ 4.5V
—
µA
2540 lnk 06
OUTPUT DRIVE CHARACTERISTICS FOR FCT162646T
Symbol
Parameter
Test Conditions(1)
VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
Min. Typ.(2) Max.
Unit
IODL
Output LOW Current
60
–60
2.4
115
200
mA
VOUT = 1.5V(3)
IODH
VOH
Output HIGH Current
Output HIGH Voltage
VCC = 5V, VIN = VIH or VIL,
–115 –200
mA
V
VCC = Min.
IOH = –16mA MIL.
IOH = –24mA COM'L.
IOL = 16mA MIL.
3.3
0.3
—
VIN = VIH or VIL
VCC = Min.
VOL
Output LOW Voltage
—
0.55
V
VIN = VIH or VIL
IOL = 24mA COM'L.
2540 lnk 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
5.13
5
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
—
0.5
1.5
mA
ICCD
Dynamic Power Supply Current(4) VCC = Max.
Outputs Open
VIN = VCC
VIN = GND
—
75
120
µA/
MHz
xDIR = xOE= GND
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
Outputs Open
VIN = VCC
VIN = GND
—
—
0.8
1.3
1.7
3.2
mA
fCP = 10MHz (xCLKBA)
50% Duty Cycle
xDIR = xOE = GND
One Bit Toggling
fi = 5MHz
VIN = 3.4V
VIN = GND
50% Duty Cycle
VCC = Max.
Outputs Open
VIN = VCC
VIN = GND
—
—
3.8
8.3
6.5(5)
fCP = 10MHz (xCLKBA)
50% Duty Cycle
xDIR = xOE = GND
Sixteen Bits Toggling
fi = 2.5MHz
VIN = 3.4V
VIN = GND
20.0(5)
50% Duty Cycle
2540 tbl 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
5.13
6
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT16646T/162646T
FCT16646AT/162646AT
Com'l. Mil.
Com'l.
Mil.
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tSU
Propagation Delay
Bus to Bus
CL = 50pF
RL = 500Ω
2.0
2.0
2.0
2.0
2.0
4.0
2.0
6.0
—
9.0
2.0
11.0
2.0
2.0
2.0
2.0
2.0
2.0
1.5
5.0
—
6.3
2.0
7.7
ns
Output Enable Time
xDIR or xOE to Bus
Output Disable Time
xDIR or xOE to Bus
Propagation Delay
Clock to Bus
14.0
9.0
9.0
11.0
—
2.0
2.0
2.0
2.0
4.5
2.0
6.0
—
15.0
11.0
10.0
12.0
—
9.8
6.3
6.3
7.7
—
2.0
2.0
2.0
2.0
2.0
1.5
5.0
—
10.5
7.7
7.0
8.4
—
ns
ns
ns
ns
ns
ns
ns
Propagation Delay
xSBA or xSAB to Bus
Set-up Time HIGH or
LOW Bus to Clock
Hold Time HIGH or
LOW Bus to Clock
Clock Pulse Width
HIGH or LOW
tH
—
—
—
—
tW
—
—
—
—
tSK(o) Output Skew(3)
0.5
0.5
0.5
0.5
ns
2540 tbl 09
FCT16646CT/162646CT
Com'l. Mil.
FCT16646ET/162646ET
Com'l. Mil.
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tSU
Propagation Delay
Bus to Bus
CL = 50pF
RL = 500Ω
1.5
5.4
1.5
6.0
1.5
3.8
—
—
ns
Output Enable Time
xDIR or xOE to Bus
Output Disable Time
xDIR or xOE to Bus
Propagation Delay
Clock to Bus
1.5
1.5
1.5
1.5
2.0
1.5
5.0
—
7.8
6.3
5.7
6.2
—
1.5
1.5
1.5
1.5
2.0
1.5
5.0
—
8.9
7.7
6.3
7.0
—
1.5
1.5
1.5
1.5
2.0
0.0
3.0(4)
—
4.8
4.0
3.8
4.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
Propagation Delay
xSBA or xSAB to Bus
Set-up Time HIGH or
LOW Bus to Clock
Hold Time HIGH or
LOW Bus to Clock
Clock Pulse Width
HIGH or LOW
tH
—
—
—
tW
—
—
—
tSK(o) Output Skew(3)
0.5
0.5
0.5
ns
2540 tbl10
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5.13
7
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
VCC
Open Drain
Disable Low
7.0V
Closed
500Ω
Enable Low
VOUT
VIN
Open
All Other Tests
Pulse
Generator
2556 lnk 10
D.U.T.
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
50pF
RT = Termination resistance: should be equal to ZOUT of the Pulse
500Ω
T
R
Generator.
C
L
2556 drw 05
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
tW
t
REM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
2556 drw 07
3V
1.5V
0V
CLEAR
tSU
t
H
CLOCK ENABLE
ETC.
2556 drw 06
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
t
PLH
t
t
PHL
PHL
t
PZL
tPLZ
VOH
OUTPUT
3.5V
1.5V
3.5V
1.5V
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
VOL
t
PLH
0.3V
0.3V
VOL
3V
1.5V
0V
t
PZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0V
2556 drw 09
2556 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
5.13
8
IDT54/74FCT16646T/AT/CT/ET, 162646T/AT/CT/ET
FAST CMOS 16-BIT BUS TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
FCT
X
X
XXXX
Process
Temperature
Range
Device Type
Package
Commercial
MIL-STD-883, Class B
Blank
B
PV
PA
PF
E
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
16646T
Non-Inverting 16-Bit Transceiver/Register
16646AT
16646CT
16646ET
162646T
162646AT
162646CT
162646ET
–55°C to +125°C
–40°C to +85°C
54
74
2540 drw 14
5.13
9
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