IDT54FCT388915T70L [IDT]
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE); 3.3V低偏移基于PLL的CMOS时钟驱动器（ 3 -STATE ）
| 型号： | IDT54FCT388915T70L |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| 文件： | 总11页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT388915T
70/100/133/150
3.3V LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
(WITH 3-STATE)
PRELIMINARY
Integrated Device Technology, Inc.
is fed back to the PLL at the FEEDBACK input resulting in
essentially zero delay across the device. The PLL consists of
the phase/frequency detector, charge pump, loop filter and
VCO. The VCO is designed for a 2Q operating frequency
range of 40MHz to f2Q Max.
The IDT54/74FCT388915T provides 8 outputs with 350ps
skew. The Q5 output is inverted from the Q outputs. The 2Q
runs at twice the Q frequency and Q/2 runs at half the Q
frequency.
FEATURES:
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)
• Max. output frequency: 150MHz
• Pin and function compatible with FCT88915T, MC88915T
• 5 non-inverting outputs, one inverting output, one 2x
output, one ÷2 output; all outputs are TTL-compatible
• 3-State outputs
TheFREQ_SELcontrolprovidesanadditional÷ 2optionin
the output path. PLL _EN allows bypassing of the PLL, which
is useful in static test modes. When PLL_EN is low, SYNC
input may be used as a test clock. In this test mode, the input
frequency is not limited to the specified range and the polarity
of outputs is complementary to that in normal operation
(PLL_EN = 1). The LOCK output attains logic HIGH when the
PLL is in steady-state phase and frequency lock. When OE/
RSTis low, all the outputs are put in high impedance state and
registers at Q, Q and Q/2 outputs are reset.
• Output skew < 350ps (max.)
• Duty cycle distortion < 500ps (max.)
• Part-to-part skew: 1ns (from tPD max. spec)
• 32/–16mA drive at CMOS output voltage levels
• VCC = 3.3V ± 0.3V
• Inputs can be driven by 3.3V or 5V components
• Available in 28 pin PLCC, LCC and SSOP packages
DESCRIPTION:
The IDT54/74FCT388915T uses phase-lock loop technol-
ogy to lock the frequency and phase of outputs to the input
reference clock. It provides low skew clock distribution for
high performance PCs and workstations. One of the outputs
TheIDT54/74FCT388915Trequiresoneexternalloopfilter
component as recommended in Figure 3.
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK
LOCK
Voltage
Controlled
Oscilator
Phase/Freq.
Detector
0
1
Charge Pump
SYNC (0)
SYNC (1)
M
u
x
LF
REF_SEL
PLL_EN
0
1
2Q
Q0
Mux
(
÷
1)
2)
1
0
D
M
u
x
Q
Q
CP
R
Divide
-By-2
(
÷
Q1
Q2
Q3
D
Q
Q
Q
Q
Q
FREQ_SEL
OE/RST
CP
R
R
R
R
R
D
CP
D
CP
D
Q4
Q5
Q/2
CP
D
CP
D
Q
CP
R
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
3052 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1995
1995 Integrated Device Technology, Inc.
9.8
DSC-4243/1
1
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
1
2
3
28
27
26
GND
Q5
Q4
4
3
2
1
28 27 26
VCC
2Q
25 Q/2
FEEDBK
REF_SEL
SYNC(0)
VCC(AN)
LF
5
VCC
GND
24
4
6
OE/RST
FEEDBACK
REF_SEL
SYNC(0)
VCC(AN)
LF
25
24
23
Q/2
GND
Q3
5
23 Q3
7
6
J28-1,
L28-1
7
22
21
20
19
18
17
VCC
VCC
22
SO28-7
8
8
Q2
Q2
9
21
20
19
9
GND
GND(AN)
SYNC(1)
FREQ_SEL
10
11
12
LOCK
PLL_EN
GND
10
11
GND
LOCK
GND(AN)
SYNC(1)
12 13 14 15 16 17 18
GND
Q0
13
14
16
15
Q1
VCC
3052 drw 03
SSOP
3052 drw 02
TOP VIEW
PLCC/LCC
TOP VIEW
PIN DESCRIPTION
Pin Name
SYNC(0)
SYNC(1)
REF_SEL
FREQ_SEL
FEEDBACK
LF
I/O
I
Description
Reference clock input.
Reference clock input.
I
I
Chooses reference between SYNC (0) & SYNC (1). (Refer to functional block diagram).
Selects between ÷ 1 and ÷ 2 frequency options. (Refer to functional block diagram).
Feedback input to phase detector.
I
I
I
Input for external loop filter connection.
Q0-Q4
O
O
O
O
O
I
Clock output.
Q5
Inverted clock output.
2Q
Clock output (2 x Q frequency).
Q/2
Clock output (Q frequency ÷ 2).
LOCK
Indicates phase lock has been achieved (HIGH when locked).
OE/RST
Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are
enabled. When LOW, outputs are in HIGH impedance.
PLL_EN
I
Disables phase-lock for low frequency testing. (Refer to functional block diagram).
3052 tbl 01
9.8
2
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Typ. Max. Unit
Symbol
Rating
Commercial
Military
Unit
(2)
CIN
Input
Capacitance
Output
VIN = 0V
4.5
5.5
6.0
pF
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to +4.6 –0.5 to +4.6
–0.5 to +7.0 –0.5 to +7.0
–0.5 to VCC –0.5 to VCC
V
COUT
VOUT = 0V
8.0
pF
(3)
VTERM
Terminal Voltage
with Respect to
GND
V
Capacitance
3052 lnk 03
NOTE:
1. This parameter is measured at characterization but not tested.
(4)
VTERM
Terminal Voltage
with Respect to
GND
V
+0.5
+0.5
TA
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
0 to +70
–55 to +125 °C
TBIAS
TSTG
IOUT
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
–60 to +60
–60 to +60 mA
3052 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to 70°C, VCC = 3.3V ±0.3V
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
5.5
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
–0.5
—
—
—
0.8
±1
V
II H
Input HIGH Current
VCC = Max.
VCC = Max.
VI = 5.5V
VI = GND
VO = VCC
VO = GND
µA
µA
µA
µA
V
II L
Input LOW Current
—
—
±1
IOZH
IOZL
VIK
High Impedance Output Current
(3-State Output Pins)
Clamp Diode Voltage
Output Drive Current
Output Drive Current
Output HIGH Voltage
Output LOW Voltage
Input Hysteresis
—
—
±1
—
—
±1
VCC = Min., IIN = –18mA
—
–0.7
—
–1.2
—
IODH
IODL
VOH
VOL
VH
VCC = Max., VIN = VIH or VIL, VO = 1.5V(3)
VCC = Max., VIN = VIH or VIL, VO = 1.5V(3)
–36
50
2.4(5)
mA
mA
V
—
—
VCC = Min.
VCC = Min.
IOH = –16mA
IOL = 32mA
3.0
0.3
100
2.0
—
—
0.5
—
V
—
—
mV
mA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
(Test mode)
—
4.0
3052 tbl 04
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC - 0.6V at rated current.
9.8
3
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Test Conditions(1)
Min. Typ.(2) Max.
Unit
∆ICC
VCC = Max.
VIN = VCC –0.6V(3)
—
2.0
30
µA
VIN = VCC –2.1V(3)
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
All Outputs Open
VIN = VCC
VIN = GND
—
0.2
0.3
mA/
MHz
CPD
IC
Power Dissipation Capacitance
Total Power Supply Current(6)
50% Duty Cycle
VCC = Max.
—
—
15
30
25
60
pF
mA
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. All bits loaded with
15pF
VCC = Max.
—
90
120
mA
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. All bits loaded with
50Ω Thevenin termination and 20pF
3052 tbl 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3. Per TTL driven input. All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (f) + ILOAD
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f =2Q Frequency
ILOAD = Dynamic Current due to load.
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
Min.
Max.
Unit
TRISE/FALL Rise/Fall Times,
SYNC inputs
—
3.0
ns
(0.8V to 2.0V)
Frequency Input Frequency,
SYNC Inputs
10.0(1)
25%
2Q fmax MHz
Duty Cycle Input Duty Cycle,
SYNC Inputs
75%
—
3052 tbl 06
OUTPUT FREQUENCY SPECIFICATIONS
Max. (2)
133
Symbol
Parameter
Min.
70
100
150
Unit
f2Q
Operating frequency 2Q Output
40
70
100
133
66.7
33.3
150
MHz
fQ
Operating frequency Q0-Q4, Q5 Outputs
Operating frequency Q/2 Output
20
10
35
50
25
75
MHz
fQ/2
17.5
37.5
MHz
3052 tbl 07
NOTES:
1. Note 7 in "General AC Specification Notes" and Figure 3 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded.
9.8
4
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Condition(1)
Min.*
Max.*
Unit
tRISE/FALL
Rise/Fall Time
Load = 50Ω to
0.2(2)
1.5
ns
All Outputs
VCC/2, CL = 20pF
(between 0.8V and 2.0V)
Output Pulse Width
(3)
tPULSE WIDTH
Load = 50Ω to
0.5tCYCLE – 0.5(5) 0.5tCYCLE + 0.5(5) ns
0.5tCYCLE – 0.7(5) 0.5tCYCLE + 0.7(5) ns
Q, Q, Q/2 outputs(3)
tPULSE WIDTH
2Q Output(3)
tPD
Q0-Q4, Q5, Q/2, @ 1.5V
Output Pulse Width
VCC/2, CL = 20pF
2Q @ 1.5V
SYNC input to FEEDBACK delay
Load = 50Ω to
VCC/2, CL = 20pF
0.1µF from LF to
Analog GND(5)
–0.5
+0.5
ns
SYNC-FEEDBACK(3) (measured at SYNC0 or 1 and FEEDBACK
input pins)
tSKEWr
Output to Output Skew
Load = 50Ω to
—
250
ps
(rising)(3,4)
between outputs 2Q, Q0-Q4,
Q/2 (rising edges only)
VCC/2, CL = 20pF
tSKEWf
(falling)(3,4)
tSKEWall (3,4)
Output to Output Skew
—
—
250
350
10
ps
ps
between outputs Q0-Q4 (falling edges only)
Output to Output Skew
2Q, Q/2, Q0-Q4 rising, Q5 falling
Time required to acquire
(6)
tLOCK
1(2)
ms
Phase-Lock from time
SYNC input signal is received
Output Enable Time
tPZH
tPZL
tPHZ
tPLZ
3(2)
3(2)
14
14
ns
OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q
Output Disable Time
ns
OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q
3052 tbl 08
GENERAL AC SPECIFICATION NOTES:
PRELIMINARY.
*
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.
5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.
6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin. tLOCK Max. is with C1 = 0.1µF, tLOCK Min. is with C1 = 0.01µF. (Where
C1 is loop filter capacitor shown in Figure 2).
9.8
5
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NOTES:
7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback
configurations. The allowable SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges,
depending on whether FREQ_SEL is HIGH or LOW. Also it is possible to feed back the Q5 output, thus creating a 180° phase shift between the SYNC
input and the Q outputs. The table below summarizes the allowable SYNC frequency range for each possible configuration.
Phase Relationship
FREQ_SEL
Level
Feedback
Output
Q/2
Allowable SYNC Input
Frequency Range (MHZ)
10 to (2x _Q fMAX Spec)/4
Corresponding 2Q Output
Frequency Range
of the Q Outputs
to Rising SYNC Edge
0°
HIGH
40 to (2Q fMAX Spec)
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Any Q (Q0-Q4)
20 to (2x_Q fMAX Spec)/2
20 to (2x_Q fMAX Spec)/2
40 to (2x_Q fMAX Spec)
5 to (2x_Q fMAX Spec)/8
10 to (2x_Q fMAX Spec)/4
10 to (2x_Q fMAX Spec)/4
20 to (2x_Q fMAX Spec)/2
40 to (2Q fMAX Spec)
40 to (2Q fMAX Spec)
40 to (2Q fMAX Spec)
20 to (2Q fMAX Spec)/2
20 to (2Q fMAX Spec)/2
20 to (2Q fMAX Spec)/2
20 to (2Q fMAX Spec)/2
0°
180°
0°
Q5
2X_Q
Q/2
0°
Any Q (Q0-Q4)
Q5
0°
180°
2X_Q
0°
3052 tbl 09
8. ThetPDspecdescribeshowthephaseoffsetbetweentheSYNCinputandtheoutputconnectedtotheFEEDBACKinput, varieswithprocess, temperature
and voltage. Measurements were made with a 10MHz SYNC input and Q/2 output as feedback. The phase measurements were made at 1.5V. The Q/
2 output was terminated at the FEEDBACK input with 100Ω to VCC and 100Ω to ground. tPD measurements were made with the loop filter connection
shown below:
External Loop
Filter
LF
0.1µF
C1
Analog GND
3052 drw 04
9.8
6
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BOARD VCC
ANALOG VCC
Analog loop filter
10µF
Low
Freq.
Bypass
0.1µF
section of the
High
LF
FCT388915T
Freq.
Bypass
0.1µF (Loop
Filter Cap)
ANALOG GND
A separate Analog power supply
is not necessary and should not
be used. Following these
BOARD GND
prescribed guidelines is all that is
necessary to use the FCT388915
in a normal digital environment.
3052 drw 12
Figure 2. Recommended Loop Filter and Analog Isolation Scheme for the FCT388915T
NOTES:
1. Figure 2 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure
stable and jitter-free operation:
a.
b.
All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of
long traces can cause undesirable voltage transients at the LF pin.
The 10µF low frequency bypass capacitor and the 0.1µF high frequency bypass capacitor form a wide bandwidth filter that will minimize the
388915T's sensitivity to voltage transients from the system digital VCC supply and ground planes.
If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, VCC step deviations should
not occur at the 388915T's digital VCC supply. The purpose of the bypass filtering scheme shown in figure 2 is to give the 388915T additional
protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system.
The loop filter capacitor (0.1µF) can be a ceramic chip capacitor, the same as a standard bypass capacitor.
c.
2. In addition to the bypass capacitors used in the analog filter of figure 2 there should be a 0.1µF bypass capacitor between each of the other (digital) four
VCC pins and the board ground plane. This will reduce output switching noise caused by the 388915T outputs, in addition to reducing potential for noise
in the "analog" section of the chip. These bypass capacitors should also be tied as close to the 388915T package as possible.
9.8
7
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
50 MHz signal
The frequency relationship shown here is applicable to all Q
outputs (Q0, Q1, Q2, Q3 and Q4).
25 MHz feedback signal
HIGH
1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATION-
SHIP
2Q
Q/2
Q4
OE/RST Q5
FEEDBACK
In this application, the Q/2 output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of Q/2 and SYNC, thus the Q/2 frequency will equal the
SYNC frequency. The Q outputs (Q0-Q4, Q5) will always run
at 2X the Q/2 frequency, and the 2Q output will run at 4X the
Q/2 frequency.
12.5 MHz
signal
LOW
REF_SEL
SYNC(0)
25 MHz
input
25 MHz
Q3
Q2
"Q"
FCT388915T
Clock
VCC(AN)
LF
Outputs
50 MHz signal
12.5 MHz feedback signal
GND(AN)
FQ_SEL
HIGH
HIGH
PLL_EN
HIGH
Q0
Q1
2Q
Q/2
Q4
OE/RST Q5
FEEDBACK
3052 drw 10
LOW
REF_SEL
SYNC(0)
12.5 MHz
input
Allowable Input Frequency Range:
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)
25 MHz
"Q"
Q3
Q2
Clock
Outputs
FCT388915T
VCC(AN)
LF
Figure 3b. Wiring Diagram and Frequency Relationships With Q4
Output Feedback
GND(AN)
FQ_SEL
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATION-
SHIP
PLL_EN
HIGH
Q0
Q1
In this application, the 2Q output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of 2Q and SYNC, thus the 2Q frequency will equal the
SYNC frequency. The Q/2 output will always run at 1/4 the
2Q frequency, and the Q output will run at 1/2 the 2Q
frequency.
HIGH
3052 drw 09
Allowable Input Frequency Range:
10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)
50 MHz feedback signal
HIGH
Figure 3a. Wiring Diagram and Frequency Relationships With Q/2
Output Feedback
2Q
Q/2
Q4
OE/RST
Q5
12.5 MHz
input
FEEDBACK
REF_SEL
SYNC(0)
LOW
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATION-
SHIP
50 MHz
input
25 MHz
Q3
Q2
"Q"
Clock
FCT388915T
VCC(AN)
In this application, the Q4 output is connected to the
FEEDBACK input. The internal PLL will line up the positive
edges of Q4 and SYNC, thus the Q4 frequency (and the rest
of the "Q" outputs) will equal the SYNC frequency. The Q/2
output will always run at 1/2 the Q frequency, and the 2Q
output will run at 2X the Q frequency.
Outputs
LF
GND(AN)
FQ_SEL
PLL_EN
HIGH
Q0
Q1
HIGH
3052 drw 11
Allowable Input Frequency Range:
40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)
Figure 3c. Wiring Diagram and Frequency Relationships With 2Q
Output Feedback
9.8
8
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CPU
CARD
CMMU
CPU
CMMU
FCT388915T
PLL
2f
CLOCK
@f
CMMU
CMMU
SYSTEM
CLOCK
SOURCE
CMMU
CPU
CARD
CMMU
CPU
CMMU
CMMU
CMMU
FCT388915T
PLL
2f
CMMU
DISTRIBUTE
CLOCK @f
CLOCK @2f
at point of use
FCT388915T
PLL
2f
MEMORY
CONTROL
MEMORY
CARDS
CLOCK @2f
at point of use
3052 drw 13
Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication
and Low Board-to-Board skew
FCT388915T System Level Testing Functionality
WhenthePLL_ENpinisLOW,thePLLisbypassedandthe These relationships can be seen in the block diagram. A
FCT388915T is in low frequency "test mode". In test mode recommended test configuration would be to use SYNC0 or
(with FREQ_SEL HIGH), the 2Q output is inverted from the SYNC1 as the test clock input, and tie PLL_EN and REF_SEL
selected SYNC input, and the Q outputs are divide-by-2 together and connect them to the test select logic.
(negative edge triggered) of the SYNC input, and the Q/2
This functionality is needed since most board-level testers
output is divide-by-4 (negative edge triggered). With
run at 1 MHz or below, and theFCT 388915T cannot lock onto
FREQ_SEL LOW the 2Q output is divide-by-2 of the SYNC,
that low of an input frequency. In the test mode described
the Q outputs divide-by-4, and the Q/2 output divide-by-8.
above, any test frequency test can be used.
9.8
9
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
50Ω TO VCC/2, CL = 20PF
ENABLE AND DISABLE TEST CIRCUIT
VCC
6.0V
VCC
VCC
100Ω
GND
500Ω
VOUT
VIN
VOUT
Pulse
Generator
VIN
D.U.T.
Pulse
Generator
D.U.T.
20pF
100Ω
C
L
RT
500Ω
RT
3052 drw 05
3052 drw 06
PROPAGATION DELAY, OUTPUT SKEW
1.5V
SYNC INPUT
(SYNC (1) or
SYNC (0))
t
CYCLE
SYNC INPUT
tPD
VCC/2
VCC/2
FEEDBACK
INPUT
Q/2 OUTPUT
t
t
t
SKEWf
t
SKEWf
SKEWr
t
SKEWr
SKEWALL
VCC/2
Q0-Q4
OUTPUTS
t
CYCLE "Q" OUTPUTS
1.5V
Q5 OUTPUT
2Q OUTPUT
VCC/2
3052 drw 08
(These waveforms represent the configuration of Figure 3a)
NOTES:
1. The FCT388915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle.
2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as ± deviation
around a center point.
3. If a Q ouput is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q
output would run at twice the SYNC frequency and the Q/2 output would run at half the SYNC frequency.
ENABLE AND DISABLE TIMES
SWITCH POSITION
ENABLE
DISABLE
Test
Disable Low
Switch
3V
6V
CONTROL
INPUT
1.5V
0V
Enable Low
Disable High
Enable High
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
GND
tPZL
tPLZ
3V
1.5V
3V
OUTPUT
NORMALLY
LOW
SWITCH
6V
3052 tbl 10
0.3V
0.3V
VOL
tPZH
tPHZ
VOH
Generator.
OUTPUT
NORMALLY
HIGH
SWITCH
GND
1.5V
0V
0V
3052 drw 07
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: tF ≤ 2.5ns; tR ≤ 2.5ns
9.8
10
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
XXXX
IDT
XX
FCT
X
X
X
Speed
Temp. Range
Device Type
Package
Process
Blank
B
Commercial
MIL-STD-883, Class B
J
PLCC
LCC
SSOP
L
PY
70MHz Max. Frequency
100MHz Max. Frequency
133MHz Max. Frequency
150MHz Max. Frequency
70
100
133
150
3.3V Low skew PLL-based CMOS clock driver
388915T
–55°C to +125°C
0°C to +70°C
54
74
3052 drw 14
9.8
11
相关型号：
IDT54FCT399DB
D Flip-Flop, FCT Series, 1-Func, Positive Edge Triggered, 4-Bit, True Output, CMOS, CDIP16, 0.300 INCH, CERDIP-16
IDT
©2020 ICPDF网 联系我们和版权申明