IDT54FCT543ATLB8 [IDT]
Registered Bus Transceiver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, CQCC28, LCC-28;
| 型号： | IDT54FCT543ATLB8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Registered Bus Transceiver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, CQCC28, LCC-28 输出元件 逻辑集成电路 |
| 文件： | 总7页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST CMOS
IDT54/74FCT543T/AT/CT/DT
OCTAL LATCHED
TRANSCEIVER
FEATURES:
DESCRIPTION:
• Std., A, C, and D grades
TheFCT543Tisanon-invertingoctaltransceiverbuiltusinganadvanced
dualmetalCMOStechnology. ThisdevicecontainstwosetsofeightD-type
latches with separate input and output controls for each set. For data flow
fromAtoB,forexample,theA-to-BEnable(CEAB)inputmustbelowinorder
to enter data from A0–A7 or to take data from B0–B7, as indicated in the
Function Table. With CEAB low, a low signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a subsequent low-to-
hightransitionoftheLEABsignalputstheAlatchesinthestoragemodeand
theiroutputsnolongerchangewiththeAinputs. WithCEABandOEABboth
low,the3-stateBoutputbuffersareactiveandreflectthedatapresentatthe
output of the A latches. Control of data from B to A is similar, but uses the
CEBA, LEBA and OEBA inputs.
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility:
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High Drive outputs (-15mA IOH, 64mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
• Power off disable outputs permit "live insertion"
• Available in the following packages:
– Industrial: SOIC, SSOP, QSOP
– Military: CERDIP, LCC
FUNCTIONALBLOCKDIAGRAM
DETAIL A
D
Q
0
B
LE
Q
D
A0
LE
1
2
3
4
5
6
7
1
2
3
4
5
A
A
A
A
A
A
A
B
B
B
B
B
DETAIL A x 7
6
7
B
B
OEBA
OEAB
CEBA
LEBA
CEAB
LEAB
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
JUNE 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-5489/2
IDT54/74FCT543T/AT/CT/DT
FASTCMOSOCTALLATCHEDTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
PINCONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
1
LEBA
OEBA
A0
VCC
CEBA
B0
INDEX
2
3
4
28 27 26
4
3
2
1
5
6
7
8
B1
B2
B3
NC
B4
B5
B6
25
24
23
22
21
20
19
A1
A1
B1
A2
A3
NC
A4
A5
A6
A2
B2
5
6
7
8
9
B3
A3
A4
A5
B4
B5
B6
B7
9
10
A6
A7
11
12 13 14 15 16 17 18
10
11
LEAB
OEAB
CEAB
GND
12
LCC
TOP VIEW
CERDIP/ SOIC/ SSOP/ QSOP
TOP VIEW
ABSOLUTEMAXIMUMRATINGS(1)
PINDESCRIPTION
Pin Names
Description
Symbol
Description
Max
Unit
V
(2)
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A0–A7
B0–B7
A-to-BOutputEnableInput(ActiveLOW)
B-to-AOutputEnableInput(ActiveLOW)
A-to-B Enable Input (Active LOW)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +7
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
°C
mA
B-to-A Enable Input (Active LOW)
A-to-BLatchEnableInput(ActiveLOW)
B-to-ALatchEnableInput(ActiveLOW)
A-to-BDataInputsorB-to-A3-StateOutputs
B-to-ADataInputsorA-to-B3-StateOutputs
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
Typ.
Max. Unit
CIN
VIN = 0V
6
8
10
12
pF
pF
COUT
VOUT = 0V
NOTE:
1. This parameter is measured at characterization but not tested.
2
IDT54/74FCT543T/AT/CT/DT
MILITARYANDINDUSTRIALTEMPERATURERANGES
FASTCMOSOCTALLATCHEDTRANSCEIVER
FUNCTION TABLE(1, 2)
ForA-to-B(SymmetricwithB-to-A)
Latch
Output
Buffers
Inputs
Status
A-to-B
Storing
Storing
X
CEAB
LEAB
OEAB
B0–B7
High Z
H
X
X
L
X
H
X
L
X
X
H
L
X
High Z
Transparent
Storing
CurrentAInputs
Previous* A Inputs
L
H
L
NOTES:
1. * Before LEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA
and OEBA.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%; Military: TA = –55°C to +125°C, VCC = 5.0V ±10%
Symbol
VIH
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2
Typ.(2)
—
Max.
—
Unit
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
VCC = Max.
—
—
—
—
—
—
—
—
—
—
0.8
±1
±1
±1
±1
±1
–1.2
—
V
IIH
Input HIGH Current(4)
Input LOW Current(4)
High Impedance Output Current
(3-State output pins)(4)
Input HIGH Current(4)
ClampDiodeVoltage
Input Hysteresis
VI = 2.7V
VI = 0.5V
VO = 2.7V
VO = 0.5V
—
µA
µA
µA
IIL
VCC = Max.
—
IOZH
IOZL
VCC = Max
—
—
II
VCC = Max., VI = VCC (Max.)
VCC = Min, IIN = -18mA
—
µA
V
VIK
VH
ICC
–0.7
200
0.01
—
mV
mA
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
1
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min
VIN = VIH or VIL
IOH = –6mA MIL
IOH = –8mA IND
IOH = –12mA MIL
IOH = –15mA IND
IOL = 48mA MIL
IOL = 64mA IND
2.4
3.3
—
V
2
3
—
VOL
Output LOWVoltage
VCC = Min
—
0.3
0.55
V
VIN = VIH or VIL
VCC = Max., VO = GND(3)
IOS
Short Circuit Current
Input/Output Power Off Leakage(5)
–60
—
–120
—
–225
mA
µA
IOFF
VCC = 0V, VIN or VO ≤ 4.5V
±1
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
3
IDT54/74FCT543T/AT/CT/DT
FASTCMOSOCTALLATCHEDTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
—
0.5
2
mA
ICCD
Dynamic Power Supply
Current(4)
VCC = Max., Outputs Open
CEAB and OEAB = GND
CEBA = VCC
VIN = VCC
VIN = GND
—
0.15
0.25
mA/
MHz
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max., Outputs Open
fCP = 10MHz (LEAB )
50% Duty Cycle
CEAB and OEAB = GND
CEBA = VCC
One Bit Toggling
VIN = VCC
VIN = GND
—
—
—
—
1.5
2
3.5
5.5
mA
mA
VIN = 3.4V
VIN = GND
at fi = 5MHz
50% duty cycle
VCC = Max., Outputs Open
fCP = 10MHz (LEAB )
50% Duty Cycle
CEAB and OEAB = GND
CEBA = VCC
VIN = VCC
VIN = GND
3.8
6
7.3(5)
16.3(5)
VIN = 3.4V
VIN = GND
Eight Bits Toggling
at fi = 2.5MHz
50% duty cycle
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of ∆ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2+ fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Output Frequency
Ni = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.
4
IDT54/74FCT543T/AT/CT/DT
MILITARYANDINDUSTRIALTEMPERATURERANGES
FASTCMOSOCTALLATCHEDTRANSCEIVER
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE-INDUSTRIAL
74FCT543AT
74FCT543CT
74FCT543DT
(2)
(2)
(2)
Symbol Parameter
Condition(1)
CL = 50pF
RL = 500Ω
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tPLH
tPHL
PropagationDelay
1.5
6.5
1.5
5.3
1.5
4.4
ns
TransparantMode
Ax to Bx or Bx to Ax
tPLH
tPHL
tPZH
tPZL
PropagationDelay
1.5
1.5
8
9
1.5
1.5
7
8
1.5
1.5
5
ns
ns
LEBA to Ax, LEAB to Bx
OutputEnableTime
5.4
OEBA or OEAB to Ax or Bx
CEBA or CEAB to Ax or Bx
OutputDisableTime
tPHZ
tPLZ
1.5
7.5
1.5
6.5
1.5
4.3
ns
OEBA or OEAB to Ax or Bx
CEBA or CEAB to Ax or Bx
Set-up Time, HIGH or LOW
Ax or Bx to LEBA or LEAB
Hold Time, HIGH or LOW
Ax or Bx to LEBA or LEAB
LEBA or LEAB Pulse Width LOW
tSU
tH
2
2
5
—
—
—
2
2
5
—
—
—
1.5
1.5
3(3)
—
—
—
ns
ns
ns
tW
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE-MILITARY
54FCT543T
54FCT543AT
54FCT543CT
(2)
(2)
(2)
Symbol Parameter
Condition(1)
CL = 50pF
RL = 500Ω
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tPLH
tPHL
PropagationDelay
1.5
10
1.5
7.5
1.5
6.1
ns
TransparantMode
Ax to Bx or Bx to Ax
tPLH
tPHL
tPZH
tPZL
PropagationDelay
1.5
1.5
14
14
1.5
1.5
9
1.5
1.5
8
9
ns
ns
LEBA to Ax, LEAB to Bx
OutputEnableTime
10
OEBA or OEAB to Ax or Bx
CEBA or CEAB to Ax or Bx
OutputDisableTime
tPHZ
tPLZ
1.5
13
1.5
8.5
1.5
7.5
ns
OEBA or OEAB to Ax or Bx
CEBA or CEAB to Ax or Bx
Set-up Time, HIGH or LOW
Ax or Bx to LEBA or LEAB
Hold Time, HIGH or LOW
Ax or Bx to LEBA or LEAB
LEBA or LEAB Pulse Width LOW
tSU
tH
3
2
5
—
—
—
2
2
5
—
—
—
2
2
5
—
—
—
ns
ns
ns
tW
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
5
IDT54/74FCT543T/AT/CT/DT
FASTCMOSOCTALLATCHEDTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
TESTCIRCUITSANDWAVEFORMS
VCC
SWITCHPOSITION
7.0V
Test
Switch
Closed
Open
500Ω
Open Drain
Disable Low
Enable Low
VOUT
VIN
Pulse
Generator
D.U.T
.
All Other Tests
50pF
500Ω
T
R
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
L
C
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal link
Test Circuits for All Outputs
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
tW
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
Octal link
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
Pulse Width
Octal link
Set-Up, Hold, and Release Times
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
VOH
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
Octal link
0V
Octal link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT54/74FCT543T/AT/CT/DT
MILITARYANDINDUSTRIALTEMPERATURERANGES
FASTCMOSOCTALLATCHEDTRANSCEIVER
ORDERINGINFORMATION
XXXX
XX
X
IDT
XX
FCT
Package
Process
Device Type
Temp. Range
Blank
Industrial
B
MIL-STD-883, Class B
Industrial Options
SO
PY
Q
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package
Military Options
CERDIP
Leadless Chip Carrier
D
L
Fast CMOS Octal Latched Transceiver
543T
543AT
543CT
543DT
54
74
– 55°C to +125°C
– 40°C to +85°C
DATASHEETDOCUMENTHISTORY
6/24/2002 Updated as per PDNs Logic-00-07 and Logic-01-04
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
logichelp@idt.com
(408) 654-6459
www.idt.com
7
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