IDT54FCT646ASO [IDT]

FAST CMOS OCTAL TRANSCEIVER/REGISTER; 快速CMOS八路收发器/寄存器


型号：	IDT54FCT646ASO
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	FAST CMOS OCTAL TRANSCEIVER/REGISTER 快速CMOS八路收发器/寄存器
文件：	总8页 (文件大小：95K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT54/74FCT646

IDT54/74FCT646A

IDT54/74FCT646C

FAST CMOS OCTAL

TRANSCEIVER/REGISTER

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• IDT54/74FCT646 equivalent to FAST speed;

• IDT54/74FCT646A 30% faster than FAST

• IDT54/74FCT646C 40% faster than FAST

• Independent registers for A and B buses

• Multiplexed real-time and stored data

• IOL = 64mA (commercial) and 48mA (military)

• CMOS power levels (1mW typical static)

• TTL input and output level compatible

• CMOS output level compatible

• Available in 24-pin (300 mil) CERDIP, plastic DIP, SOIC,

CERPACK and 28-pin LCC

• Product available in Radiation Tolerant and Radiation

Enhanced Versions

The IDT54/74FCT646/A/C consists of a bus transceiver

with 3-state D-type flip-flops and control circuitry arranged for

multiplexed transmission of data directly from the data bus or

from the internal storage registers.

The IDT54/74FCT646/A/C utilizes the enable control (G)

and direction (DIR) pins to control the transceiver functions.

SAB and SBA control pins are provided to select either real

time or stored data transfer. The circuitry used for select

control will eliminate the typical decoding glitch that occurs in

a multiplexer during the transition between stored and real-

time data. A LOW input level selects real-time data and a

HIGH selects stored data.

Data on the A or B data bus or both can be stored in the

internal D flip flops by LOW-to-HIGH transitions at the

appropriate clock pins (CPAB or CPBA) regardless of the

select or enable control pins.

• Military product compliant to MIL-STD-883, Class B

FUNCTIONAL BLOCK DIAGRAM

DIR

CPBA

SBA

CPAB

SAB

1 OF 8 CHANNELS

B REG

A REG

2536 drw 01

TO 7 OTHER CHANNELS

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FAST is a registered trademark of National Semiconductor Co.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MAY 1992

1992 Integrated Device Technology, Inc.

7.18

DSC-4626/2

IDT54/74FCT646/A/C

FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

INDEX

CPAB

SAB

DIR

Vcc

CPBA

SBA

28 27 26

P24-1, 21

D24-1,

S024-2

B₄

L28-1

E24-1

12 13 14 15 16 17 18

GND

2536 drw 02

DIP/SOIC/CERPACK

TOP VIEW

LCC

TOP VIEW

PIN DESCRIPTION

LOGIC SYMBOL

Pin Names

Description

A1–A8

B1–B8

Data Register A Inputs

Data Register B Outputs

CPAB

SAB

DIR

A1 A2 A3 A4 A5 A6 A7 A8

Data Register B Inputs

Data Register A Outputs

CPBA

SBA

CPAB, CPBA

SAB, SBA

DIR, G

Clock Pulse Inputs

Output Data Source Select Inputs

Output Enable Inputs

B1 B2 B3 B4 B5 B6 B7 B8

2536 tbl 01

2536 drw 06

FUNCTION TABLE⁽²⁾

(1)

Inputs

Data I/O

A1–A8

Operation or Function

IDT54/74FCT646

DIR

CPAB

CPBA

SAB

SBA

B1–B8

H or L

↑

H or L

↑

Input

Output

Input

Isolation

Store A and B Data

Input

Real-Time B Data to A Bus

Stored B Data to A Bus

H or L

Output

Real-Time A Data to B Bus

Stored A Data to B Bus

H or L

NOTES:

2536 tbl 02

1. The data output functions may be enabled or disabled by various signals at the G or DIR inputs. Data input functions are always enabled, i.e., data at

the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.

2. H = HIGH, L = LOW, X = Don’t Care, ↑ = LOW-to-HIGH Transition.

7.18

IDT54/74FCT646/A/C

FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

BUS

DIR

CPAB CPBA SAB

SBA

DIR

CPAB CPBA SAB

SBA

2536 drw 03

REAL–TIME TRANSFER

BUS A TO BUS B

REAL–TIME TRANSFER

BUS B TO BUS A

BUS

DIR⁽¹⁾

CPAB CPBA SAB

SBA

DIR

CPAB CPBA SAB

SBA

H or L

2536 drw 04

TRANSFER STORED

DATA TO A AND/OR B

STORAGE FROM

A AND/OR B

NOTE:

1. Cannot transfer data to A bus and B bus simultaneously.

7.18

IDT54/74FCT646/A/C

FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions Typ. Max. Unit

Symbol

Rating

Commercial

Military

Unit

(2)

VTERM

Terminal Voltage

with Respect

to GND

–0.5 to +7.0 –0.5 to +7.0

CIN

VIN = 0V

CI/O

VOUT = 0V

(3)

NOTE:

2536 tbl 04

VTERM

Terminal Voltage

with Respect

to GND

–0.5 to VCC –0.5 to VCC

1. This parameter is measured at characterization but not tested.

Operating

0 to +70

–55 to +125 °C

Temperature

TBIAS

TSTG

Temperature

Under Bias

–55 to +125 –65 to +135 °C

–55 to +125 –65 to +150 °C

Storage

Temperature

Power Dissipation

DC Output Current

0.5

IOUT

120

NOTES:

2536 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability. No terminal voltage

may exceed VCC by +0.5V unless otherwise noted.

2. Inputs and VCC terminals only.

3. Outputs and I/O terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V

Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%

Symbol

VIH

Parameter

Input HIGH Level

Input LOW Level

Input HIGH Current

(Except I/O pins)

Input LOW Current

(Except I/O pins)

Input HIGH Current

(I/O pins only)

Test Conditions⁽¹⁾

Min.

2.0

—

Typ.⁽²⁾

Max.

—

Unit

Guaranteed Logic HIGH Level

—

VIL

Guaranteed Logic LOW Level

VCC = Max.

—

0.8

IIH

VI = VCC

VI = 2.7V

VI = 0.5V

VI = GND

VI = VCC

VI = 2.7V

VI = 0.5V

VI = GND

—

µA

—

5⁽⁴⁾

–5⁽⁴⁾

–5

IIL

IIH

IIL

—

VCC = Max.

—

µA

—

15⁽⁴⁾

–15⁽⁴⁾

–15

–1.2

—

Input LOW Current

(I/O pins only)

—

VIK

IOS

Clamp Diode Voltage

Short Circuit Current

Output HIGH Voltage

VCC = Min., IN = –18mA

VCC = Max.⁽³⁾, VO = GND

—

–0.7

–120

VCC

4.0

GND

0.3

–60

VHC

2.4

—

VOH

VCC = 3V, VIN = VLC or VHC, IOH = –32µA

—

VCC = Min.

IOH = –300µA

—

VIN = VIH or VIL

IOH = –12mA MIL.

—

IOH = –15mA COM’L.

—

VOL

Output LOW Voltage

VCC = 3V, VIN = VLC or VHC, IOL = 300µA

VLC

(4)

VCC = Min.

IOL = 300µA

—

VLC

VIN = VIH or VIL

IOL = 48mA MIL.

IOL = 64mA COM’L.

—

0.55

—

NOTES:

2536 tbl 05

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.

3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

4. This parameter is guaranteed but not tested.

7.18

IDT54/74FCT646/A/C

FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

VLC = 0.2V; VHC = VCC – 0.2V

Symbol

Parameter

Test Conditions⁽¹⁾

VCC = Max.

Min.

Typ.⁽²⁾

Max.

Unit

ICC

Quiescent Power Supply Current

—

0.2

1.5

VIN ≥ VHC; VIN ≤ VLC

∆ICC

Quiescent Power Supply Current

TTL Inputs HIGH

Dynamic Power Supply Current⁽⁴⁾

VCC = Max.

VIN = 3.4V⁽³⁾

—

0.5

2.0

ICCD

VCC = Max.

VIN ≥ VHC

VIN ≤ VLC

0.15

0.25

mA/MHz

Outputs Open

G = DIR = GND

One Input Toggling

50% Duty Cycle

Total Power Supply Current⁽⁶⁾

VCC = Max.

Outputs Open

fCP = 10MHz

50% Duty Cycle

G = DIR = GND

One Bit Toggling

at fi = 5MHz

VIN ≥ VHC

VIN ≤ VLC

(FCT)

—

1.7

2.2

4.0

6.0

VIN = 3.4V

VIN = GND

50% Duty Cycle

VCC = Max.

Outputs Open

fCP = 10MHz

50% Duty Cycle

G = DIR = GND

Eight Bits Toggling

at fi = 5MHz

VIN ≥ VHC

VIN ≤ VLC

(FCT)

—

7.0

9.2

12.8⁽⁵⁾

21.8⁽⁵⁾

VIN = 3.4V

VIN = GND

50% Duty Cycle

NOTES:

2536 tbl 06

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at VCC = 5.0V, +25°C ambient.

3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.

6. IC = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)

ICC = Quiescent Current

∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)

DH = Duty Cycle for TTL Inputs High

NT = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)

fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

fi = Input Frequency

Ni = Number of Inputs at fi

All currents are in milliamps and all frequencies are in megahertz.

7.18

IDT54/74FCT646/A/C

FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

54/74FCT646

54/74FCT646A

54/74FCT646C

Com’l. Mil.

Com’l.

Mil.

(2)

Max. Min.

(2)

Symbol

Parameter

Condition⁽¹⁾Min.

Max. Min.

Max. Unit

tPLH

tPHL

Propagation

Delay

Bus to Bus

CL = 50 pF

RL = 500Ω

2.0

9.0

2.0 11.0 2.0

6.3

9.8

6.3

7.7

—

2.0

7.7 1.5

5.4

7.8

6.3

5.7

6.2

—

1.5

6.0

8.9

7.7

6.3

7.0

—

tPZH

tPZL

Output Enable

Time G, DIR to

Bus

2.0 14.0 2.0 15.0 2.0

2.0 10.5 1.5

1.5

tPHZ

tPLZ

Output Disable

Time G, DIR to

Bus

2.0

9.0

2.0 11.0 2.0

2.0 10.0 2.0

2.0

1.5

5.0

7.7

7.0

8.4

—

1.5

2.0

1.5

5.0

1.5

2.0

1.5

5.0

tPLH

tPHL

Propagation

Delay Clock

to Bus

tPLH

tPHL

Propagation

Delay SBA or

SAB to Bus

2.0 11.0 2.0 12.0 2.0

tSU

Set-up Time

HIGH or LOW

Bus to Clock

4.0

2.0

6.0

—

4.5

2.0

6.0

—

2.0

1.5

5.0

Hold Time

HIGH or LOW

Bus to Clock

—

Clock Pulse

Width HIGH or

LOW

—

NOTES:

2536 tbl 07

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

7.18

IDT54/74FCT646/A/C

FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS

VCC

SWITCH POSITION

Test

Switch

Closed

Open

7.0V

Open Drain

Disable Low

Enable Low

500Ω

V OUT

VIN

Pulse

Generator

D.U.T.

All Other Tests

50pF

C L

500Ω

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

2536 tbl 08

RT = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

SET-UP, HOLD AND RELEASE TIMES

PULSE WIDTH

1.5V

DATA

INPUT

t_SU

t _H

LOW-HIGH-LOW

1.5V

TIMING

INPUT

PULSE

t _W

ASYNCHRONOUS CONTROL

t _REM

PRESET

CLEAR

ETC.

1.5V

HIGH-LOW-HIGH

PULSE

1.5V

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

ETC.

1.5V

t SU

PROPAGATION DELAY

ENABLE AND DISABLE TIMES

ENABLE

DISABLE

CONTROL

INPUT

1.5V

SAME PHASE

INPUT TRANSITION

1.5V

t_PZL

t_PLZ

t_PHL

t_PLH

3.5V

1.5V

3.5V

OUTPUT

NORMALLY

LOW

V_OH

SWITCH

CLOSED

OUTPUT

1.5V

0.3V

V_OL

V_OH

t_PZH

t_PHZ

V_OL

t_PLH

t_PHL

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

1.5V

OPPOSITE PHASE

INPUT TRANSITION

1.5V

NOTES

2536 drw 07

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;

tR ≤ 2.5ns.

7.18

IDT54/74FCT646/A/C

FAST CMOS OCTAL TRANSCEIVER/REGISTER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

IDT

FCT XXXX

Temperature

Range

Device

Type

Package

Process/

Temperature

Range

Blank

Commercial

MIL-STD-883, Class B

Plastic DIP

CERDIP

Small Outline IC

Leadless Chip Carrier

CERPACK

646

646A

646C

Non-inverting Octal Transceiver/Register

Fast Non-inverting Octal Transceiver/Register

Super Fast Non-inverting Octal Transceiver/Register

–55°C to +125°C

0°C to +70°C

2536 drw 05

7.18

IDT54FCT646ASO [IDT]

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