IDT54FCT646DTLB [IDT]
FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE); 快速CMOS八路收发器/寄存器（三态）
| 型号： | IDT54FCT646DTLB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE) |
| 文件： | 总9页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT646T/AT/CT/DT - 2646T/AT/CT
IDT54/74FCT648T/AT/CT
IDT54/74FCT652T/AT/CT/DT - 2652T/AT/CT
FAST CMOS OCTAL
TRANSCEIVER/
REGISTERS (3-STATE)
Integrated Device Technology, Inc.
FEATURES:
• Common features:
– Low input and output leakage ≤1µA (max.)
– Extended commercial range of –40°C to +85°C
– CMOS power levels
– True TTL input and output compatibility
– VOH = 3.3V (typ.)
DESCRIPTION:
TheFCT646T/FCT2646T/FCT648T/FCT652T/2652Tcon-
sist of a bus transceiver with 3-state D-type flip-flops and
control circuitry arranged for multiplexed transmission of data
directly from the data bus or from the internal storage regis-
ters.
The FCT652T/FCT2652T utilize GAB and GBA signals to
control the transceiver functions. The FCT646T/FCT2646T/
FCT648T utilize the enable control (G) and direction (DIR)
pins to control the transceiver functions.
SABandSBAcontrolpinsareprovidedtoselecteitherreal-
time or stored data transfer. The circuitry used for select
control will eliminate the typical decoding glitch that occurs in
a multiplexer during the transition between stored and real-
time data. A LOW input level selects real-time data and a
HIGH selects stored data.
Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by LOW-to-HIGH transitions at the appro-
priate clock pins (CPAB or CPBA), regardless of the select or
enable control pins.
– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, TSSOP,
CERPACK and LCC packages
• Features for FCT646T/648T/652T:
– Std., A, C and D speed grades
– High drive outputs (-15mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
• Features for FCT2646T/2652T:
The FCT26xxT have balanced drive outputs with current
limiting resistors. This offers low ground bounce, minimal
undershoot and controlled output fall times-reducing the need
for external series terminating resistors. FCT2xxxT parts are
plug-in replacements for FCTxxxT parts.
– Std., A, and C speed grades
– Resistor outputs (-15mA IOH, 12mA IOL Com.)
(-12mA IOH, 12mA IOL Mil.)
– Reduced system switching noise
FUNCTIONAL BLOCK DIAGRAM
IDT54/74FCT652/2652
ONLY
GAB
GBA
IDT54/74FCT646/2646/648
ONLY
G
DIR
CPBA
SBA
CPAB
SAB
B REG
646/2646/652/2652
1 OF 8 CHANNELS
1D
C1
ONLY
A REG
1D
B1
A1
C1
2634 drw 01
646/2646/652/2652
ONLY
TO 7 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEPTEMBER 1996
1996 Integrated Device Technology, Inc.
6.20
DSC-2634/9
1
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
1
2
3
4
5
6
7
8
9
10
VCC
CPBA
SBA
G
CPAB
SAB
DIR
A1
24
23
22
21
20
19
18
17
16
4
3
2
28 27 26
FCT646/FCT2646T
FCT648
1
5
A1
G
25
P24-1
D24-1
B1
B2
24
23
6
7
8
9
A2
A3
A2
A3
A4
A5
A6
A7
B1
SO24-2
SO24-7*
SO24-8
SO24-9*
&
B2
B3
B4
B5
B6
L28-1
NC
A4
NC
B3
22
21
20
19
A5
10
11
B4
B5
A6
15
12 13 14
16 17 18
E24-1
15
14
13
A8
GND
B7
B8
11
12
2634 drw 03
2634 drw 02
LCC
TOP VIEW
DIP/SOIC/SSOP/
QSOP/TSSOP/CERPACK
TOP VIEW
* FCT646/2646T/AT/CT/DT only
INDEX
1
2
3
4
5
6
7
8
9
10
VCC
CPAB
SAB
GAB
A1
24
23
22
21
20
19
18
17
16
CPBA
SBA
GBA
B1
FCT652/FCT2652T
P24-1
D24-1
SO24-2
SO24-7*
SO24-8
&
4
3
2
28 27 26
1
5
A1
GBA
B1
25
24
23
22
21
20
19
A2
A3
A4
A5
A6
A7
6
7
8
9
A2
A3
B2
B3
B4
B5
B6
B2
L28-1
NC
A4
NC
B3
E24-1
A5
10
11
B4
B5
15
14
13
A6
A8
GND
B7
B8
15
11
12
1213 14
16 17 18
2634 drw 05
2634 drw 04
DIP/SOIC/SSOP/
QSOP/CERPACK
TOP VIEW
LCC
TOP VIEW
* FCT652/2652T/AT/CT/DT only
PIN DESCRIPTION
Pin Names
Description
Data Register A Inputs
Data Register B Outputs
A
B
1
- A
- B
8
1
8
Data Register B Inputs
Data Register A Outputs
CPAB, CPBA
SAB, SBA
Clock Pulse Inputs
Output Data Source Select Inputs
Output Enable Inputs (646/648)
Output Enable Inputs (652)
DIR, G
GAB, GBA
2634 tbl 01
6.20
2
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Operation or Function
FUNCTION TABLE (646/648)
Inputs
Data I/O(1)
DIR CPAB CPBA SAB SBA
A1 - A8
B1 - B8
FCT646T/FCT2646T
Isolation
Store A and B Data
Real-Time B Data to A Bus Real-Time B Data to A Bus
Stored B Data to A Bus Stored B Data to A Bus
Real-Time A Data to B Bus Real-Time A Data to B Bus
Stored A Data to B Bus Stored A Data to B Bus
FCT648T
G
H
H
X
X
H or L H or L
X
X
X
X
Input
Output
Input
Input
Isolation
Store A and B Data
↑
↑
L
L
L
L
L
L
X
X
X
H or L
X
X
X
L
L
H
X
X
Input
H
H
X
Output
H or L
X
H
2634 tbl 02
FUNCTION TABLE (652)
Inputs
Data I/O
Operation or Function
FCT652T/FCT2652T
GAB
CPAB CPBA SAB SBA
A1 - A8
B1 - B8
GBA
L
L
H
H
H or L H or L
X
X
X
X
Input
Input
Isolation
Store A and B Data
Unspecified(1) Store A, Hold B
↑
↑
↑
↑
X
H
H
H
H or L
↑
X
X(2)
X
X
Input
Input
Output
Store A in Both Registers
L
L
X
L
H or L
↑
↑
↑
X
X
X
X(2)
Unspecified(1)
Output
Input
Input
Hold A, Store B
Store B in Both Registers
L
L
L
L
X
X
X
H or L
X
X
X
L
H
H
L
H
X
X
H
Output
Input
Real-Time B Data to A Bus
Stored B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
H
H
H
H
L
X
Input
Output
Output
H or L
X
H
H or L H or L
Output
Stored A Data to B Bus and Stored B Data to A Bus
NOTES:
2634 tbl 03
1. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data
inputfunctionsarealwaysenabled,i.e.dataatthebuspinswillbestoredoneveryLOW-to-HIGHtransition
on the clock inputs.
2. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.
H = HIGH, L = LOW, X = Don't Care, ≠ = LOW-to-HIGH transition.
3. A in B Register.
4. B in A Register.
6.20
3
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUS
A
BUS
B
BUS
A
BUS
B
GAB GBA
CPAB
X
CPAB
X
CPBA
X
CPBA
X
SAB SBA
GAB GBA
CPAB
X
CPBA
X
SAB SBA
652/2652
652/2652
L
L
G
L
X
L
H
H
L
X
646/2646/ DIR
648
SAB SBA
DIR
H
G
L
CPAB
X
CPBA
X
SAB SBA
646/2646/
648
L
X
L
L
X
REAL-TIME TRANSFER
BUS B TO A
REAL-TIME TRANSFER
BUS A TO B
2634 drw 06
2634 drw 07
BUS
A
BUS
A
BUS
B
BUS
B
652/2652 GAB GBA
CPAB
H or
CPBA
H or
SAB SBA
652/2652 GAB GBA
CPAB
CPBA
X
SAB SBA
H
L
H
H
X
L
L
H
X
H
X
X
X
X
X
X
↑
X
(1)
↑
↑
646/2646/
648
DIR
L
G
L
CPAB
X
H or
CPBA
H or
X
SAB SBA
↑
X
H
H
X
H
L
646/2646/ DIR
G
L
CPAB
CPBA
X
SAB SBA
648
H
L
X
X
X
X
X
X
↑
X
TRANSFER STORES
DATA TO A AND/OR B
L
↑
↑
X
H
↑
2634 drw 09
NOTE:
1. 646/2646/648 cannot transfer data to A bus and B bus simultaneously.
STORAGE FROM
A AND/OR B
2634 drw 08
6.20
4
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
Symbol
Description
Max.
Unit
CIN
Input
Capacitance
Output
VIN = 0V
6
8
10
pF
(2)
VTERM
Terminal Voltage with Respect to –0.5 to +7.0
GND
V
COUT
VOUT = 0V
12
pF
(3)
VTERM
Terminal Voltage with Respect to
GND
–0.5 to
CC +0.5
V
Capacitance
V
2634 lnk 05
NOTE:
T
STG
OUT
NOTES:
Storage Temperature
–65 to +150
°C
1. This parameter is measured at characterization but not tested.
I
DC Output Current
–60 to +120 mA
2634 lnk 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
—
—
—
—
—
—
—
—
0.8
±1
±1
±1
±1
±1
–1.2
—
V
VIL
II H
II L
Input LOW Level
Guaranteed Logic LOW Level
V
Input HIGH Current(4)
Input LOW Current(4)
High Impedance Output Current
(3-State Output pins)(4)
Input HIGH Current(4)
Clamp Diode Voltage
Input Hysteresis
VCC = Max.
VCC = Max.
VI = 2.7V
VI = 0.5V
VO = 2.7V
VO = 0.5V
—
µA
—
IOZH
IOZL
II
—
µA
—
VCC = Max., VI = VCC (Max.)
VCC = Min., IIN = –18mA
—
—
µA
V
VIK
VH
ICC
–0.7
200
0.01
mV
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
1
mA
2634 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT646T/648T/652T
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VOH
Output HIGH Voltage
VCC = Min.
VIN = VIH or VIL
IOH = –6mA MIL.
2.4
2.0
—
3.3
3.0
0.3
—
V
IOH = –8mA COM'L.
IOH = –12mA MIL.
IOH = –15mA COM'L.
IOL = 48mA MIL.
—
V
V
VOL
Output LOW Voltage
Short Circuit Current
VCC = Min.
VIN = VIH or VIL
VCC = Max., VO = GND(3)
0.55
IOL = 64mA COM'L.
IOS
–60
—
–120 –225
±1
mA
IOFF
Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤ 4.5V
—
µA
2634 lnk 06
6.20
5
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OUTPUT DRIVE CHARACTERISTICS FOR FCT2646T/2652T
Symbol
Parameter
Test Conditions(1)
VCC = 5V, VIN = VIH or VIL, VOUT= 1.5V(3)
VCC = 5V, VIN = VIH or VIL, VOUT= 1.5V(3)
Min. Typ.(2) Max.
Unit
IODL
Output LOW Current
16
–16
2.4
48
–48
3.3
—
—
—
mA
IODH
VOH
Output HIGH Current
Output HIGH Voltage
mA
V
VCC = Min.
IOH = –12mA MIL.
IOH = –15mA COM'L.
IOL = 12mA
VIN = VIH or VIL
VCC = Min.
VOL
Output LOW Voltage
—
0.3
0.50
V
VIN = VIH or VIL
2634 lnk 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Test Conditions(1)
Min. Typ.(2) Max.
Unit
∆ICC
VCC = Max.
VIN = 3.4V(3)
—
0.5
2.0
mA
ICCD
Dynamic Power Supply Current(4) VCC = Max.
VIN = VCC FCTxxxT
VIN = GND
—
0.15
0.25
mA/
MHz
Outputs Open
GAB = GBA = GND or
G = DIR = GND
One Input Toggling
50% Duty Cycle
VCC = Max.
Outputs Open
fCP = 10MHz
FCT2xxxT
—
0.06
0.12
IC
Total Power Supply Current(6)
VIN = VCC FCTxxxT
VIN = GND
—
—
—
1.5
0.6
2.0
1.1
3.5
2.2
5.5
4.2
mA
FCT2xxxT
50% Duty Cycle
GAB = GBA = GND or VIN = 3.4
FCTxxxT
G = DIR = GND
One Bit Toggling
at fi = 5MHz
VIN = GND
FCT2xxxT
50% Duty Cycle
VCC = Max.
Outputs Open
fCP = 10MHz
VIN = VCC FCTxxxT
VIN = GND
—
—
—
—
3.8
1.5
6.0
3.8
7.3(5)
4.0(5)
FCT2xxxT
50% Duty Cycle
GAB = GBA = GND or VIN = 3.4
FCTxxxT
16.3(5)
13.0(5)
G = DIR = GND
Eight Bits Toggling
at fi = 2.5MHz
VIN = GND
FCT2xxxT
50% Duty Cycle
2634 tbl 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.20
6
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
646/648/652T
2646/2652T
646/648/652AT
2646/2652AT
Com'l.
Mil.
Com'l.
Mil.
(2)
(2)
Min.
(2)
(2)
Min.
Condition(1)
CL = 50pF
RL = 500Ω
Unit
Min.
Max.
Max.
Min.
Max.
Max.
Symbol
tPLH
tPHL
Parameter
Propagation Delay
Bus to Bus
2.0
9.0
14.0
9.0
9.0
11.0
—
2.0
11.0
2.0
6.3
2.0
7.7
ns
tPZH
Output Enable Time, G,
DIR to Bus(3)
2.0
2.0
2.0
2.0
4.0
2.0
6.0
2.0
2.0
2.0
2.0
4.5
2.0
6.0
15.0
11.0
10.0
12.0
—
2.0
2.0
2.0
2.0
2.0
1.5
5.0
9.8
6.3
6.3
7.7
—
2.0
2.0
2.0
2.0
2.0
1.5
5.0
10.5
7.7
7.0
8.4
—
ns
ns
ns
ns
ns
ns
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tSU
Output Disable Time, G,
DIR to Bus(3)
Propagation Delay
Clock to Bus
Propagation Delay SBA or
SAB to Bus
Set-up Time HIGH or LOW
Bus to Clock
tH
Hold Time HIGH or LOW
Bus to Clock
—
—
—
—
tW
Clock Pulse Width,
HIGH or LOW
—
—
—
—
ns
2634 tbl 09
646/648/652CT
2646/2652CT
646/652DT
Com'l. Mil.
Com'l.
Mil.
(2)
Min.
(2)
Min.
(2)
(2)
Min.
Condition(1)
CL = 50pF
RL = 500Ω
Unit
Max.
Max.
Min.
Max.
Max.
Symbol
tPLH
tPHL
Parameter
Propagation Delay
Bus to Bus
1.5
1.5
1.5
1.5
1.5
2.0
1.5
5.0
5.4
1.5
6.0
1.5
4.4
—
—
—
—
—
—
—
—
—
ns
tPZH
Output Enable Time, G,
DIR to Bus(3)
7.8
6.3
5.7
6.2
—
1.5
1.5
1.5
1.5
2.0
1.5
5.0
8.9
7.7
6.3
7.0
—
1.5
1.5
1.5
1.5
1.5
1.0
3.0
5.0
4.3
4.4
5.0
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tSU
Output Disable Time, G,
DIR to Bus(3)
Propagation Delay
Clock to Bus
Propagation Delay SBA or
SAB to Bus
Set-up Time HIGH or LOW
Bus to Clock
tH
Hold Time HIGH or LOW
Bus to Clock
—
—
—
tW
Clock Pulse Width,
HIGH or LOW(4)
—
—
—
NOTES:
1. See test circuit and waveforms.
2634 tbl 10
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. GAB, GBA to Bus for 652.
4. This parameter is guaranteed but not tested.
6.20
7
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
VCC
7.0V
Open Drain
Disable Low
Closed
500
Ω
Ω
Enable Low
VOUT
VIN
Open
All Other Tests
Pulse
Generator
D.U.T.
2634 lnk 11
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
50pF
500
T
R
C
L
Generator.
2634 drw 10
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
tH
t
t
SU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
t
W
t
REM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
2634 drw 12
3V
1.5V
0V
CLEAR
CLOCK ENABLE
ETC.
SU
t
H
2634 drw 11
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
t
PLH
t
t
PHL
PHL
t
PZL
tPLZ
VOH
OUTPUT
3.5V
1.5V
3.5V
1.5V
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
VOL
tPLH
0.3V
0.3V
VOL
3V
1.5V
0V
t
PZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
2634 drw 13
0V
2634 drw 14
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.20
8
IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT
FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
FCT
X
XXXX
Device Type
X
X
Temperature
Family
Package
Process/
Temperature
Range
Range
Blank
Commercial
B
MIL-STD-883, Class B
P
Plastic DIP (P24-1)
D
CERDIP (D24-1)
SO
L
E
Small Outline IC (SO24-2)
Leadless Chip Carrier (L28-1)
CERPACK (E24-1)
PY
Q
PG
Shrink Small Outline Package (SO24-7)
Quarter-size Small Outline Package (SO24-8)
Thin Shrink Small Outline Package (SO24-9)
Non-inverting Octal Transceiver/Register
Inverting Octal Transceiver/Register
Inverting Octal Transceiver/Register
Non-inverting Octal Transceiver/Register
646T
648T
652T
646AT
648AT
652AT
646CT
648CT
652CT
646DT
652DT
High Drive
Balanced Drive
Blank
2
54
74
–55
°
C to +125
C to +85
°C
C
–40
°
°
2634 drw 15
6.20
9
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