IDT54FCT825BTQ [IDT]
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS; 高性能CMOS总线接口寄存器
| 型号： | IDT54FCT825BTQ |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS |
| 文件： | 总9页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT821AT/BT/CT
HIGH-PERFORMANCE
CMOS BUS
INTERFACE REGISTERS
IDT54/74FCT823AT/BT/CT/DT
IDT54/74FCT825AT/BT/CT
Integrated Device Technology, Inc.
FEATURES:
• Common features:
– Low input and output leakage ≤1µA (max.)
– CMOS power levels
– True TTL input and output compatibility
– VOH = 3.3V (typ.)
DESCRIPTION:
The FCT82xT series is built using an advanced dual metal
CMOS technology. The FCT82xT series bus interface regis-
ters are designed to eliminate the extra packages required to
buffer existing registers and provide extra data width for wider
address/data paths or buses carrying parity. The FCT821T
are buffered, 10-bit wide versions of the popular FCT374T
function. The FCT823T are 9-bit wide buffered registers with
Clock Enable (EN) and Clear (CLR) – ideal for parity bus
interfacing in high-performance microprogrammed systems.
TheFCT825Tare8-bitbufferedregisterswithalltheFCT823T
controls plus multiple enables (OE1, OE2, OE3) to allow multi-
user control of the interface, e.g., CS, DMA and RD/WR. They
are ideal for use as an output port requiring high IOL/IOH.
The FCT82xT high-performance interface family can drive
large capacitive loads, while providing low-capacitance bus
loading at both inputs and outputs. All inputs have clamp
diodes and all outputs are designed for low-capacitance bus
loading in high-impedance state.
– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for FCT821T/FCT823T/FCT825T:
– A, B, C and D speed grades
– High drive outputs (-15mA IOH, 48mA IOL)
– Power off disable outputs permit “live insertion”
FUNCTIONAL BLOCK DIAGRAM
D0
DN
EN
CLR
CL
CL
D
Q
Q
D
Q
Q
CP
CP
CP
OE
Y
0
YN
2567 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1995
1995 Integrated Device Technology, Inc
6.21
DSC-4202/5
1
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
FCT821 10-BIT REGISTER
INDEX
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
VCC
Y0
Y1
Y2
Y3
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
4 3 2
282726
1
D2
D3
D4
NC
D5
D6
D7
5
6
7
8
25
Y2
Y3
Y4
NC
Y5
Y6
Y7
P24-1
D24-1
SO24-2
SO24-7
SO24-8
&
24
23
22
21
20
19
L28-1
Y4
Y5
Y6
Y7
Y8
9
10
11
1213 1415161718
E24-1
15
14
13
D9
GND
Y9
CP
11
12
2567 drw 02
LCC
TOP VIEW
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
FCT823 9-BIT REGISTER
INDEX
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
V
Y
Y
Y
Y
CC
0
OE
D0
D1
D2
D3
D4
D5
D6
4 3 2
282726
1
D
2
1
5
6
7
8
9
25
Y
Y
Y
2
3
4
P24-1
D24-1
SO24-2
SO24-7
SO24-8
&
2
D3
D4
NC
D5
24
23
22
21
20
19
3
NC
Y
Y
Y
Y
Y
4
5
6
7
8
L28-1
Y
Y
Y
5
D6
10
11
6
7
D7
D7
D
8
9
10
E24-1
1213 1415161718
15
14
13
CLR
GND
EN
CP
11
12
2567 drw 03
LCC
TOP VIEW
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
FCT825 8-BIT REGISTER
INDEX
1
2
3
24
23
22
VCC
OE1
OE2
D0
OE3
Y0
4 3 2
282726
1
D1
D2
D3
NC
D4
D5
D6
5
6
7
8
25
Y1
Y2
Y3
NC
Y4
Y5
Y6
D1
D2
4
5
P24-1 21
D24-1 20
Y1
Y2
24
23
22
21
20
19
SO24-2
SO24-8
&
D3
D4
D5
D6
19
18
17
16
Y3
6
7
8
9
L28-1
Y4
Y5
9
10
11
E24-1
Y6
1213 1415161718
D7
10
15
14
13
Y7
EN
CP
CLR
GND
11
12
2567 drw 04
LCC
TOP VIEW
DIP/SOIC/QSOP/CERPACK
TOP VIEW
6.21
2
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
FUNCTION TABLE(1)
Internal/
Outputs
Names
I/O
Description
Inputs
DI
I
The D flip-flop data inputs.
DI
CP
QI
YI
OE
CLR
EN
Function
CLR
I
When the clear input is LOW and OE is
LOW, the QI outputs are LOW. When
the clear input is HIGH, data can be
entered into the register.
H
H
H
H
L
L
L
H
↑
↑
L
H
Z
Z
High Z
H
L
L
L
X
X
H
H
L
L
L
L
X
X
X
X
L
H
L
H
X
X
X
X
↑
L
L
Z
L
Clear
Hold
Load
CP
I
Clock Pulse for the Register; enters
data into the register on the LOW-to-
HIGH transition.
H
L
H
H
H
H
H
H
NC
NC
L
Z
NC
Z
H
H
L
YI
O
I
The register 3-state outputs.
H
Z
↑
EN
Clock Enable. When the clock enable is
LOW, data on the D I input is transferred
to the QI output on the LOW-to-HIGH
clock transition. When the clock enable
is HIGH, the QI outputs do not change
state, regardless of the data or clock
input transitions.
L
L
↑
L
H
H
↑
NOTE:
1. H = HIGH
L = LOW
2567 tbl 02
X = Don’t Care
NC = No Change
↑ = LOW-to-HIGH Transition
Z = High Impedance
OE
I
Output Control. When the OE input is
HIGH, the Y I outputs are in the high-
impedance state. When the OE input is
LOW, the TRUE register data is present
at the YI outputs.
2567 tbl 01
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
Symbol
Rating
Commercial
Military
Unit
(2)
CIN
Input
Capacitance
Output
VIN = 0V
6
8
10
pF
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0
V
COUT
VOUT = 0V
12
pF
(3)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to
–0.5 to
V
Capacitance
VCC +0.5
VCC +0.5
2567 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
TA
Operating
0 to +70
–55 to +125 °C
Temperature
Temperature
Under Bias
Storage
TBIAS
TSTG
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
Temperature
Power Dissipation
PT
0.5
0.5
W
IOUT
DC Output
Current
–60 to +120 –60 to +120 mA
2567 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
6.21
3
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Parameter
Input HIGH Level
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VIH
Guaranteed Logic HIGH Level
2.0
—
—
—
—
—
—
—
—
—
—
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
0.8
V
I
I
I
I
I
I H
I L
Input HIGH Current(4)
Input LOW Current(4)
High Impedance Output Current
(3-State Output pins)(4)
Input HIGH Current(4)
Clamp Diode Voltage
Input Hysteresis
V
CC = Max.
CC = Max.
CC = Max., V
V
V
V
V
I
I
= 2.7V
= 0.5V
—
±1
±1
±1
±1
±1
µA
µA
µA
—
OZH
OZL
I
V
O
O
= 2.7V
= 0.5V
—
—
V
V
I
= VCC (Max.)
—
V
IK
H
CC = Min., IIN = –18mA
—
–0.7
200
0.01
–1.2
—
V
V
mV
I
CC
Quiescent Power Supply Current
V
CC = Max., VIN = GND or VCC
1
mA
2567 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT821/823/825T
Symbol
Parameter
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VOH
Output HIGH Voltage
VCC = Min.
VIN = VIH or VIL
IOH = –6mA MIL.
2.4
2.0
—
3.3
3.0
0.3
—
V
IOH = –8mA COM'L.
IOH = –12mA MIL.
IOH = –15mA COM'L.
IOL = 32mA MIL.
—
V
V
VOL
Output LOW Voltage
Short Circuit Current
VCC = Min.
VIN = VIH or VIL
VCC = Max., VO = GND(3)
0.5
IOL = 48mA COM'L.
IOS
–60
—
–120 –225
±1
mA
IOFF
Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤ 4.5V
—
µA
2567 lnk 06
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
6.21
4
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Test Conditions(1)
Min. Typ.(2) Max.
Unit
VCC = Max.
VIN = 3.4V(3)
∆ICC
—
—
0.5
2.0
mA
ICCD
Dynamic Power Supply Current(4) VCC = Max.
VIN = VCC
0.15
0.25
mA/
Outputs Open
VIN = GND
MHz
OE = EN = GND
One Input Toggling
50% Duty Cycle
VCC = Max.
Outputs Open
fCP= 10MHz
50% Duty Cycle
OE = EN = GND
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
VCC = Max.
IC
Total Power Supply Current(6)
VIN = VCC
VIN = GND
—
—
—
—
1.5
2.0
3.8
6.0
3.5
5.5
mA
VIN = 3.4V
VIN = GND
VIN = VCC
VIN = GND
7.3(5)
Outputs Open
fCP= 10MHz
50% Duty Cycle
OE = EN = GND
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
VIN = 3.4V
VIN = GND
16.3(5)
2567 tbl 07
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.21
5
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT821/823/825AT
FCT821/823/825BT
Com'l. Mil.
Max. Unit
Com'l.
Mil.
Symbol
Parameter
Propagation Delay
CP to Y OE = LOW)
Condition(1)
= 50pF
= 500
= 300pF(4)
= 500
= 50pF
= 500
Min (2)
.
Max. Min (2)
.
Max. Min (2)
.
Max. Min (2)
.
t
t
PLH
PHL
C
L
1.5
10.0
20.0
—
1.5
11.5
20.0
—
1.5
7.5
15.0
—
1.5
8.5
16.0
—
ns
I
(
R
L
Ω
C
L
1.5
4.0
2.0
4.0
2.0
1.5
6.0
7.0
1.5
4.0
2.0
4.0
2.0
1.5
7.0
7.0
1.5
3.0
1.5
3.0
0
1.5
3.0
1.5
3.0
0
R
L
Ω
t
t
t
t
t
t
t
t
SU
H
Set-up Time HIGH or LOW
to CP
Hold Time HIGH or LOW
to CP
C
L
ns
ns
ns
ns
ns
ns
ns
D
I
R
L
Ω
—
—
—
—
D
I
SU
H
Set-up Time HIGH or LOW
EN to CP
—
—
—
—
Hold Time HIGH or LOW
EN to CP
—
—
—
—
PHL
REM
W
Propagation Delay, CLR to Y
I
14.0
—
15.0
—
1.5
6.0
6.0
9.0
—
1.5
6.0
6.0
9.5
—
Recovery Time CLR to CP
Clock Pulse Width
HIGH or LOW
—
—
—
—
W
CLR Pulse Width LOW
6.0
1.5
—
7.0
1.5
—
6.0
1.5
—
6.0
1.5
—
ns
ns
t
t
PZH
PZL
Output Enable Time OE to Y
I
C
L
= 50pF
= 500
= 300pF(4)
12.0
13.0
8.0
9.0
R
L
Ω
C
L
1.5
1.5
1.5
23.0
7.0
1.5
1.5
1.5
25.0
8.0
1.5
1.5
1.5
15.0
6.5
1.5
1.5
1.5
16.0
7.0
R
L
= 500
= 5pF(4)
= 500
= 50pF
= 500
Ω
t
t
PHZ
PLZ
Output Disable Time OE to Y
I
CL
ns
R
L
Ω
C
L
8.0
9.0
7.5
8.0
R
L
Ω
NOTES:
1. See test circuit and waveforms.
2567 tbl 08
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. This condition is guaranteed but not tested.
6.21
6
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT821/823/825CT
FCT823DT
Com'l.
Min (2)
Com'l.
Mil.
Max.
Symbol
Parameter
Propagation Delay
CP to Y OE = LOW)
Condition(1)
= 50pF
= 500
= 300pF(4)
= 500
= 50pF
= 500
Min (2)
.
Max. Min (2)
.
.
Max.
Unit
t
t
PLH
PHL
C
L
1.5
6.0
12.5
—
1.5
7.0
13.5
—
1.5
1.5
2.0
1.0
3.0
0
5.0
ns
I
(
R
L
Ω
C
L
1.5
3.0
1.5
3.0
0
1.5
3.0
1.5
3.0
0
8.5
—
—
—
—
5.0
—
—
R
L
Ω
t
t
t
t
t
t
t
t
SU
H
Set-up Time HIGH or LOW
to CP
Hold Time HIGH or LOW
to CP
C
L
ns
ns
ns
ns
ns
ns
ns
D
I
R
L
Ω
—
—
D
I
SU
H
Set-up Time HIGH or LOW
EN to CP
—
—
Hold Time HIGH or LOW
EN to CP
—
—
PHL
REM
W
Propagation Delay, CLR to Y
Recovery Time CLR to CP
Clock Pulse Width
I
1.5
6.0
6.0
8.0
—
1.5
6.0
6.0
8.5
—
1.5
3.0
3.0
—
—
(3)
HIGH or LOW
(3)
W
CLR Pulse Width LOW
6.0
1.5
—
6.0
1.5
—
3.0
1.5
—
ns
ns
t
t
PZH
PZL
Output Enable Time OE to Y
I
C
L
= 50pF
= 500
= 300pF(4)
7.0
8.0
4.8
R
L
Ω
C
L
1.5
1.5
1.5
12.5
6.0
1.5
1.5
1.5
13.5
6.0
1.5
1.5
1.5
9.0
4.0
4.0
R
L
= 500
= 5pF(4)
= 500
= 50pF
= 500
Ω
t
t
PHZ
PLZ
Output Disable Time OE to Y
I
CL
ns
R
L
Ω
C
R
L
6.5
6.5
L
Ω
NOTES:
1. See test circuit and waveforms.
2567 tbl 09
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. This condition is guaranteed but not tested.
6.21
7
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
SWITCH POSITION
Test
Switch
VCC
7.0V
Open Drain
Disable Low
Closed
500
Ω
Enable Low
VOUT
VIN
Open
All Other Tests
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
Pulse
Generator
D.U.T.
2567 lnk 10
50pF
500Ω
T
R
C
L
2567 drw 05
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
t
W
t
REM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
2567 drw 07
3V
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
2567 drw 06
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
t
PLH
t
t
PHL
PHL
t
PZL
tPLZ
V
OH
OUTPUT
3.5V
1.5V
3.5V
1.5V
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
V
OL
t
PLH
0.3V
0.3V
VOL
3V
1.5V
0V
t
PZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
V
OH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
2567 drw 08
0V
2567 drw 09
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.21
8
IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
XXXX
X
X
Temp. Range
Device Type
Package
Process
Blank
Commercial
B
MIL-STD-883, Class B
P
Plastic DIP
D
CERDIP
E
CERPACK
L
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package
SO
PY
Q
821AT
823AT
825AT
821BT
823BT
825BT
821CT
823CT
825CT
823DT
10-Bit Non-Inverting Register
9-Bit Non-Inverting Register
8-Bit Non-Inverting Register
54
74
–55°C to +125°C
0°C to +70°C
2567 drw 10
6.21
9
相关型号：
©2020 ICPDF网 联系我们和版权申明