IDT5T915PAI [IDT]
2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER; 2.5V差分1 ： 5时钟缓冲器TERABUFFER
| 型号： | IDT5T915PAI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER |
| 文件： | 总19页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5V DIFFERENTIAL
IDT5T915
1:5 CLOCK BUFFER
TERABUFFER™
DESCRIPTION:
FEATURES:
The IDT5T915 2.5V differential (DDR) clock buffer is a user-selectable
single-endedordifferentialinputtofivedifferentialoutputsbuiltonadvanced
metalCMOStechnology. Thedifferentialclockbufferfanoutfromasingleor
differentialinput tofivedifferentialorsingle-endedoutputsreducesloadingon
theprecedingdriverandprovidesanefficientclockdistributionnetwork. The
IDT5T915canactasatranslatorfromadifferentialHSTL,eHSTL,1.8V/2.5V
LVTTL,LVEPECL,orsingle-ended1.8V/2.5VLVTTLinputtoHSTL,eHSTL,
1.8V/2.5VLVTTLoutputs. Selectableinterfaceiscontrolledby3-levelinput
signalsthatmaybehard-wiredtoappropriatehigh-mid-lowlevels.
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion < 300ps (max)
• High speed propagation delay < 2ns (max)
• Up to 250MHz operation
• Very low CMOS power levels
• Hot insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input
interface
• Selectable differential or single-ended inputs and five differen-
tial outputs
The IDT5T915 true or complementary outputs can be asynchronously
enabled/disabled. Multiple power and grounds reduce noise.
• 2.5V VDD
• Available in TSSOP package
APPLICATIONS:
• Clock and signal distribution
FUNCTIONALBLOCKDIAGRAM
TxS
GL
OUTPUT
CONTROL
G(+)
Q1
OUTPUT
CONTROL
Q1
OUTPUT
CONTROL
Q2
RxS
A
OUTPUT
CONTROL
Q2
A/VREF
OUTPUT
CONTROL
Q3
G(-)
OUTPUT
CONTROL
Q3
OUTPUT
CONTROL
Q4
OUTPUT
CONTROL
Q4
OUTPUT
CONTROL
Q5
OUTPUT
CONTROL
Q5
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
FEBRUARY 2003
1
© 2003 Integrated Device Technology, Inc.
DSC-5893/21
IDT5T915
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
VDD
VDDQ
VI
Description
Power Supply Voltage(2)
Output Power Supply(2)
Input Voltage
Max
–0.5 to +3.6
–0.5 to +3.6
–0.5 to +3.6
–0.5 to VDDQ +0.5
–0.5 to +3.6
–65 to +165
150
Unit
V
V
GL
VDD
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
VDDQ
VDDQ
GND
GND
GND
VDDQ
Q2
V
2
VO
Output Voltage(3)
V
VDD
3
VREF
TSTG
TJ
Reference Voltage(3)
Storage Temperature
Junction Temperature
V
GND
GND
G(+)
VDDQ
Q1
4
°C
°C
5
NOTES:
6
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VDDQ and VDD internally operate independently. No power sequencing requirements
need to be met.
3. Not to exceed 3.6V.
7
8
Q1
9
Q2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
VDDQ
Q3
GND
VDDQ
A/VREF
A
Q3
VDDQ
GND
Q5
VDDQ
GND
Q4
CAPACITANCE(1,2) (TA = +25°C, F = 1.0MHz)
Symbol
Parameter
Min
Typ.
Max.
Unit
CIN
Input Capacitance
—
3.5
—
pF
Q5
Q4
NOTES:
1. This parameter is measured at characterization but not tested.
2. Capacitance applies to all inputs except RxS and TxS.
VDDQ
G(-)
VDDQ
VDDQ
GND
GND
VDDQ
GND
TxS
GND
GND
VDD
VDD
RxS
TSSOP
TOP VIEW
RECOMMENDEDOPERATINGRANGE
Symbol
Description
Min.
–40
2.4
Typ.
+25
2.5
Max.
+85
2.6
Unit
°C
V
TA
AmbientOperatingTemperature
InternalPowerSupplyVoltage
VDD(1)
HSTL Output Power Supply Voltage
Extended HSTL and 1.8V LVTTL Output Power Supply Voltage
1.4
1.65
1.5
1.8
1.6
1.95
V
V
VDDQ(1)
VT
2.5VLVTTLOutputPowerSupplyVoltage
TerminationVoltage
VDD
V
V
VDDQ / 2
NOTE:
1. All power supplies should operate in tandem. If VDD or VDDQ is at maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.
2
IDT5T915
INDUSTRIALTEMPERATURERANGE
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
PINDESCRIPTION
Symbol
A
I/O
Type
Description
I
I
Adjustable(1) Clock input. A is the "true" side of the differential clock input. If operating in single-ended mode, A is the clock input.
A/VREF
Adjustable(1) Complementaryclockinput. A/VREF isthe"complementary"sideofAiftheinputisindifferentialmode. Ifoperatinginsingle-ended
mode,A/VREF isconnectedtoGND. Forsingle-endedoperationindifferentialmode, A/VREF shouldbesettothedesiredtoggle
voltage for A:
2.5VLVTTL
VREF = 1250mV
1.8VLVTTL,eHSTL VREF = 900mV
HSTL
VREF = 750mV
VREF = 1082mV
LVEPECL
G(+)
G(-)
GL
I
I
I
LVTTL(5)
LVTTL(5)
LVTTL(5)
Gate control for "true", Qn, outputs. When G(+) is LOW, the "true" outputs are enabled. When G(+) is HIGH, the "true" outputs are
asynchronouslydisabledtotheleveldesignatedbyGL(4).
Gate control for "complementary", Qn, outputs. When G(-) is LOW, the "complementary" outputs are enabled. When G(-) is HIGH,
the"complementary"outputsareasynchronouslydisabledtotheoppositelevelasGL(4).
Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true"
outputsdisableLOWand"complementary"outputsdisableHIGH.
Qn
Qn
RxS
O
O
I
Adjustable(2) Clockoutputs
Adjustable(2) Complementaryclockoutputs
3 Level(3)
3 Level(3)
Selectssingle-ended2.5VLVTTL(HIGH),1.8VLVTTL(MID)clockinputordifferential(LOW)clockinput
TxS
I
Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or HSTL (LOW) compatible. Used in
conjuctionwithVDDQ tosettheinterfacelevels.
VDD
PWR
PWR
PWR
Power supply for the device core and inputs
VDDQ
Powersupplyforthedeviceoutputs. Whenutilizing2.5VLVTTLoutputs, VDDQ shouldbeconnectedtoVDD.
Power supply return for all power
GND
NOTES:
1. Inputs are capable of translating the following interface standards. User can select between:
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage.
3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt
pulses or be able to tolerate them in down stream circuitry.
5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.
3
IDT5T915
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
INDUSTRIALTEMPERATURERANGE
INPUT/OUTPUTSELECTION(1)
Input
Output
Input
Output
2.5VLVTTL
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
eHSTL
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
HSTL DIF
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL
2.5V LVTTL SE
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
1.8VLVTTL
HSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
HSTL DIF
NOTE:
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require the
A/VREF pin to be connected to GND. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring a VREF. Differential (DIF) inputs are used only in
differential mode.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
Symbol
VIHH
Parameter
Test Conditions
Min.
Max
Unit
V
Input HIGH Voltage Level(1)
Input MID Voltage Level(1)
InputLOWVoltageLevel(1)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
VIN = VDD
VDD – 0.4
—
VIMM
VDD/2 – 0.2 VDD/2 + 0.2
V
VILL
—
—
0.4
200
+50
—
V
HIGH Level
MID Level
LOW Level
I3
3-Level Input DC Current (RxS, TxS)
VIN = VDD/2
–50
–200
µA
VIN = GND
NOTE:
1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2.
4
IDT5T915
INDUSTRIALTEMPERATURERANGE
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFORHSTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(7)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current(9)
InputLOWCurrent(9)
VDD = 2.6V
VDD = 2.6V
VI = VDDQ/GND
VI = GND/VDDQ
—
—
—
±5
±5
µA
—
—
VIK
ClampDiodeVoltage
VDD = 2.4V, IIN = -18mA
- 0.7
- 1.2
+3.6
—
V
VIN
VDIF
VCM
VIH
VIL
DCInputVoltage
- 0.3
0.2
V
DCDifferentialVoltage(2,8)
DC Common Mode Input Voltage(3,8)
DC Input HIGH(4,5,8)
DC Input LOW(4,6,8)
Single-EndedReferenceVoltage(4,8)
V
680
750
750
900
mV
mV
mV
mV
VREF + 100
—
—
VREF - 100
—
VREF
—
OutputCharacteristics
VOH
VOL
Output HIGH Voltage
IOH = -8mA
IOH = -100µA
IOL = 8mA
VDDQ - 0.4
VDDQ - 0.1
—
—
—
V
V
V
V
OutputLOWVoltage
0.4
0.1
IOL = 100µA
—
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF.
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be
referenced.
9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
POWERSUPPLYCHARACTERISTICSFORHSTLOUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current
VDDQ = Max., Reference Clock = LOW(3)
Outputsenabled,Alloutputsunloaded
VDDQ = Max., Reference Clock = LOW(3)
Outputsenabled,Alloutputsunloaded
VDD = Max., VDDQ = Max., CL = 0pF
20
30
mA
IDDQQ
IDDD
IDDDQ
ITOT
Quiescent VDDQ Power Supply Current
0.1
20
0.3
30
mA
µA/MHz
µA/MHz
mA
Dynamic VDD Power Supply
CurrentperOutput
Dynamic VDDQ Power Supply
CurrentperOutput
VDD = Max., VDDQ = Max., CL = 0pF
30
50
Total Power VDD Supply Current
VDDQ = 1.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF
VDDQ = 1.5V, FREFERENCE CLOCK = 250MHz, CL = 15pF
VDDQ = 1.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF
VDDQ = 1.5V, FREFERENCE CLOCK = 250MHz, CL = 15pF
20
35
35
60
40
50
ITOTQ
Total Power VDDQ Supply Current
70
mA
120
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
5
IDT5T915
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
INDUSTRIALTEMPERATURERANGE
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL
Symbol
VDIF
Parameter
Value
Units
V
InputSignalSwing(1)
1
VX
DifferentialInputSignalCrossingPoint(2)
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
750
mV
V
VTHI
CrossingPoint
1
tR, tF
V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the
VDIF (AC) specification under actual use conditions.
2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOReHSTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(7)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current(9)
InputLOWCurrent(9)
VDD = 2.6V
VDD = 2.6V
VI = VDDQ/GND
VI = GND/VDDQ
—
—
—
±5
±5
µA
—
—
VIK
ClampDiodeVoltage
VDD = 2.4V, IIN = -18mA
- 0.7
- 1.2
+3.6
—
V
VIN
VDIF
VCM
VIH
VIL
DCInputVoltage
- 0.3
0.2
V
DCDifferentialVoltage(2,8)
DC Common Mode Input Voltage(3,8)
DC Input HIGH(4,5,8)
DC Input LOW(4,6,8)
Single-EndedReferenceVoltage(4,8)
V
800
900
900
1000
—
mV
mV
mV
mV
VREF + 100
—
VREF - 100
—
VREF
—
OutputCharacteristics
VOH
VOL
Output HIGH Voltage
IOH = -8mA
IOH = -100µA
IOL = 8mA
VDDQ - 0.4
VDDQ - 0.1
—
—
—
V
V
V
V
OutputLOWVoltage
0.4
0.1
IOL = 100µA
—
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in a differential mode, A/VREF is tied to the DC voltage VREF.
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be
referenced.
9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
6
IDT5T915
INDUSTRIALTEMPERATURERANGE
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
POWERSUPPLYCHARACTERISTICSFOReHSTLOUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current
VDDQ = Max., Reference Clock = LOW(3)
Outputsenabled,Alloutputsunloaded
VDDQ = Max., Reference Clock = LOW(3)
Outputsenabled,Alloutputsunloaded
VDD = Max., VDDQ = Max., CL = 0pF
20
30
mA
IDDQQ
IDDD
IDDDQ
ITOT
Quiescent VDDQ Power Supply Current
0.1
20
0.3
30
mA
µA/MHz
µA/MHz
mA
Dynamic VDD Power Supply
CurrentperOutput
Dynamic VDDQ Power Supply
CurrentperOutput
VDD = Max., VDDQ = Max., CL = 0pF
40
60
Total Power VDD Supply Current
VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF
VDDQ = 1.8V, FREFERENCE CLOCK = 250MHz, CL = 15pF
VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF
VDDQ = 1.8V, FREFERENCE CLOCK = 250MHz, CL = 15pF
20
35
40
80
40
50
ITOTQ
Total Power VDDQ Supply Current
80
mA
160
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL
Symbol
VDIF
Parameter
Value
Units
InputSignalSwing(1)
1
V
mV
V
VX
DifferentialInputSignalCrossingPoint(2)
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
900
VTHI
CrossingPoint
1
tR, tF
V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the
VDIF (AC) specification under actual use conditions.
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR
LVEPECL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(2)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current(6)
InputLOWCurrent(6)
VDD = 2.6V
VDD = 2.6V
VDD = 2.4V, IIN = -18mA
VI = VDDQ/GND
—
—
—
—
±5
±5
µA
VI = GND/VDDQ
VIK
ClampDiodeVoltage
—
- 0.7
—
- 1.2
3.6
V
VIN
VCM
VREF
VIH
VIL
DCInputVoltage
- 0.3
915
—
V
DC Common Mode Input Voltage(3,5)
Single-EndedReferenceVoltage(4,5)
DC Input HIGH
1082
1082
—
1248
—
mV
mV
mV
mV
1275
555
1620
875
DC Input LOW
—
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, +25°C ambient.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation while in differential mode, A/VREF is tied to the DC Voltage VREF.
5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should
be referenced.
6. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
7
IDT5T915
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
INDUSTRIALTEMPERATURERANGE
DIFFERENTIALINPUTACTESTCONDITIONSFORLVEPECL
Symbol
VDIF
Parameter
Value
Units
mV
mV
V
InputSignalSwing(1)
732
VX
DifferentialInputSignalCrossingPoint(2)
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
1082
CrossingPoint
1
VTHI
tR, tF
V/ns
NOTES:
1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet
the VDIF (AC) specification under actual use conditions.
2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR2.5V
LVTTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(8)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current(10)
InputLOWCurrent(10)
ClampDiodeVoltage
DCInputVoltage
VDD = 2.6V
VDD = 2.6V
VI = VDDQ/GND
VI = GND/VDDQ
—
—
—
—
±5
±5
µA
VIK
VIN
VDD = 2.4V, IIN = -18mA
—
- 0.7
- 1.2
+3.6
V
V
- 0.3
Single-Ended Inputs(2)
VIH
DC Input HIGH
DC Input LOW
1.7
—
—
V
V
VIL
0.7
DifferentialInputs
VDIF
VCM
VIH
DCDifferentialVoltage(3,9)
DC Common Mode Input Voltage(4,9)
DC Input HIGH(5,6,9)
DC Input LOW(5,7,9)
Single-EndedReferenceVoltage(5,9)
0.2
1150
—
1350
V
1250
1250
mV
mV
mV
mV
VREF + 100
—
—
VIL
VREF - 100
—
VREF
—
OutputCharacteristics
VOH
VOL
Output HIGH Voltage
IOH = -12mA
IOH = -100µA
IOL = 12mA
IOL = 100µA
VDDQ - 0.4
VDDQ - 0.1
—
—
—
V
V
V
V
OutputLOWVoltage
0.4
0.1
—
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and A/VREF is tied to GND.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be
referenced.
10. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
8
IDT5T915
INDUSTRIALTEMPERATURERANGE
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
POWERSUPPLYCHARACTERISTICSFOR2.5VLVTTLOUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current
VDDQ = Max., Reference Clock = LOW(3)
Outputsenabled,Alloutputsunloaded
VDDQ = Max., Reference Clock = LOW(3)
Outputsenabled,Alloutputsunloaded
VDD = Max., VDDQ = Max., CL = 0pF
20
30
mA
IDDQQ
IDDD
IDDDQ
ITOT
Quiescent VDDQ Power Supply Current
0.1
25
0.3
40
mA
µA/MHz
µA/MHz
mA
Dynamic VDD Power Supply
CurrentperOutput
Dynamic VDDQ Power Supply
CurrentperOutput
VDD = Max., VDDQ = Max., CL = 0pF
45
70
Total Power VDD Supply Current
VDDQ = 2.5V., FREFERENCE CLOCK = 100MHz, CL = 15pF
VDDQ = 2.5V., FREFERENCE CLOCK = 200MHz, CL = 15pF
VDDQ = 2.5V., FREFERENCE CLOCK = 100MHz, CL = 15pF
VDDQ = 2.5V., FREFERENCE CLOCK = 200MHz, CL = 15pF
25
45
40
70
ITOTQ
Total Power VDDQ Supply Current
40
80
mA
100
200
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 2.5V LVTTL
Symbol
VDIF
Parameter
Value
VDD
Units
InputSignalSwing(1)
V
V
VX
DifferentialInputSignalCrossingPoint(2)
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
VDD/2
VTHI
CrossingPoint
2.5
V
tR, tF
V/ns
NOTES:
1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must
meet the VDIF (AC) specification under actual use conditions.
2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the
VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2.5V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 2.5V LVTTL
Symbol
VIH
Parameter
Value
VDD
0
Units
V
Input HIGH Voltage
VIL
InputLOWVoltage
V
VTHI
InputTimingMeasurementReferenceLevel(1)
InputSignalEdgeRate(2)
VDD/2
2
V
tR, tF
V/ns
NOTES:
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
9
IDT5T915
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGEFOR1.8V
LVTTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(8)
Max
Unit
InputCharacteristics
IIH
IIL
Input HIGH Current(12)
InputLOWCurrent(12)
ClampDiodeVoltage
DCInputVoltage
VDD = 2.6V
VDD = 2.6V
VI = VDDQ/GND
VI = GND/VDDQ
—
—
—
—
±5
±5
µA
VIK
VIN
VDD = 2.4V, IIN = -18mA
—
- 0.7
- 1.2
V
V
- 0.3
VDDQ + 0.3
Single-Ended Inputs(2)
VIH
DC Input HIGH
DC Input LOW
1.073(11)
—
—
0.683(11)
V
V
VIL
DifferentialInputs
VDIF
VCM
VIH
DCDifferentialVoltage(3,9)
DC Common Mode Input Voltage(4,9)
DC Input HIGH(5,6,9)
DC Input LOW(5,7,9)
Single-EndedReferenceVoltage(5,9)
0.2
825
—
975
V
900
900
mV
mV
mV
mV
VREF + 100
—
—
VIL
VREF - 100
—
VREF
—
OutputCharacteristics
VOH
VOL
Output HIGH Voltage
IOH = -6mA
IOH = -100µA
IOL = 6mA
VDDQ - 0.4
VDDQ - 0.1
—
—
—
V
V
V
V
OutputLOWVoltage
0.4
0.1
IOL = 100µA
—
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 1.8V LVTTL single-ended operation, the RxS pin is allowed to float or tied to VDD/2 and A/VREF is tied to GND.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation in differential mode, A/VREF is tied to the DC voltage VREF. The input is guaranteed to toggle within ±200mV of VREF when VREF is constrained within
+600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the A input. To guarantee switching in voltage range specified in the JEDEC 1.8V
LVTTL interface specification, VREF must be maintained at 900mV with appropriate tolerances.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be
referenced.
10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 • VDD where VDD is 1.8V ± 0.15V.
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated
worst case value ( VIH = 0.65 • [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply.
11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 • VDD where VDD is 1.8V ± 0.15V.
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated
worst case value ( VIL = 0.35 • [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply.
12. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
10
IDT5T915
INDUSTRIALTEMPERATURERANGE
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
POWERSUPPLYCHARACTERISTICSFOR1.8VLVTTLOUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current
VDDQ = Max., Reference Clock = LOW(3)
Outputsenabled,Alloutputsunloaded
VDDQ = Max., Reference Clock = LOW(3)
Outputsenabled,Alloutputsunloaded
VDD = Max., VDDQ = Max., CL = 0pF
20
30
mA
IDDQQ
IDDD
IDDDQ
ITOT
Quiescent VDDQ Power Supply Current
0.1
20
0.3
40
mA
µA/MHz
µA/MHz
mA
Dynamic VDD Power Supply
CurrentperOutput
Dynamic VDDQ Power Supply
CurrentperOutput
VDD = Max., VDDQ = Max., CL = 0pF
55
80
Total Power VDD Supply Current
VDDQ = 1.8V., FREFERENCE CLOCK = 100MHz, CL = 15pF
VDDQ = 1.8V., FREFERENCE CLOCK = 200MHz, CL = 15pF
VDDQ = 1.8V., FREFERENCE CLOCK = 100MHz, CL = 15pF
VDDQ = 1.8V., FREFERENCE CLOCK = 200MHz, CL = 15pF
25
40
40
60
ITOTQ
Total Power VDDQ Supply Current
50
100
240
mA
120
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol
VDIF
Parameter
Value
VDDI
Units
InputSignalSwing(1)
V
mV
V
VX
DifferentialInputSignalCrossingPoint(2)
InputTimingMeasurementReferenceLevel(3)
InputSignalEdgeRate(4)
VDDI/2
VTHI
CrossingPoint
1.8
tR, tF
V/ns
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable
results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions.
2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the
VX specification under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1.8V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol
VIH
Parameter
Value
VDDI
0
Units
V
Input HIGH Voltage(1)
VIL
InputLOWVoltage
V
VTHI
InputTimingMeasurementReferenceLevel(2)
InputSignalEdgeRate(3)
VDDI/2
2
mV
V/ns
tR, tF
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input.
2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
3. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
11
IDT5T915
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
INDUSTRIALTEMPERATURERANGE
ACELECTRICALCHARACTERISTICSOVEROPERATINGRANGE(5)
Symbol
SkewParameters
tSK(O)
Parameter
Min.
Typ.
Max
Unit
ps
Same Device Output Pin-to-Pin Skew(1)
Inverting Skew(2)
Single-EndedandDifferentialModes
Single-EndedinDifferentialMode(DSE)
Single-EndedandDifferentialModes
Single-EndedinDifferentialMode(DSE)
Single-EndedandDifferentialModes
Single-EndedinDifferentialMode(DSE)
Single-EndedandDifferentialModes
Single-EndedinDifferentialMode(DSE)
—
—
—
—
—
—
—
—
—
25
25
—
tSK(INV)
tSK(P)
—
300
—
ps
300
—
Pulse Skew(3)
300
—
ps
300
—
tSK(PP)
Part-to-PartSkew(4)
300
—
ps
300
VOX
HSTLandeHSTLDifferentialTrueandComplementaryOutputCrossingVoltageLevel
VDDQ/2 - 200 VDDQ/2 VDDQ/2 + 200 mV
PropagationDelay
tPLH
tPHL
tR
Propagation Delay A to Qn/Qn
Output Rise Time (20% to 80%)
Output Fall Time (20% to 80%)
2.5V / 1.8V LVTTL Outputs
HSTL / eHSTL Outputs
2.5V / 1.8V LVTTL Outputs
HSTL / eHSTL Outputs
2.5V / 1.8V LVTTL Outputs
HSTL / eHSTL Outputs
—
—
—
—
—
—
—
—
—
—
2.5
2
ns
ps
350
350
350
350
—
1050
1350
1050
1350
250
200
tF
ps
fO
FrequencyRange(HSTL/eHSTLoutputs)
FrequencyRange(2.5V/1.8VLVTTLoutputs)
MHz
—
OutputGateEnable/DisableDelay
tPGE
OutputGateEnabletoQn/Qn
OutputGateEnabletoQn/QnDriventoGLDesignatedLevel
—
—
—
—
3.5
3
ns
ns
tPGD
NOTES:
1. Skew measured between all outputs or output pairs under identical input and output interfaces, transitions and load conditions on any one device. For single ended and differential
LVTTL outputs, this measurement is made when each output voltage passes through VDDQ/2. For differential LVTTL outputs, the true outputs are compared only with other true
outputs and the complementary outputs are compared only with other complementary outputs. For differential HSTL outputs, the measurement takes place at the crossing point
of the true and complementary signals.
2. For operating with either 1.8V or 2.5V LVTTL output interfaces with both true and complementary outputs enabled. Inverting skew is the skew between true and complementary
outputs switching in opposite directions under identical input and output interfaces, transitions and load conditions on any one device.
3. Skew measured is the difference between propagation delay times tPHL and tPLH of any output or output pair under identical input and output interfaces, transitions and load conditions
on any one device. For single ended and differential LVTTL outputs, this measurement is made when each output voltage passes through VDDQ/2. The measurement applies
to both true and complementary signals. For differential HSTL outputs, the measurement takes place at the crossing point of the true and complementary signals.
4. Skew measured is the magnitude of the difference in propagation times between any outputs or output pairs of two devices, given identical transitions and load conditions at identical
VDD/VDDQ levels and temperature.
5. Guaranteed by design.
12
IDT5T915
INDUSTRIALTEMPERATURERANGE
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
ACDIFFERENTIALINPUTSPECIFICATIONS(1)
Symbol
Parameter
Min.
1.73
2.17
Typ.
—
Max
—
Unit
t W
Reference Clock Pulse Width HIGH or LOW (HSTL/eHSTL outputs)(2)
Reference Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL outputs)(2)
ns
—
—
HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL
VDIF
VIH
ACDifferentialVoltage(3)
AC Input HIGH(4,5)
AC Input LOW(4,6)
400
Vx + 200
—
—
—
—
—
—
mV
mV
mV
VIL
Vx - 200
LVEPECL
VDIF
ACDifferentialVoltage(3)
AC Input HIGH(4)
AC Input LOW(4)
400
1275
—
—
—
—
—
—
mV
mV
mV
VIH
VIL
875
NOTES:
1. For differential input mode, RxS is tied to GND.
2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the voltage range defined
by VDIF has been met or exceeded.
3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level.
The AC differential voltage must be achieved to guarantee switching to a new state.
4. For single-ended operation, A/VREF is tied to DC voltage (VREF). Refer to each input interface's DC specification for the correct VREF range.
5. Voltage required to switch to a logic HIGH, single-ended operation only.
6. Voltage required to switch to a logic LOW, single-ended operation only.
13
IDT5T915
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
INDUSTRIALTEMPERATURERANGE
DIFFERENTIALACTIMINGWAVEFORMS
1/fo
tW
tW
VIH
VTHI
VIL
A
VIH
VTHI
VIL
A
tPHL
tPLH
VOH
VOX
VOL
Qn
Qn
tSK(O)
tSK(O)
Qm
VOH
VOX
VOL
Qm
HSTL and eHSTL Output Propagation and Skew Waveforms
1/fo
tW
tW
VIH
VTHI
VIL
A
A
VIH
VTHI
VIL
tPHL
tPLH
VOH
VTHO
VOL
Qn
Qn
Qm
Qm
comp tPHL
comp tPLH
VOH
VTHO
VOL
tSK(O)
tSK(O)
VOH
VTHO
VOL
tSK(O)
tSK(O)
VOH
VTHO
VOL
1.8V or 2.5V LVTTL Output Propagation and Skew Waveforms
NOTES:
1. For the HSTL and eHSTL outputs, tPHL and tPLH are measured from the input passing through VTHI or input pair crossing to the crossing point of each Qn and Qn.
2. For 1.8V and 2.5V LVTTL outputs, tPHL and tPLH are measured from the input passing through VTHI or input pair crossing to the slower of Qn or Qn passing through VTHO.
3. Pulse skew is calculated using the following expression:
tSK(P) = | tPHL - tPLH |
where tPHL and tPLH are measured on the controlled edges of any one output from the rising and falling edges of a single pulse. Note that the tPHL and tPLH shown above are
not valid measurements for this calculation because they are not taken from the same pulse.
14
IDT5T915
INDUSTRIALTEMPERATURERANGE
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
VIH
VTHI
VIL
A
A
VIH
VTHI
VIL
VIH
VTHI
VIL
GL
tPLH
VIH
VTHI
VIL
G(+)
tPGE
tPGD
Qn
VOH
VTHO
VOL
Qn
Differential Gate Disable/Enable Showing Runt Pulse Generation
NOTES:
1. The waveforms shown only gate "true" output, Qn.
2. As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this problem.
15
IDT5T915
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
INDUSTRIALTEMPERATURERANGE
SDR AC TIMING WAVEFORMS
1/fo
tW
tW
VIH
VTHI
VIL
A
VIH
VTHI
VIL
A
tPHL
tPLH
VOH
VTHO
VOL
Qn
Qm
tSK(O)
tSK(O)
VOH
VTHO
VOL
Propagation and Skew Waveforms
NOTES:
1. tPHL and tPLH signals are measured from the input passing through VTHI or input pair crossing to Qn passing through VTHO.
2. Pulse Skew is calculated using the following expression:
tSK(P) = | tPHL - tPLH |
where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the tPHL and tPLH shown are not
valid measurements for this calculation because they are not taken from the same pulse.
VIH
VTHI
VIL
A
A
VIH
VTHI
VIL
VIH
VTHI
VIL
GL
Gx
Qn
tPLH
VIH
VTHI
VIL
tPGD
tPGE
VOH
VTHO
VOL
SDR Gate Disable/Enable Showing Runt Pulse Generation
NOTE:
As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this problem.
16
IDT5T915
INDUSTRIALTEMPERATURERANGE
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
TESTCIRCUITSANDCONDITIONS
VDDI
R1
R2
3 inch, ~50Ω
Transmission Line
VIN
VDDQ
VDD
VDDI
A
D.U.T.
Pulse
Generator
R1
R2
A
3 inch, ~50Ω
Transmission Line
VIN
Test Circuit for Differential Input(1)
DIFFERENTIALINPUTTESTCONDITIONS
Symbol
VDD = 2.5V ± 0.1V
Unit
R1
100
Ω
R2
100
Ω
VDDI
VCM*2
V
HSTL: Crossing of A and A
eHSTL: Crossing of A and A
LVEPECL: Crossing of A and A
1.8V LVTTL: VDDI/2
2.5V LVTTL: VDD/2
VTHI
V
NOTE:
1. This input configuration is used for all input interfaces. For single-ended testing,
the VIN input is tied to GND. For testing single-ended in differential input mode,
the VIN is left floating.
17
IDT5T915
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
INDUSTRIALTEMPERATURERANGE
VDDQ
VDDQ
R1
VDDQ
VDD
VDDQ
VDD
R1
R2
R2
CL
D.U.T.
VDDQ
Qn
Qn
D.U.T.
R1
R2
CL
Qn
CL
Test Circuit for SDR Outputs
Test Circuit for Differential Outputs
DIFFERENTIALOUTPUTTEST
CONDITIONS
SDROUTPUTTESTCONDITIONS
Symbol
VDD = 2.5V ± 0.1V
VDDQ = Interface Specified
15
Unit
Symbol
VDD = 2.5V ± 0.1V
Unit
VDDQ = Interface Specified
CL
R1
pF
Ω
Ω
V
CL
R1
15
100
pF
Ω
Ω
V
100
R2
100
R2
100
VOX
HSTL: Crossing of Qn and Qn
eHSTL: Crossing of Qn and Qn
1.8V LVTTL: VDDQ/2
2.5V LVTTL: VDDQ/2
VTHO
VDDQ / 2
VTHO
V
18
IDT5T915
INDUSTRIALTEMPERATURERANGE
2.5VDIFFERENTIAL1:5CLOCKBUFFERTERABUFFER
ORDERINGINFORMATION
XX
X
XXXXX
IDT
Package Process
Device Type
I
-40°C to +85°C (Industrial)
PA
Thin Shrink Small Outline Package
2.5V Differential 1:5 Clock Buffer Terabuffer™
5T915
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
for Tech Support:
logichelp@idt.com
(408) 654-6459
19
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