IDT5T940-30NLGI8 [IDT]
PLL Based Clock Driver, 5T Series, 2 True Output(s), 0 Inverted Output(s), PQCC28, GREEN, PLASTIC, VFQFPN-28;
| 型号： | IDT5T940-30NLGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 5T Series, 2 True Output(s), 0 Inverted Output(s), PQCC28, GREEN, PLASTIC, VFQFPN-28 驱动 逻辑集成电路 |
| 文件： | 总13页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT5T940
PRECISION CLOCK GENERATOR
OC-192 APPLICATIONS
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES OCTOBER 28, 2014
FEATURES:
DESCRIPTION:
• Input frequency:
The IDT5T940 generates a high precision FEC (Forward Error Cor-
rection) or non-FEC source clock for SONET/SDH systems as well as a
source clock for Gigabit Ethernet systems. This device also has clock
regeneration capability: it creates a "clean" version of the clock input by
using the internal oscillator to square the input clock's rising and falling
edges and remove jitter. In the event that the main clock input fails, the
device automatically locks to a backup reference clock using a hitless
switchover mechanism.
- ForSONETnon-FEC:19.44MHz,38.88MHz,77.76MHz,155.52MHz,
311.04MHz, or 622.08MHz
- For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz,
333.26MHz, or 666.52MHz
- For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz,
312.5MHz, or 625MHz
- For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz,
322.26MHz, or 644.53MHz
• 3-level inputs for feedback divide ratio and output frequency range
selection
• 1x, 2x, 4x, 8x, 16x, and 32x outputs on QOUT
• Regenerated input clock or QOUT/4 on QREG
• Lock indicator
This device detects loss of valid CLKIN and leaves the VCO of the PLL at
thelastvalidfrequencywhileanalternateinputREFINisselected. IfCLKIN
andREFINaredifferentfrequencies,themultiplicationfactorwillbeadjustedto
retainthesameoutputfrequency.
TheIDT5T940canactasatranslatorfromadifferentialLVPECL,LVDS,or
single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T940-10
has LVDS outputs and the IDT5T940-30 has LVPECL outputs.
ThethreemodesofoutputfrequencyrangearecontrolledbytheSELmode,
whichisa3-levelpin. WhenSELmodeishighorlow,theQOUT isamultiplied
versionoftheinputclockwhileQREGisaregeneratedversionoftheinputclock.
WhenSELmodeismid,theQOUT isamultipliedversionoftheinputclockwhile
QREG isQOUT/4.
• Power-down mode
• LVPECL or LVDS outputs
• Three modes of output frequency range
- Mode0:QOUT range155.5-166.6MHz. QREG isaregeneratedversion
of the input clock.
- Mode 1: QOUT range 622 - 666.5MHz. QREG output 155.5-166.6MHz.
- Mode 2: QOUT range 622 - 666.5MHz. QREG is a regenerated version
of the input clock frequency.
TheIDT5T940featuresaselectableloopbandwidth.
• Selectable loop bandwidths
• Hitless switchover
• Differential LVPECL, LVDS, or single-ended LVTTL input interface
• 2.375 - 3.465V core and I/O
• Available in VFQFPN package
• use replacement part:8T49N222B-dddNLGI
APPLICATIONS:
• Terabit routers
• Gigabit ethernet systems
• SONET / SDH systems
• Digital cross connects
• Optical transceiver modules
FUNCTIONALBLOCKDIAGRAM
PLLBW1
PLLBW0
QREG
QREG
CLKIN
CLKIN
INPUT
MUX
DIVN
DIVM
PLL
QOUT
QOUT
CONTROL
LOGIC
LOCK,
FREQ.
DETECTOR
REFIN
REFIN
PD
SELMODE
LOCK
CLK/
REF0
CLK/
REF1
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MAY 2013
1
c
2013 Integrated Device Technology, Inc.
DSC 6195/27
IDT5T940
PRECISIONCLOCKGENERATOROC-192APPLICATIONS
INDUSTRIALTEMPERATURERANGE
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
VDD
VI
Description
Max
–0.5 to +4.1
–0.5 to +4.1
–0.5 to VDD+0.5
150
Unit
V
Power Supply Voltage
Input Voltage
V
VO
Output Voltage
V
28 27 26 25 24 23 22
TJ
Junction Temperature
Storage Temperature
°C
°C
GND
CLKIN
CLKIN
GND
1
2
3
4
5
6
7
21
20
19
18
17
16
15
VDD
TSTG
–65 to +165
GND
QREG
QREG
GND
VDD
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
GND
REFIN
REFIN
GND
LOCK
8
9
10 11 12 13 14
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter Description
Typ.
2.5
Max.
3
Unit
pF
CIN
InputCapacitance
OutputCapacitance
COUT
—
—
pF
NOTE:
1. Capacitance applies to all inputs except CLK/REF[1:0] and SELmode.
VFQFPN
TOP VIEW
RECOMMENDEDOPERATINGRANGE
Symbol
Description
Min.
–40
2.375
—
Typ.
+25
Max.
+85
3.465
—
Unit
°C
V
TA
AmbientOperatingTemperature
Power Supply Voltage
VDD
—
VT
TerminationVoltage(LVPECL)
TerminationVoltage(LVDS)
VDD – 2
1.2
V
—
—
2
IDT5T940
INDUSTRIALTEMPERATURERANGE
PRECISIONCLOCKGENERATOROC-192APPLICATIONS
PLLBANDWIDTHSELECTION
OUTPUTFREQUENCYRANGE
PLLBW[1:0]
Min.
65KHz
250KHz
1MHz
4MHz
Max.
120KHz
500KHz
2MHz
Min. CLKIN/REFIN
19.44MHz
SELmode
QOUT/QOUT
155.5-166.6
622-666.5
622-666.5
QREG/QREG
Unit
MHz
MHz
MHz
LL
LH
HL
H H
L
M
H
regeneratedCLKIN/CLKIN
155.5-166.6
19.44MHz
38.88MHz
regeneratedCLKIN/CLKIN
8MHz
155.52MHz
LOCKFREQUENCYDETECTOR
INPUTFREQUENCYRANGE
The 5T940 will lock to, and track, a valid CLKIN signal; LOCK will be low
when this has occurred. If CLKIN fails, the 5T940 PLL will smoothly switch
tolocktoREFINwithoutgeneratinganyglitchesontheoutput. Thefactthat
thePLLislockedtoREFINratherthanCLKINisindicatedbyahighstateon
LOCK.WhenavalidinputisthenappliedtoCLKIN,the5T940willsmoothly
switchbacktolockingonCLKIN,andLOCK willgolow. LOCK willalsoswitch
tohighshouldthefrequencyofCLKINdriftclosetothelimitsoftheVCOtuning
range.
CLK/REF[1:0]
InputFrequencyRange
19.4MHz - 20.9MHz
reserved
H H
H M
HL
38.8MHz - 41.7MHz
77.7MHz - 83.4MHz
AutomaticDetection
155.5MHz - 167MHz
311MHz - 334MHz
reserved
M H
M M
ML
LH
LM
LL
622MHz - 667MHz
PINDESCRIPTION
Pin Name
I/O
Type
Description
CLKIN, CLKIN
I
Adjustable(1)
Differentialorsingle-endedclockinputsignal. Fordifferential,LVPECLorLVDSsupported. Ifleftopen-circuited,inputswillfloat
toLVTTLthresholdvoltagesothateitherinputmaybeusedasasingle-endedinput. Acapacitortogroundshouldbeconnected
onthefloatinginput.
REFIN, REFIN
I
Adjustable(1)
Differentialreferenceclockinput. ThereferenceclockinputisusedasaninputtothePLLwhenCLKIN/CLKINfails. Differential
orsingle-endedclockinputsignal. Fordifferential,LVPECLorLVDSsupported. Ifleftopen-circuited,inputswillfloattoLVTTL
thresholdvoltagesothateitherinputmaybeusedasasingle-endedinput. Acapacitortogroundshouldbeconnectedonthe
floatinginput.
CLK/REF[1:0]
SELmode
PLLBW[1:0]
PD
I
I
3-level(2)
3-level(2)
LVTTL
3levelinputscontrollingPLLfeedbackdividerratio. AutomaticdetectionisusedifbothinputsareMID.
3levelinputtoselectoutputfrequencyrangeforQOUT/QOUT andQREG/QREG (seeOutputFrequencyRangetable)
PLLBandwidthSelectInputs(seePLLBandwidthSelectiontable)
Power Down Control. Shuts off entire chip when LOW.
Differentialclockoutput. LVPECLorLVDSoutputs.
I
I
LVTTL
QOUT, QOUT
QREG, QREG
LOCK
0
0
0
Adjustable(3)
Adjustable(3)
LVTTL
Regenerated clock output from CLKIN/CLKIN, LVPECL, or LVDS outputs.
LOW when PLL is locked to CLKIN, HIGH in all other conditions
Power Supply
VDD
PWR
GND
PWR
Ground
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V LVTTL levels
Single-ended 2.5V LVTTL levels
Differential LVPECL levels
Differential LVDS levels
2. 3-level inputs are static inputs and must be tied to VDD or GND or left floating.
3. Outputs can be LVPECL or LVDS.
3
IDT5T940
PRECISIONCLOCKGENERATOROC-192APPLICATIONS
INDUSTRIALTEMPERATURERANGE
CLOCK INPUT/OUTPUT CONFIGURATION DESCRIPTION
Application
REFIN (MHz)
CKIN (MHz)
SELmode
LOW
MID
QREG (MHz)
19.44
QOUT (MHz)
155.52
622.08
622.08
155.52
622.08
622.08
155.52
622.08
622.08
155.52
622.08
622.08
155.52
622.08
622.08
155.52
622.08
622.08
166.63
666.52
666.52
166.63
666.52
666.52
166.63
666.52
666.52
166.63
666.52
666.52
166.63
666.52
666.52
166.63
666.52
666.52
Non-FEC
19.44,38.88,77.76,155.52,311.04,
622.08
19.44
155.52
19.44
HIGH
LOW
MID
38.88
77.76
38.88
155.52
38.88
HIGH
LOW
MID
77.76
155.52
77.76
HIGH
LOW
MID
155.52
311.04
622.08
20.83
155.52
155.52
155.52
311.04
155.52
311.04
622.08
155.52
622.08
20.83
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
FEC
20.83,41.66,83.31,166.63,333.26,
666.52
166.63
20.83
HIGH
LOW
MID
41.66
41.66
166.63
41.66
HIGH
LOW
MID
83.31
83.31
166.63
83.31
HIGH
LOW
MID
166.63
333.26
666.52
166.63
166.63
166.63
333.26
166.63
333.26
666.52
166.63
666.52
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
4
IDT5T940
INDUSTRIALTEMPERATURERANGE
PRECISIONCLOCKGENERATOROC-192APPLICATIONS
CLOCK INPUT/OUTPUT CONFIGURATION DESCRIPTION (CONTINUED)
Application
REFIN (MHz)
CKIN (MHz)
SEL mode
LOW
MID
QREG (MHz)
19.53
QOUT (MHz)
156.25
625
10GEcopper
19.53,39.06,78.12,156.25,312.5,
625
19.53
156.25
19.53
HIGH
LOW
MID
625
39.06
78.12
156.25
312.5
625
39.06
156.25
625
156.25
39.06
HIGH
LOW
MID
625
78.12
156.25
625
156.25
78.12
HIGH
LOW
MID
625
156.25
156.25
156.25
312.50
156.25
312.5
156.25
625
HIGH
LOW
MID
625
156.25
625
HIGH
LOW
MID
625
625
156.25
625
156.25
625
HIGH
LOW
MID
625
10GEoptical
20.14,40.28,80.56,161.13,322.26,
644.53
20.14
40.28
80.56
161.13
322.26
644.53
20.14
161.13
644.53
644.53
161.13
644.53
644.53
161.13
644.53
644.53
161.13
644.53
644.53
161.13
644.53
644.53
161.13
644.53
644.53
161.13
20.14
HIGH
LOW
MID
40.28
161.13
40.28
HIGH
LOW
MID
80.56
161.13
80.56
HIGH
LOW
MID
161.13
161.13
161.13
322.26
161.13
322.26
644.53
161.13
644.53
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
5
IDT5T940
PRECISIONCLOCKGENERATOROC-192APPLICATIONS
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS(1,2)
Symbol
IDD_PD
ΔIDD
Parameter
Test Conditions
Typ.
—
Max
50
Unit
μA
μA
Power Supply Current
VDD = Max., PD = GND, All outputs unloaded
VDD = Max., VIN = 2.375V
Power Supply Current per Input HIGH
(LVTTLinputsonly)
—
100
ITOT
TotalPowerSupplyCurrent
VDD = Max., QOUT = 622MHz, All outputs unloaded
—
200
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. As a general requirement, these parts must be capable of operating at the maximum frequency under a nominal load at a reasonable operating temperature. That means that
these parts must not burn up under extended use in a typical application.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
Symbol
VIHH
Parameter
Test Conditions
Min.
Max
Unit
V
Input HIGH Voltage Level(1)
Input MID Voltage Level(1)
InputLOWVoltageLevel(1)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
VIN = VDD
VDD – 0.4
—
VIMM
VDD/2 – 0.2 VDD/2 + 0.2
V
VILL
—
—
0.4
200
+50
—
V
HIGH Level
MID Level
LOW Level
I3
3-LevelInputDCCurrent
VIN = VDD/2
–50
–200
μA
VIN = GND
NOTE:
1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched dynamically after powerup,
the function and timing of the outputs may be glitched, and the PLL may require additional tAQ time before all datasheet limits are achieved.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVTTL
Symbol
IIH
Parameter
Input HIGH Current
InputLOWCurrent
ClampDiodeVoltage
DCInputVoltage
DC Input HIGH
Test Conditions
VDD = 3.465V
Min.
—
Typ.
—
Max
±1
Unit
μA
IIL
VDD = 3.465V
—
—
±1
VIK
VDD = 2.375V, IIN = -18mA
—
- 0.7
—
- 1.2
+3.465
—
V
V
V
V
VIN
- 0.3
1.7
—
VIH
—
VIL
DC Input LOW
—
0.7
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVPECL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
InputCharacteristics
IIN
Input Current (CLKIN, REFIN)
VDD = 3.465V
-20
1
—
—
—
+20
VDD - 0.3
—
μA
V
VCMR
VDIF
CommonModeInputVoltage
DifferentialVoltageRequiredtoToggleInput
100
mV
OutputCharacteristics
VOH
VOL
OutputVoltageHIGH(terminatedthrough50Ωtied to VDD -2V)(2)
OutputVoltageLOW(terminatedthrough50ΩtiedtoVDD -2V)(2)
VDD - 1.15
VDD - 1.95
0.55
—
—
—
VDD - 0.9
VDD - 1.61
0.93
V
V
V
VSWING
Peak-to-PeakOutputVoltageSwing
NOTES:
1. VDD = 2.375 - 3.645V.
2. Not to exceed VDD - 0.05V.
6
IDT5T940
INDUSTRIALTEMPERATURERANGE
PRECISIONCLOCKGENERATOROC-192APPLICATIONS
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVDS
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
InputCharacteristics
IIN
Input Current (CLKIN, REFIN)
CommonModeInputVoltageRange(1)
VDD = 3.465V
-20
0.9
100
—
—
—
+20
VDD - 0.05
—
μA
V
VCM
VDIF
DifferentialVoltageRequiredtoToggleInput
mV
OutputCharacteristics
VOT(+)
VOT(-)
ΔVOT
VOS
DifferentialOutputVoltagefortheTRUEBinaryState
247
-247
—
—
—
—
1.2
—
9
454
-454
50
mV
mV
mV
V
DifferentialOutputVoltagefortheFALSEBinaryState
ChangeinVOTBetweenComplementaryOutputStates
OutputCommonModeVoltage(OffsetVoltage)
ChangeinVOSBetweenComplementaryOutputStates
OutputsShortCircuitCurrent
1.125
—
1.375
50
ΔVOS
IOS
mV
mA
mA
VOUT(+) and VOUT(-) = 0V
VOUT(+) = VOUT(-)
—
24
IOSD
DifferentialOutputsShortCircuitCurrent
—
6
12
NOTE:
1. Not to exceed VDD - 0.05V.
INPUT TIMING REQUIREMENTS
Symbol
Parameter
Min.
40
Typ.
Max.
60
Unit
%
REFH
Input Reference Clock Duty Cycle
InputReferenceClockRange
InputReferenceClockFrequencyTolerance
Clock in Frequency Range
Clock in Duty Cycle
50
FREF
19.44
-100
19.44
40
—
666.52
100
MHz
ppm
MHz
%
REFTOL
FCLKIN
—
—
666.52
60
CLKINH
tAQ
50
AcquisitionTimefromReturnofValidCLKIN
FrequencyToleranceforLOCK
TolerancetoInputJitter
—
60
±450
150
us
LOCKTOL
tJIT(TOL)
-600
600
ppm
GR-253Sect. 5.6.2.2
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (OC-192)
Symbol
Parameter
Min.
155.52
155.52
622.08
19.44
19.44
—
Typ.
—
—
—
—
—
150
100
150
100
10
Max.
166.63
666.52
666.52
666.52
667
Unit
SELmode = LOW
SELmode = MID
SELmode = HIGH
QOUT
MultipliedClockOutputFrequency
MHz
QREG
CLKIN
tR
RegeneratedClockOutputFrequency
InputClockFrequency
MHz
MHz
ps
OutputRiseTime
LVPECL
LVDS
—
—
—
tF
OutputFallTime
LVPECL
LVDS
—
—
ps
—
—
tSK
Skew between QOUT and QREG
PLLBandwidthSetting
JitterTransferPeaking
JitterGeneration(1)
—
20
ps
KHz
PLLBW
65
80
120
tP
tJ
—
—
0.3
1
0.1
dB
Output Frequency = 622MHz - 666.5MHz
—
0.65
2
ps (RMS)
(with 50KHz to 80MHz band pass filter) Output Frequency = 155.5MHz - 166.6MHz
Output Duty Cycle
—
tDUTY
45
—
55
%
NOTE:
1. All input frequencies and PLLBW[1:0] permitted by PLL Bandwidth Selection table.
7
IDT5T940
PRECISIONCLOCKGENERATOROC-192APPLICATIONS
INDUSTRIALTEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (OC-48)
Symbol
Parameter
Min.
155.52
155.52
622.08
19.44
19.44
—
Typ.
Max.
166.63
666.52
666.52
666.52
667
Unit
SELmode = LOW
SELmode = MID
SELmode = HIGH
—
QOUT
MultipliedClockOutputFrequency
—
MHz
—
QREG
CLKIN
tR
RegeneratedClockOutputFrequency
InputClockFrequency
—
MHz
MHz
ps
—
OutputRiseTime
LVPECL
LVDS
150
100
150
100
10
—
—
—
tF
OutputFallTime
LVPECL
LVDS
—
—
ps
—
—
tSK
Skew between QOUT and QREG
PLLBandwidthSetting
—
20
ps
PLLBW
65
80
120
KHz
250
—
305
0.05
0.1
0.4
0.5
—
500
tP
tJ
JitterTransferPeaking
0.1
dB
ps (RMS)
%
Output frequency = 622MHz - 666.5MHz
Output frequency = 155.5MHz - 166.6MHz
Output frequency = 77.7MHz - 83.4MHz
—
0.3
JitterGeneration
(with 12KHz to 20MHz filter)(1)
—
1.5
—
1.7
tDUTY
Output Duty Cycle
45
55
NOTE:
1. All input frequencies and PLLBW[1:0] permitted by PLL Bandwidth Selection table.
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (OC-12)
Symbol
Parameter
Min.
155.52
155.52
622.08
19.44
19.44
—
Typ.
Max.
166.63
666.52
666.52
666.52
667
Unit
SELmode = LOW
SELmode = MID
SELmode = HIGH
—
QOUT
MultipliedClockOutputFrequency
—
MHz
—
QREG
CLKIN
tR
RegeneratedClockOutputFrequency
InputClockFrequency
—
MHz
MHz
ps
—
OutputRiseTime
LVPECL
LVDS
150
100
150
100
10
—
—
—
tF
tSK
OutputFallTime
LVPECL
LVDS
—
—
ps
ps
—
—
Skew between QOUT and QREG
PLLBandwidthSetting
JitterTransferPeaking
—
20
65
80
120
PLLBW
tP
250
305
1250
0.05
0.3
0.4
0.5
—
500
KHz
dB
1000
—
2000
0.1
Output frequency = 155.5MHz - 166.6MHz
Output frequency = 77.7MHz - 83.4MHz
Output frequency = 19.4MHz - 20.9MHz
—
1.1
tJ
JitterGeneration
(with 3KHz to 5MHz filter)(1)
—
1.3
ps (RMS)
%
—
1.6
tDUTY
Output Duty Cycle
45
55
NOTE:
1. All input frequencies and PLLBW[1:0] permitted by PLL Bandwidth Selection table.
8
IDT5T940
INDUSTRIALTEMPERATURERANGE
PRECISIONCLOCKGENERATOROC-192APPLICATIONS
TESTCONDITIONS
A
50
50
LVDS
VDIFF
VT TEST POINT
B
DRIVER
Test Circuit for LVDS Output Characteristics
A
B
50
50
VDIFF
VT
Test Circuit for LVDS Input Characteristics
A
50
50
LVPECL
DRIVER
VDD - 2V
B
VDIFF
Test Circuit for LVPECL Output Characteristics
A
B
50
VDIFF
VB
50
VB = VDD - 2V
Test Circuit for LVPECL Input Characteristics
9
IDT5T940
PRECISIONCLOCKGENERATOROC-192APPLICATIONS
INDUSTRIALTEMPERATURERANGE
RECOMMENDEDLANDINGPATTERN
NL 28 pin
NOTE: All dimensions are in millimeters.
10
IDT5T940
INDUSTRIALTEMPERATURERANGE
PRECISIONCLOCKGENERATOROC-192APPLICATIONS
ORDERINGINFORMATION
IDT
XXXXX
XX
X
Device Type Package Package
I
-40ºC to +85ºC (Industrial)
NLG
VFQFPN - Green
5T940-10 Precision Clock Generator – LVDS Output
5T940-30 Precision Clock Generator – LVPECL Output
11
IDT5T940
PRECISIONCLOCKGENERATOROC-192APPLICATIONS
INDUSTRIALTEMPERATURERANGE
REVISIONHISTORY
Rev
Table
Page
Discription of Change
Date
A
1
NRND - Not Recommended for New Designs
5/16/13
Product Discontinuation Notice - Last Time Buy Expires
October 28, 2014, PDN# CQ-13-02
A
1
11/27/13
12
IDT5T940
INDUSTRIALTEMPERATURERANGE
PRECISIONCLOCKGENERATOROC-192APPLICATIONS
We’ve Got Your Timing Solution.
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in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
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Copyright 2013. All rights reserved.
13
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