IDT5V41064 [IDT]
1 OUTPUT PCIE GEN1/2 SYNTHESIZER Spread-spectrum capable; reduces EMI; 1输出PCIE GEN1 / 2合成器扩频能力;降低EMI
| 型号： | IDT5V41064 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 1 OUTPUT PCIE GEN1/2 SYNTHESIZER Spread-spectrum capable; reduces EMI |
| 文件： | 总12页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
1 OUTPUT PCIE GEN1/2 SYNTHESIZER
IDT5V41064
Recommended Applications
Features/Benefits
One output synthesizer for PCIe Gen1/2
• 16-pin QFN package; very small board footprint
• Spread-spectrum capable; reduces EMI
General Description
• Outputs can be terminated to LVDS; can drive a wider
variety of devices
The IDT5V41064 is a PCIe Gen2 compliant spread
spectrum capable clock generator. The device has 1
differential HCSL output and can be used in communication
or embedded systems to subtantially reduce
electro-magnetic interference (EMI). Spread spectrum can
be enabled via a select pin.
• Spread enable via pin selection; no software required to
configure device
• Industrial temperature range available; supports
demanding embedded applications
• For PCIe Gen3 applications, see the 5V41234
Output Features
Key Specifications
• 1 - 0.7V current mode differential HCSL output pairs
• Cycle-to-cycle jitter < 100 ps
• PCIe Gen2 phase jitter < 3.0ps RMS
Block Diagram
VDD
Control
Logic
SS1
CLK
Phase Lock
Loop
CLK
X1
X2
Clock
Buffer/
Crystal
Oscillator
25 MHz
crystal /clock
Crystal Tuning Capacitors
RR (IREF)
GND
IDT® 1 OUTPUT PCIE GEN1/2 SYNTHESIZER
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Pin Assignment
Spread Spectrum Select Table
SS1
Spread%
-0.5% down
No spread
0
1
13
GND
X1
1
CLK
CLK
X2
GND
VDDA
9
NC
5
16-pin QFN
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
Power Connect to ground.
Pin Description
1
2
3
GND
X1
XI
Crystal or clock input. Connect to 25 MHz crystal or single-ended clock.
X2
XO
Crystal connection. Connect to parallel mode crystal. Leave floating if X1 is driven by
single-ended clock.
4
5
6
7
NC
–
No connect.
GND
SS1
IREF
Power Connect to ground.
Input
Spread Select 1. See table above. Internal pull-up resistor.
Output 475Ω precision resistor must be attached to this pin, which is connected to internal
current source.
8
NC
VDDA
GND
CLK
CLK
NC
–
No connect.
9
Power Connect to 3.3V and filter as analog supply.
Power Connect to ground.
10
11
12
13
14
15
16
Output HCSL complementary output clock.
Output HCSL true output clock.
–
–
No connect.
No connect.
NC
VDD
NC
Power Connect to 3.3 V for OSC and digital circuits.
No connect.
–
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Applications Information
External Components
A minimum number of external components are required for
proper operation.
Output Structures
6*IREF
IREF
=2.3 mA
Decoupling Capacitors
Decoupling capacitors of 0.01 μF should be connected
between VDD and the ground plane (pin 4) as close to the
VDD pin as possible. Do not share ground vias between
components. Route power from power source through the
capacitor pad and then into IDT pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal with
See Layout
Guidelines
C = 16 pF should be used. This crystal must have less than
L
Ω
RR 475
300 ppm of error across temperature in order for the
IDT5V41064 to meet PCI Express specifications.
General PCB Layout Recommendations
Crystal Capacitors
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Crystal capacitors are connected from pins X1 to ground
and X2 to ground to optimize the accuracy of the output
frequency.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
C = Crystal’s load capacitance in pF
L
Crystal Capacitors (pF) = (C - 8) * 2
L
2. No vias should be used between decoupling capacitor
and VDD pin.
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
Current Source (Iref) Reference Resistor - R
R
If board target trace impedance (Z) is 50Ω, then R = 475Ω
(1%), providing IREF of 2.32 mA. The output current (I ) is
R
OH
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the IDT5V41064.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the
IDT5V41064 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the PCI-Express Layout Guidelines section.
The IDT5V41064 can also be terminated to LVDS
compatible voltage levels. See Layout Guidelines section.
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Layout Guidelines for PCI Express
PCIe Reference Clock
Common Recommendations for Differential Routing
L1 length, route as non-coupled 50ohm trace
L2 length, route as non-coupled 50ohm trace
L3 length, route as non-coupled 50ohm trace
Dimension or Value
0.5 max
0.2 max
0.2 max
33
Unit Figure
inch
inch
inch
ohm
ohm
1
1
1
1
1
Rs
Rt
49.9
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
2 min to 16 max
1.8 min to 14.4 max
inch
inch
1
1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace
L4 length, route as coupled stripline 100ohm differential trace
0.25 to 14 max
0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
L2
L1
Rs
Rs
L4
L4'
L2'
L1'
Rt
Rt
HCSL Output Buffer
PCI Express
Down Device
REF_CLK Input
L3' L3
Figure 2: PCI Express Connector Routing
L2
L1
Rs
L4
L4'
L2'
L1'
Rs
Rt
Rt
HCSL Output Buffer
PCI Express
Add-in Board
REF_CLK Input
L3' L3
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Layout Guidelines for LVDS and Other Applications
Alternative Termination for LVDS and other Common Differential Signals (figure 3)
Vdiff
0.45v
0.58
0.80
0.60
Vp-p
0.22v
0.28
0.40
0.3
Vcm
1.08
0.6
0.6
1.2
R1
33
33
33
33
R2
R3
R4
Note
150
78.7
78.7
174
100
137
none
140
100
100
100
100
ICS874003i-02 input compatible
Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Figure 3
L2
L1
R3
R4
R1a
R1b
L4
L4'
L2'
L1'
R2a
R2b
HCSL Output Buffer
Down Device
REF_CLK Input
L3'
L3
Cable Connected AC Coupled Application (figure 4)
Component
Value
Note
R5a, R5b
R6a, R6b
Cc
8.2K 5%
1K 5%
0.1 µF
Vcm
0.350 volts
Figure 4
3.3 Volts
R5a
R5b
Cc
L4
L4'
Cc
R6a
R6b
PCIe Device
REF_CLK Input
IDT® 1 OUTPUT PCIE GEN1/2 SYNTHESIZER
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Typical PCI-Express (HCSL) Waveform
700 mV
0
500 ps
500 ps
tOR
tOF
0.525 V
0.175 V
0.525 V
0.175 V
Typical LVDS Waveform
1325 mV
1000 mV
500 ps
500 ps
tOR
tOF
1250 mV
1150 mV
1250 mV
1150 mV
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5V41064. These ratings are stress
ratings only. Functional operation of the device at these or any other conditions above those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
Item
Rating
Supply Voltage, VDD, VDDA
5.5 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
0 to +70° C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
-40 to +85° C
-65 to +150° C
125°C
Junction Temperature
Soldering Temperature
260°C
ESD Protection (Input)
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
3.135
2.2
Typ.
Max.
3.465
Units
Supply Voltage
V
1
Input High Voltage
V
VDD +0.3
V
V
IH
1
Input Low Voltage
Input Leakage Current
V
I
VSS-0.3
-5
0.8
5
IL
2
0 < Vin < VDD
μA
mA
pF
pF
nH
kΩ
kΩ
IL
Operating Supply Current
Input Capacitance
Output Capacitance
Pin Inductance
I
2 pF load
70
7
DD
C
Input pin capacitance
Output pin capacitance
IN
C
6
OUT
L
5
PIN
Output Resistance
Pull-up Resistor
Rout
CLK outputs
SS1
3.0
R
100
PUP
1 Single edge is monotonic when transitioning through region.
2 Inputs with pull-ups/-downs are not included.
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AC Electrical Characteristics - CLK/CLK
Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature -40 to +85° C
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ.
25
Max.
Units
MHz
MHz
mV
mV
mV
mV
ps
Output Frequency
100
700
0
1,2
Output High Voltage
V
660
-150
250
850
27
OH
1,2
Output Low Voltage
V
OL
1,2
Crossing Point Voltage
Crossing Point Voltage
Absolute
350
40
550
140
100
700
700
125
55
1,2,4
Variation over all edges
1,3
Jitter, Cycle-to-Cycle
25
1,2
Rise Time
t
From 0.175 V to 0.525 V
From 0.525 V to 0.175 V
175
175
332
344
75
ps
OR
1,2
Fall Time
t
ps
OF
1,2
Rise/Fall Time Variation
ps
1,3
Duty Cycle
45
51
%
Stabilization Time
t
From power-up VDD=3.3 V
1.2
3.0
3.0
ms
STABLE
Spread Change Time
t
Settling period after spread change
ms
SPREAD
1
Test setup is R =33 ohms R =50 ohms with 2 pF, R = 475Ω (1%).
S
P
R
2
3
4
Measurement taken from a single-ended waveform.
Measurement taken from a differential waveform.
Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.
Electrical Characteristics - Differential Phase Jitter
Parameter
Symbol
Conditions
Min Typ Max
Units
Notes
t
PCIe Gen1
30
1.2
1.9
86
3
ps (p-p)
ps (RMS)
ps (RMS)
1,2,3
1,2,3
1,2,3
jphasePLL
Jitter, Phase
t
PCIe Gen2, 10 kHz < f < 1.5 MHz
jphaseLO
t
PCIe Gen2, 1.5 MHz < f < Nyquist (50 MHz)
3.1
jphaseHIGH
Note 1. Guaranteed by design and characterization, not 100% tested in production.
Note 2. See http://www.pcisig.com for complete specs.
Note 3: Applies to 100MHz, spread off and 0.5% down spread only.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
Still air
63.2
55.9
53.1
51.4
65.8
° C/W
° C/W
° C/W
° C/W
° C/W
JA
θ
1 m/s air flow
2 m/s air flow
3 m/s air flow
JA
θ
JA
θ
JA
Thermal Resistance Junction to Case
θ
JC
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Marking Diagrams
XXX
XXX
YWW$
064GI
YWW$
064G
Notes:
1. Line 1: ‘XXX’ is the lot traceability (last numeric character of the assembly lot number).
2. Line 2: ‘YYW’ – Date code; $ – Assembly location.
3. Line 3: truncated IDT part number.
4. “G” designates RoHS compliant package.
5. “I” within the part number indicates industrial temperature range.
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Package Outline and Package Dimensions (16-pin QFN)
Package dimensions are kept current with JEDEC Publication No. 95
(Ref)
ND & NE
Even
Seating Plane
(ND-1)x
(Ref)
e
A1
Index Area
(Typ)
If ND & NE
are Even
L
A3
e
2
N
1
2
N
1
2
(NE-1)x
(Ref)
e
Sawn
Singulation
E2
E
E2
2
Top View
b
A
C
(Ref)
ND & NE
Odd
e
Thermal Base
D
D2
2
C
D2
0.08
Millimeters
Symbol
Min
0.80
0
0.20 Reference
0.18
Max
1.00
0.05
A
A1
A3
b
0.30
e
0.50 BASIC
N
16
N
N
4
4
D
E
D x E BASIC
3.00 x 3.00
D2
E2
L
1.55
1.55
0.30
1.80
1.80
0.50
Ordering Information
Part / Order Number
5V41064NLG
Marking
See Page 8
Shipping Packaging
Trays
Package
16-pin QFN
16-pin QFN
16-pin QFN
16-pin QFN
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
5V41064NLG8
5V41064NLGI
Tape and Reel
Trays
5V41064NLGI8
Tape and Reel
“G" after the two-letter package code are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Revision History
Rev. Originator
Date
Description of Change
A
04/01/08 Initial release - preliminary.
B
RW
03/02/10 1. Updated Title and Features bullets
2. Added Differential Phase Jitter table
3. Updated Cycle-to-cycle Jitter spec from 80ps to 125ps
C
D
E
RDW
RDW
RDW
06/18/10 1. Updated package and pinout to 16QFN.
2. Added Spread Spectrum.
07/19/10 1. Updated title and general description
2. Updated cycle-to-cycle jitter spec from 125 to 100 ps
12/21/10 1. Minor corrections
2. Updated with Typical data
3. Released to final
F
RDW
RDW
10/28/11 Updated Thermal char data
G
11/21/11 1. Changed title to “1 Output PCIe GEN1/2 Synthesizer”
2. Added note to Features section: “For PCIe Gen3 applications, see 5V41234”
3. Updated Differential Phase Jitter table.
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For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
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www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or
registered trademarks used to identify products or services of their respective owners.
Printed in USA
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