IDT6198L55Y
更新时间:2024-09-18 02:27:56
品牌:IDT
描述:CMOS STATIC RAM 64K (16K x 4-BIT) with Output Control
IDT6198L55Y 概述
CMOS STATIC RAM 64K (16K x 4-BIT) with Output Control CMOS静态RAM 64K ( 16K ×4位)输出控制
IDT6198L55Y 数据手册
通过下载IDT6198L55Y数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载IDT6198S
IDT6198L
CMOS STATIC RAM
64K (16K x 4-BIT)
with Output Control
Integrated Device Technology, Inc.
niques, provides a cost-effective approach for memory inten-
sive applications. Timing parameters have been specified to
meet the speed demands of the IDT79R3000 RISC proces-
sors.
Access times as fast as 15ns are available. The IDT6198
offersareducedpowerstandbymode, ISB1, whichisactivated
when CS goes HIGH. This capability significantly decreases
system, while enhancing system reliability. The low-power
version (L) also offers a battery backup data retention capa-
bility where the circuit typically consumes only 30µW when
operating from a 2V battery.
FEATURES:
• High-speed (equal access and cycle times)
— Military: 20/25/35/45/55/70/85ns (max.)
— Commercial: 15/20/25/35ns (max.)
• OutputEnable(OE)pinavailableforaddedsystemflexibility
• Low-power consumption
• JEDEC compatible pinout
• Battery back-up operation—2V data retention (L version
only)
• 24-pin CERDIP, high-density 28-pin leadless chip carrier,
and 24-pin SOJ
• Produced with advanced CMOS technology
• Bidirectional data inputs and outputs
• Military product compliant to MIL-STD-883, Class B
All inputs and outputs are TTL-compatible and operate
from a single 5V supply.
TheIDT6198ispackagedineithera24-pin300mil CERDIP,
28-pin leadless chip carrier or 24-pin J-bend small outline IC.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
DESCRIPTION:
The IDT6198 is a 65,536-bit high-speed static RAM orga-
nized as 16K x 4. It is fabricated using IDT’s high-perfor-
mance, high-reliabilitytechnology—CMOS. Thisstate-of-the-
art technology, combined with innovative circuit design tech-
FUNCTIONAL BLOCK DIAGRAM
A0
VCC
GND
65,536-BIT
MEMORY ARRAY
DECODER
A13
I/O0
COLUMN I/O
I/O1
INPUT
DATA
CONTROL
I/O2
I/O3
CS
WE
OE
2987 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MAY 1994
1994 Integrated Device Technology, Inc.
DSC-1010/4
6.3
1
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE(1)
PIN CONFIGURATIONS
Mode
Standby
Read
I/O
Power
Standby
Active
CS
H
L
WE
X
OE
X
1
24
VCC
A13
A12
A11
A10
A9
A0
A1
A2
A3
A4
A5
A6
A7
A8
High-Z
2
23
22
3
H
L
DATAOUT
DATAIN
High-Z
4
21
20
D24-1
Write
L
L
X
Active
5
&
Read
L
H
H
Active
SO24-4
6
19
18
17
16
15
14
13
7
NC
NOTE:
1. H = VIH, L = VIL, X = Don't Care
2987 tbl 02
8
I/O3
I/O2
I/O1
I/O0
WE
9
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
10
11
12
CS
OE
GND
Rating
Com’l.
Mil.
Unit
VTERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0
with Respect
to GND
V
2987 drw 02
DIP/SOJ
TOP VIEW
TA
Operating
0 to +70
–55 to +125 °C
Temperature
TBIAS
TSTG
Temperature
Under Bias
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
INDEX
28 27
3
2
Storage
Temperature
1
1
26
A
4
5
6
7
8
9
NC
25
24
23
22
21
20
19
18
2
3
4
5
6
7
8
A
A
A
A
A
13
12
11
10
9
A
A
A
A
A
A
A
PT
Power Dissipation
1.0
50
1.0
50
W
IOUT
DC Output
Current
mA
L28-2
NOTE:
2987 tbl 03
I/O
I/O
I/O
3
10
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
11
2
1
12
CS
13 14 15 16 17
2987 drw 03
CAPACITANCE (TA = +25°C, f = 1.0MHz)
LCC
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
Max. Unit
TOP VIEW
CIN
VIN = 0V
7
7
pF
pF
CI/O
VOUT = 0V
PIN DESCRIPTIONS
NOTE:
2987 tbl 04
Name
Description
1. This parameter is determined by device characterization, but is not
production tested.
A0–A13
CS
Address Inputs
Chip Select
WE
Write Enable
OE
Output Enable
Data Input/Output
Power
I/O0–I/O3
VCC
GND
Ground
2987 tbl 01
6.3
2
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED DC OPERATING
CONDITIONS
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Symbol
Parameter
Min. Typ. Max. Unit
Grade
Military
Commercial
Temperature
–55°C to +125°C
0°C to +70°C
GND
VCC
VCC
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
4.5
0
5.0
0
5.5
0
V
V
V
0V
5V ± 10%
5V ± 10%
GND
VIH
0V
2.2
—
—
6.0
0.8
2987 tbl 06
VIL
–0.5(1)
V
NOTE:
2987 tbl 05
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V ± 10%
IDT6198S
IDT6198L
Symbol
Parameter
Test Condition
VCC = Max.,
VIN = GND to VCC
Min.
Max.
Min.
Max.
Unit
|ILI|
Input Leakage Current
MIL.
COM’L.
—
—
10
5
—
—
5
2
µA
|ILO|
VOL
Output Leakage Current VCC = Max., CS= VIH,
VOUT = GND to VCC
MIL.
COM’L.
—
—
10
5
—
—
5
2
µA
Output Low Voltage
IOL = 10mA, VCC = Min.
IOL = 8mA, VCC = Min.
0.5
0.4
—
—
0.5
0.4
V
—
VOH
Output High Voltage
IOH = –4mA, VCC = Min.
2.4
—
2.4
—
V
2987 tbl 07
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
6198S15
6198L15
6198S20
6198L20
6198S25
6198L25
6198S35
6198L35
6198S45 6198S55/70/85
6198L45 6198L55/70/85
Symbol
Parameter
Power Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l.
Mil.
Unit
ICC1
Operating Power
Supply Current
S
L
100
75
—
—
100 105 100 105 100 105
70 80 70 80 70 80
—
—
105
80
—
—
105
mA
CS = VIL, Outputs Open
80
VCC = Max., f = 0(2)
ICC2
ISB
Dynamic Operating
Current
CS = VIL, Outputs Open
S
L
135
125
—
—
130 160 125 155 125 140
115 130 105 120 105 115
—
—
140
110
—
—
140
110
mA
mA
mA
(2)
VCC = Max., f = fMAX
Standby Power Supply
Current (TTL Level)
CS ≥ VIH, VCC = Max.,
S
L
60
45
—
—
55
40
70
50
50
35
60
40
45
30
50
35
—
—
50
35
—
—
50
35
(2)
Outputs Open, f = fMAX
ISB1
Full Standby Power
Supply Current (CMOS
Level) CS ≥ VHC,
S
L
20
—
—
15
25
15
20
15
20
—
—
20
—
—
20
1.5
0.5
1.5
0.5
1.5
0.5
1.5
1.5
1.5
VCC=Max., VIN ≥ VHC or
VIN ≤ VLC, f = 0(2)
NOTES:
2987 tbl 06
1. All values are maximum guaranteed values.
2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
6.3
3
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Typ. (1)
VCC @
Max.
VCC @
Symbol
VDR
Parameter
Test Condition
Min.
2.0v
3.0V
2.0V
3.0V
Unit
V
VCC for Data Retention
Data Retention Current
—
2.0
—
—
—
—
ICCDR
MIL.
COM’L.
—
—
10
10
15
15
600
150
900
225
µA
(3)
tCDR
Chip Deselect to Data
Retention Time
CS ≥ VHC
VIN ≥ VHC or ≤ VLC
0
—
—
—
—
ns
(3)
tR
|ILI|(3)
(2)
Operation Recovery Time
Input Leakage Current
tRC
—
—
—
—
—
2
—
2
ns
µA
—
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
2987 tbl 09
3. This parameter is guaranteed by device characterization but is not production tested.
LOW VCC DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
VCC
4.5V
4.5V
VDR ≥2V
tR
tCDR
CS
VIH
VIH
VDR
2987 drw 04
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
1.5V
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5V
See Figures 1 and 2
2987 tbl 10
5V
5V
480Ω
480Ω
DATAOUT
DATAOUT
255Ω
255Ω
5pF*
30pF*
2987 drw 05
2987 drw 06
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tOLZ, tCLZ, tOHZ, tWHZ, tCHZ and tOW)
*Includes scope and jig capacitances
6.3
4
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
6198S15(1)
6198L15(1)
6198S20
6198L20
6198S25
6198L25
6198S35 6198S45/55(2) 6198S70/85(2)
6198L35 6198L45/55(2) 6198L70/85(2)
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
tAA
Read Cycle Time
15
—
—
5
—
15
15
—
8
20
—
—
5
—
19
20
—
9
25
—
—
5
—
25
25
—
11
—
10
9
35
—
—
5
—
35
35
—
18
—
14
15
—
—
35
45/55
—
—
5
—
45/55
45/55
—
70/85
—
—
5
—
ns
Address Access Time
70/85 ns
70/85 ns
tACS
Chip Select Access Time
(3)
tCLZ
tOE
Chip Select to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Select to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
—
ns
45/55 ns
ns
—
5
—
5
—
5
—
5
—
5
25/35
—
—
5
(3)
(3)
tOLZ
—
7
—
8
—
tCHZ
tOHZ
tOH
2
2
2
2
—
—
5
15/20
15/20
—
—
—
5
25/30 ns
25/30 ns
(3)
2
7
2
8
2
2
5
—
—
15
5
—
—
20
2
—
—
25
5
—
—
ns
ns
(3)
tPU
tPD
0
0
0
0
0
—
0
(3)
—
—
—
—
—
45/55
—
70/85 ns
NOTES:
2987 tbl 11
1. 0° to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter is guaranteed by device characterization but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC
ADDRESS
tAA
tOH
OE
tOE
(5)
(5)
tOHZ
tOLZ
CS
tACS
(5)
tCHZ
(5)
tCLZ
DATA VALID
DATAOUT
2987 drw 07
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state voltage.
6.3
5
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
2987 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)
CS
(5)
tACS
(5)
tCHZ
tCLZ
DATAOUT
DATA VALID
tPU
tPD
ICC
VCC SUPPLY
CURRENT
ISB
2987 drw 09
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state voltage.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
6198S15(1)
6198L15(1)
6198S20
6198L20
6198S25
6198L25
6198S35 6198S45/55(2) 6198S70/85(2)
6198L35 6198L45/55(2) 6198L70/85(2)
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle
tWC
tCW
tAW
tAS
Write Cycle Time
14
14
14
0
—
—
—
—
—
—
5
17
17
17
0
—
—
—
—
—
—
6
20
20
20
0
—
—
—
—
—
—
7
30
25
25
0
—
—
—
—
—
—
10
—
—
—
40/50
35/50
35/50
0
—
—
60/75
60/75
60/75
0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
—
—
tWP
tWR
tWHZ
tDW
tDH
Write Pulse Width
14
0
17
0
20
0
25
0
35/50
0
—
60/75
0
Write Recovery Time
—
(3)
Write Enable to Output in High-Z
Data Valid to End-of-Write
Data Hold Time
—
10
0
—
10
0
—
13
0
—
15
0
—
15/25
—
—
30/40 ns
—
—
—
—
—
—
—
—
—
20/25
0
30/35
0
—
—
—
ns
ns
—
(3)
tOW
Output Active from End-of-Write
5
5
5
5
5
—
5
ns
NOTES:
2987 tbl 12
1. 0° to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter is guaranteed by device characterization, but is not production tested.
6.3
6
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
CONTROLLED TIMING)(1, 2, 3, 7)
WE
tWC
ADDRESS
OE
tAW
CS
tWP
tWR
tAS
WE
(6)
tWZ
(6)
tOW
DATAOUT
DATAIN
(4)
(4)
tDW
tDH
DATA VALID
2987 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CONTROLLED TIMING)(1, 2, 3)
CS
tWC
ADDRESS
tAW
CS
tAS
tCW
tWR
WE
tDW
tDH
DATAIN
DATA VALID
2987 drw 11
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap ( tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
6.3
7
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT6198
X
XX
X
X
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
B
Commercial (0°C to +70°C)
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
D
L
Y
300 mil CERDIP (D24-1)
Leadless Chip Carrier (L28-2)
Small Outline IC J-Bend (SO24-4)
15
20
25
35
45
55
70
85
Commercial Only
Military Only
Military Only
Military Only
Military Only
Speed in nanoseconds
S
L
Standard Power
Low Power
2987 drw 12
6.3
8
IDT6198L55Y 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
IDT6198L55YB | IDT | CMOS STATIC RAM 64K (16K x 4-BIT) with Output Control | 获取价格 | |
IDT6198L70CB | ETC | x4 SRAM | 获取价格 | |
IDT6198L70D | IDT | CMOS STATIC RAM 64K (16K x 4-BIT) with Output Control | 获取价格 | |
IDT6198L70DB | IDT | CMOS STATIC RAM 64K (16K x 4-BIT) with Output Control | 获取价格 | |
IDT6198L70L | IDT | CMOS STATIC RAM 64K (16K x 4-BIT) with Output Control | 获取价格 | |
IDT6198L70LB | IDT | CMOS STATIC RAM 64K (16K x 4-BIT) with Output Control | 获取价格 | |
IDT6198L70Y | IDT | CMOS STATIC RAM 64K (16K x 4-BIT) with Output Control | 获取价格 | |
IDT6198L70YB | IDT | CMOS STATIC RAM 64K (16K x 4-BIT) with Output Control | 获取价格 | |
IDT6198L85CB | ETC | x4 SRAM | 获取价格 | |
IDT6198L85D | IDT | CMOS STATIC RAM 64K (16K x 4-BIT) with Output Control | 获取价格 |
IDT6198L55Y 相关文章
- 2024-09-20
- 6
- 2024-09-20
- 9
- 2024-09-20
- 8
- 2024-09-20
- 6