IDT7005L55GI [IDT]
Dual-Port SRAM, 8KX8, 55ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-68;
| 型号： | IDT7005L55GI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 8KX8, 55ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-68 静态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED
IDT7005S/L
8K x 8 DUAL-PORT
STATIC RAM
one device
Features
◆
◆
M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Devices are capable of withstanding greater than 2001V
electrostatic discharge
Battery backup operation2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin
thin quad flatpack
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
◆
◆
◆
◆
Military:20/25/35/55/70ns(max.)
Industrial: 35/55ns (max.)
Commercial:15/17/20/25/35/55ns(max.)
Low-power operation
◆
◆
◆
IDT7005S
Active: 750mW (typ.)
Standby: 5mW (typ.)
IDT7005L
◆
◆
◆
Active: 700mW (typ.)
Standby: 1mW (typ.)
IDT7005 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
◆
◆
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
FunctionalBlockDiagram
OER
OEL
CEL
CER
R/WL
R/WR
I/O0L- I/O7L
I/O0R-I/O7R
I/O
I/O
Control
Control
(1,2)
BUSYL
(1,2)
BUSYR
A12R
A12L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A0L
A0R
13
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CEL
OEL
CER
OER
WR
R/
R/WL
SEMR
INTR
SEML
INTL
M/S
(2)
(2)
2738 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
JUNE 1999
1
DSC 2738/11
©1998 Integrated Device Technology, Inc.
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
a very low standby power mode.
The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM. The
IDT7005isdesignedtobeusedasastand-alone64K-bitDual-PortRAM
orasacombinationMASTER/SLAVEDual-PortRAMfor16-bit-or-more
wordsystems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproach
in16-bitorwidermemorysystemapplicationsresultsinfull-speed,error-
freeoperationwithouttheneedforadditionaldiscretelogic.
FabricatedusingIDTsCMOShigh-performancetechnology,these
devices typically operate on only 750mW of power. Low-power (L)
versionsofferbatterybackupdataretentioncapabilitywithtypicalpower
consumptionof500µWfroma2Vbattery.
The IDT7005 is packaged in a ceramic 68-pin PGA, 68-pin quad
flatpack,68-pinPLCCanda64-pinthinquadflatpack,(TQFP).Military
gradeproductismanufacturedincompliancewiththelatestrevisionofMIL-
PRF-38535QMLmakingitideallysuitedtomilitarytemperatureapplica-
tionsdemandingthehighestlevelofperformanceandreliability.
This device provides two independent ports with separate control,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
reads or writes to any location in memory. An automatic power down
featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter
PinConfigurations(1,2,3)
INDEX
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSY
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59
58
57
56
55
IDT7005J or F
J68-1(4)
54
53
52
51
50
49
48
47
46
45
44
F68-1(4)
L
68 Pin PLCC / FLATPACK
Top View(5)
,
I/O3R
I/O4R
I/O5R
I/O6R
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2738 drw 02
INDEX
1
2
3
4
5
6
48
47
46
A4L
I/O2L
A3L
3L
4L
I/O
A2L
I/O
A1L
45
44
43
I/O5L
GND
I/O6L
I/O7L
VCC
A0L
7005PF
PN-64(4)
INTL
BUSY
L
7
8
9
42
41
40
GND
64-Pin TQFP
Top View(5)
M/S
GND
I/O0R
I/O1R
I/O2R
.
10
11
12
BUSYR
INTR
A0R
39
38
37
CC
V
13
14
15
16
A1R
36
35
34
33
NOTES:
I/O3R
A2R
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
4R
I/O
A3R
I/O5R
A4R
3. J68-1 package body is approximately .95 in x .95 in x .12 in.
F68-1 package body is approximately .97 in x .97 in x .08 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
2738 drw 03
6.42
2
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
51
A5L
52
50
A4L
48
A2L
46
A0L
44
BUSY
42
M/S
40
INT
38
36
A3R
11
10
09
08
07
1R
L
R
A
53
A7L
49
A3L
47
A1L
45
INTL
43
GND
41
BUSYR
39
37
35
A4R
34
A5R
A0R A2R
6L
A
55
54
A8L
56
32
A7R
33
A6R
9L
A
57
A
30
A9R
31
A8R
11L
A10L
58
59
28
A11R
29
A10R
VCC
A12L
60
N/C
62
IDT7005G
G68-1(4)
61
26
GND
27
A12R
06
05
N/C
63
68-Pin PGA
Top View(5)
24
N/C
25
N/C
SEML
L
CE
65
64
22
SEMR
23
CE
04
03
02
R
L
OE
R/WL
66
67
I/O0L
20
OE
21
R/WR
.
R
N/C
1
3
5
7
9
68
11
13
VCC
15
18
I/O7R
19
N/C
GND
GND
I/O7L
I/O1L
I/O4L
I/O2L
I/O1R
I/O4R
2
4
6
8
10
12
14
16
17
01
I/O5L
I/O0R I/O2R I/O3R I/O5R I/O6R
VCC
E
I/O6L
I/O3L
A
B
C
D
F
G
H
J
K
L
INDEX
2738 drw 04
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18in x 1.18in x .16in.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
PinNames
Left Port
Right Port
Names
CEL
CER
Chip Enable
WL
WR
R/
R/
Read/Write Enable
Output Enable
Address
OEL
OER
0L
12L
0R
12R
A
- A
A
- A
0L
0R
7R
I/O - I/O7L
SEML
I/O - I/O
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
SEMR
INTR
BUSYR
S
INTL
BUSYL
M/
Master or Slave Select
Power
CC
V
GND
Ground
2738 tbl 01
6.42
3
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
R/W
X
I/O0-7
Mode
CE
H
OE
X
SEM
H
High-Z
DATAIN
Deselected: Power-Down
Write to Memory
L
L
X
H
L
H
L
H
DATAOUT Read Memory
High-Z Outputs Disabled
X
X
H
X
2738 tbl 02
NOTE:
1. A0L A12L is not equal to A0R A12R
Truth Table II: Semaphore Read/Write Control(1)
Inputs(1)
Outputs
R/W
I/O0-7
Mode
CE
H
OE
L
SEM
H
↑
L
L
L
DATAOUT Read in Semaphore Flag Data Out
H
X
DATAIN
Write I/Oo into Semaphore Flag
Not Allowed
____
L
X
X
2738 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O7. These eight semaphores are addressed by A0 - A2.
AbsoluteMaximumRatings(1)
MaximumOperatingTemperature
andSupplyVoltage(1,2)
Commercial
& Industrial
Symbol
Rating
Military
Unit
Ambient
(2)
Grade
Temperature
-55OC to+125OC
0OC to +70OC
-40OC to +85OC
GND
0V
Vcc
VTERM
Terminal Voltage
with Respect to
GND
-0.5 to +7.0
-0.5 to +7.0
V
Military
5.0V + 10%
5.0V + 10%
5.0V + 10%
Temperature Under
Bias
-55 to +125
-55 to +125
50
-65 to +135
-65 to +150
50
oC
oC
Commercial
Industrial
0V
TBIAS
TSTG
IOUT
OV
Storage
Temperature
2738 tbl 05
NOTES:
1. This is the parameter TA.
mA
DC Output Current
2
Industrial temperature: for specific speeds, packages and powers contact
your sales office.
2738 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
RecommendedDCOperating
Conditions
Symbol
Parameter
Min.
Typ.
Max.
5.5
Unit
V
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10%
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
VCC
Supply Voltage
4.5
5.0
GND
VIH
Ground
0
0
0
V
Capacitance(1) (TA = +25°C, f = 1.0MHz)
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
V
____
-0.5(1)
V
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max.
Unit
____
VIL
2738 tbl 06
CIN
VIN = 3dV
9
pF
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
COUT
VOUT = 3dV
10
pF
2738 tbl 07
NOTES:
1. These parameters are determined by device characterization but are not
production tested (TQFP Package only).
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
6.42
4
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the 0perating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7005S
7005L
Symbol
|ILI|
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
Min.
Max.
10
Min.
Max.
Unit
µA
µA
V
___
___
VCC = 5.5V, VIN = 0V to VCC
5
5
___
___
___
___
|ILO|
IH
OUT
CC
10
CE = V , V = 0V to V
VOL
IOL = +4mA
0.4
0.4
___
___
VOH
Output High Voltage
IOH = -4mA
2.4
2.4
V
2738 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
Data Retention Characteristics Over All Temperature RangeS
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
Symbol
VDR
ICCDR
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
V
___
___
VCC for Data Retention
VCC = 2V
2.0
___
Data Retention Current
Mil. & Ind.
Com'l.
100
4000
µA
CE > VHC
___
VIN > VHC or < VLC
100
1500
(3)
___
___
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
SEM > VHC
(3)
(2)
___
___
tR
tRC
ns
2738 tbl 09
NOTES:
1. TA = +25°C, VCC = 2V, and are not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by characterization, but is not production tested.
Data Retention Waveform
DATA RETENTION MODE
VDR >
4.5V
4.5V
tR
VCC
2V
tCDR
VIH
VDR
CE
VIH
2738 drw 05
6.42
5
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6) (VCC = 5.0V ± 10%)
7005X15
7005X17
7005X20
Com'l &
Military
7005X25
Com'l &
Military
Com'l Only
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
CC
I
Dynamic Operating Current
(Both Ports Active)
S
L
170
160
310
260
170
160
310
260
160
150
290
240
155
145
265
220
mA
IL
CE = V , Outputs Open
IH
SEM = V
(3)
MAX
f = f
____
____
____
____
____
____
____
____
MIL &
IND
S
L
160
150
370
320
155
145
340
280
SB1
I
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
20
10
60
60
20
10
60
50
20
10
60
50
16
10
60
50
mA
mA
L
R
IH
CE = CE = V
R
L
IH
SEM = SEM = V
(3)
MAX
f = f
____
____
____
____
____
____
____
____
MIL &
IND
S
L
20
10
90
70
16
10
80
65
(5)
SB2
I
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
105
95
190
160
105
95
190
160
95
85
180
150
90
80
170
140
"A"
IL
"B"
IH
CE = V and CE = V
Active Port Outputs Open,
(3)
MAX
f=f
____
____
____
____
____
____
____
____
R
L
IH
MIL &
IND
S
L
95
85
240
210
90
80
215
180
SEM = SEM = V
SB3
L
I
Full Standby Current (Both Both Ports CE and
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
mA
mA
R
CC
Ports - All CMOS Level
Inputs)
CE > V - 0.2V
IN
IN
CC
V
V
> V - 0.2V or
____
____
____
____
____
____
____
____
(4)
MIL &
IND
S
L
1.0
0.2
30
10
1.0
0.2
30
10
< 0.2V, f = 0
R
L
CC
SEM = SEM > V - 0.2V
SB4
I
Full Standby Current
(One Port - All
CMOS Level Inputs)
"A"
COM'L
S
L
100
90
170
140
100
90
170
140
90
80
155
130
85
75
145
120
CE < 0.2V and
(5)
CE"B"
CC
> V - 0.2V
R
L
CC
SEM = SEM > V - 0.2V
____
____
____
____
____
____
____
____
MIL &
IND
S
L
90
80
225
200
85
75
200
170
IN
CC
IN
V
> V - 0.2V or V < 0.2V
Active Port Outputs Open
(3)
MAX
f = f
2738 tbl 10
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind
& Military
7005X70
Military
Only
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
____
____
____
____
CC
I
Dynamic Operating
Current
(Both Ports Active)
COM'L
S
L
150
140
250
210
150
140
250
210
mA
IL
CE = V , Outputs Open
IH
SEM = V
(3)
MAX
f = f
MIL &
IND
S
L
150
140
300
250
150
140
300
250
140
130
300
250
____
____
____
____
SB1
I
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
13
10
60
50
13
10
60
50
mA
mA
mA
mA
L
R
IH
CE = CE = V
R
L
IH
SEM = SEM = V
f = f
(3)
MAX
MIL &
IND
S
L
13
10
80
65
13
10
80
65
10
8
80
65
____
____
____
____
(5)
SB2
I
Standby Current
(One Port - TTL
Level Inputs)
"A"
IL
"B"
IH
COM'L
S
L
85
75
155
130
85
75
155
130
CE = V and CE = V
Active Port Outputs Open,
(3)
MAX
f=f
85
75
R
L
IH
MIL &
IND
S
L
190
160
85
75
190
160
80
70
190
160
SEM = SEM = V
____
____
____
____
SB3
L
I
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
Both Ports CE and
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
R
CC
CE > V - 0.2V
IN
IN
CC
V
V
> V - 0.2V or
(4)
MIL &
IND
S
L
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
< 0.2V, f = 0
R
L
CC
SEM = SEM > V - 0.2V
____
____
____
____
SB4
I
Full Standby Current
(One Port - All
CMOS Level Inputs)
COM'L
S
L
80
70
135
110
80
70
135
110
"A"
CE < 0.2V and
(5)
"B"
CC
CE > V - 0.2V
R
L
CC
SEM = SEM > V - 0.2V
MIL &
IND
S
L
80
70
175
150
80
70
175
150
75
65
175
150
IN
CC
IN
V
> V - 0.2V or V < 0.2V
Active Port Outputs Open
f = f
(3)
MAX
2738 tbl 11
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VCC = 5V, TA = +25°C and are not production tested. ICC DC = 120mA (typ)
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using AC Test Conditions of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the port opposite port "A".
6. Industrial temperature: for other speeds, packages and powers contact your sales office.
6.42
6
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
5V
5V
AC Test Conditions
Input Pulse Levels
GND to 3.0V
5ns Max.
1.5V
1250Ω
1250Ω
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAOUT
BUSY
INT
DATAOUT
5pF*
775Ω
30pF
775Ω
1.5V
Figures 1 and 2
2738 tbl 12
2738 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(For tLZ, tHZ, tWZ, tOW)
*Including scope and jig
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4,5)
7005X15
Com'l Only
7005X17
Com'l Only
7005X20
Com'l &
Military
7005X25
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
____
tRC
Read Cycle Time
15
17
20
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
tAA
Address Access Time
15
15
17
17
20
20
25
25
Chip Enable Access Time(3)
Output Enable Access Time
____
____
____
____
____
____
____
____
tACE
tAOE
tOH
10
10
12
13
____
____
____
____
Output Hold from Address Change
Output Low-Z Time(1,2)
3
3
3
3
____
____
____
____
tLZ
3
3
3
3
Output High-Z Time(1,2)
10
10
12
15
____
____
____
____
tHZ
tPU
Chip Enable to Power Up Time (2,5)
Chip Disable to Power Down Time (2,5)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
0
0
0
0
____
____
____
____
____
____
____
____
tPD
15
17
20
25
____
____
____
____
tSOP
tSAA
10
10
10
10
____
____
____
____
15
17
20
25
ns
2738 tbl 13a
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind
& Military
IDT7005X70
Military
Only
Symbol
READ CYCLE
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
tRC
Read Cycle Time
35
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
tAA
Address Access Time
35
35
55
55
70
70
Chip Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
____
____
tACE
tAOE
tOH
20
30
35
____
____
____
3
3
3
____
____
____
tLZ
3
3
3
Output High-Z Time(1,2)
15
25
30
____
____
____
tHZ
tPU
Chip Enable to Power Up Time (2,5)
Chip Disable to Power Down Time (2,5)
0
0
0
____
____
____
____
____
____
tPD
35
50
50
____
____
____
tSOP
tSAA
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
15
15
15
____
____
____
35
55
70
ns
2738 tbl 13b
NOTES:
1. Transition is measured ±500mV from Low or High impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
5. Industrial temperature: for other speeds, packages and powers contact your sales office.
6.42
7
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
tAA
(4)
tACE
CE
(4)
tAOE
OE
R/W
(1)
tOH
tLZ
VALID DATA(4)
DATAOUT
(2)
tHZ
BUSYOUT
(3,4)
tBDD
2738 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
Timing of Power-Up Power-Down
CE
PU
t
PD
t
ICC
SB
I
,
2738 drw 08
6.42
8
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5,6)
7005X15
Com'l Only
7005X17
Com'l Only
7005X20
Com'l &
Military
7005X25
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time
Chip Enable to End-of-Write(3)
15
12
12
0
17
12
12
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
tWP
tWR
tDW
tHZ
12
0
12
0
15
0
20
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
10
10
15
15
____
____
____
____
10
10
12
15
____
____
____
____
tDH
0
0
0
0
(1,2)
____
____
____
____
tWZ
tOW
tSWRD
tSPS
Write Enable to Output in High-Z
Output Active from End-of-Write(1, 2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
10
12
15
____
____
____
____
0
5
5
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
____
____
ns
2738 tbl 14a
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind
& Military
7005X70
Military Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time
35
30
30
0
55
45
45
0
70
50
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
tWP
tWR
tDW
tHZ
25
0
40
0
50
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
15
30
40
____
____
____
15
25
30
____
____
____
tDH
0
0
0
(1,2)
____
____
____
tWZ
tOW
tSWRD
tSPS
Write Enable to Output in High-Z
15
25
30
Output Active from End-of-Write(1, 2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
____
____
____
ns
2738 tbl 14b
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with load (Figure 2).
2. This parameter is guaranteed by device characterization but is not production tested.
3. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
6. Industrial temperature: for other speeds, packages and powers contact your sales office.
6.42
9
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
tAW
CE or SEM(9)
(3)
(6)
(2)
tWR
tAS
tWP
R/W
DATAOUT
DATAIN
(7)
tOW
tWZ
(4)
(4)
tDW
tDH
2738 drw 09
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
tWC
ADDRESS
tAW
CE or SEM(9)
(6)
(2)
(3)
tAS
tEW
tWR
R/
W
tDW
tDH
DATAIN
2738 drw 10
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured ±500mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified
tWP.
9. To access RAM, CE = VIH and SEM = VIL. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.42
10
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
tOH
A0-A2
VALID ADDRESS
VALID ADDRESS
tAW
tWR
tACE
tEW
SEM
tDW
tSOP
DATA OUT
VALID
DATA0
DATAIN VALID
tWP tDH
tAS
R/
W
tSWRD
tAOE
OE
tSOP
Write Cycle
Read Cycle
2738 drw 11
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
(2)
SIDE
“A”
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
(2)
R/W"B"
SEM"B"
SIDE “B”
2738 drw 12
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH. Semaphore flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port A may be either left or right port. B is the opposite from port A.
3. This parameter is measured from R/WA or SEMA going HIGH to R/WB or SEMB going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.42
11
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6,7)
7005X15
Com'l Only
7005X17
Com'l Only
7005X20
Com'l &
Military
7005X25
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S=VIH)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
BAA
t
15
15
15
17
17
17
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BDA
t
BAC
t
tBDC
tAPS
tBDD
tWH
15
17
17
17
____
____
____
____
5
5
5
5
____
____
____
____
BUSY Disable to Valid Data(3)
18
18
30
30
(5)
____
____
____
____
Write Hold After
12
13
15
17
BUSY
BUSY TIMING (M/S=VIL)
____
____
____
____
BUSY Input to Write(4)
tWB
0
0
0
0
ns
ns
(5)
____
____
____
____
tWH
Write Hold After BUSY
12
13
15
17
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
30
25
30
25
45
35
50
35
ns
____
____
____
____
tDDD
Write Data Valid to Read Data Delay(1)
ns
____
____
____
____
2738 tbl 15a
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind &
Military
7005X70
Military
Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S=VIH)
____
____
____
____
____
____
____
____
____
____
____
____
tBAA
20
20
20
45
40
40
45
40
40
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
20
35
35
____
____
____
5
5
5
____
____
____
BUSY Disable to Valid Date(3)
35
40
45
(5)
____
____
____
Write Hold After BUSY
25
25
25
BUSY TIMING (M/S=VIL)
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
PORT-TO-PORT DELAY TIMING
tWB
0
0
0
ns
ns
____
____
____
tWH
25
25
25
tWDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
60
45
80
65
95
80
ns
____
____
____
____
____
____
tDDD
ns
2738 tbl 15b
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD tWP (actual) or tDDD tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part number indicates power rating (S or L).
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
6.42
12
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
(4)
Timing Waveform of Write with Port-to-Port Read with BUSY(2,5) (M/S = VIH
)
tWC
MATCH
ADDR"A"
tWP
R/
W"A"
tDW
tDH
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
2738 drw 13
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for for M/S = VIL (slave).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), then BUSY is an input (BUSY"A" =VIH), and BUSY"B" = "don't care", for this example.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite port "A".
Timing Waveform of Write with BUSY
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
tWH
(2)
R/W"B"
2738 drw 14
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on Port "B", blocking R/W"B", until BUSY"B" goes HIGH
3. tWB is only for the 'Slave' Version..
6.42
13
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR
and
"A"
"B"
ADDRESSES MATCH
CE"A"
CE"B"
(2)
APS
t
t
t
BDC
BAC
BUSY"B"
2738 drw 15
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDRESS "N"
(2)
tAPS
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
2738 drw 16
NOTES:
1. All timing is the same for left and right ports. Port A may be either the left or right port. Port B is the port opposite from port A.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1,2)
7005X15
Com'l Only
7005X17
Com'l Only
7005X20
Com'l &
Military
7005X25
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
tAS
Address Set-up Time
Write Recovery Time
0
0
0
0
ns
ns
ns
____
____
____
____
tWR
tINS
tINR
0
0
0
0
____
____
____
____
Interrupt Set Time
15
15
15
15
20
20
20
20
____
____
____
____
Interrupt Reset Time
ns
2738 tb l 16a
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind
& Military
7005X70
Military
Only
Symbol
INTERRUPT TIMING
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
tAS
Address Set-up Time
0
0
0
ns
ns
ns
____
____
____
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
0
0
0
____
____
____
25
25
40
40
50
50
____
____
____
Interrupt Reset Time
ns
2738 tb l 16b
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. Industrial temperature: for other speeds, packages and powers contact your sales office.
6.42
14
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
t
WC
ADDR"A"
INTERRUPT SET ADDRESS(2)
(3)
(4)
t
AS
t
WR
CE"A"
R/
W
"A"
(3)
t
INS
INT"B"
2738 drw 17
t
RC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
CE"B"
(3)
AS
t
OE"B"
(3)
INR
t
INT"B"
2738 drw 18
NOTES:
1. All timing is the same for left and right ports. Port A may be either the left or right port. Port B is the port opposite from port A.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III Interrupt Flag(1,4)
Left Port
Right Port
R/
W
L
A12L-A0L
1FFF
X
R/
W
R
A12R-A0R
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
CE
L
OE
L
INT
L
CE
R
OE
R
INT
R
L
L
X
X
L
X
X
X
X
X
L
X
L
X
L
L(2)
H(3)
X
X
X
X
X
1FFF
1FFE
X
X
X
L(3)
H(2)
L
X
X
L
1FFE
X
X
X
Reset Left INTL Flag
2738 tbl 17
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
6.42
15
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table IV Address BUSY
Arbitration
Inputs
Outputs
AOL-A12L
AOR-A12R
(1 )
(1 )
Function
Normal
Normal
Normal
CEL
X
CER
X
BUSYL
BUSYR
NO MATCH
MATCH
H
H
H
H
H
X
X
H
MATCH
H
H
L
L
MATCH
(2)
(2)
Write Inhibit(3 )
2738 tbl 18
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7005 are
push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D7 Left
D0 - D7 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2738 tbl 19
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7005.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's. These eight semaphores are addressed by A0 - A2.
3. CE=VIH, SEM=VIL to access the semaphores. Refer to the semaphore Read/Write Control Truth Table.
FunctionalDescription
(HEX), where a write is defined as CE = R/W= VIL per Truth Table III.
Theleftportclearstheinterruptthroughaccessofaddresslocation1FFE
when CE =OE = VIL. For this example, R/Wis a "don't care". Likewise,
therightportinterruptflag(INTR)isassertedwhentheleftportwritesto
memory location 1FFF (HEX) and to clear the interrupt flag (INTR), the
rightportmustreadthememorylocation1FFF.Themessage(8bits)at
1FFEor1FFFisuser-defined,sinceitisanaddressableSRAMlocation.
Iftheinterruptfunctionisnotused,addresslocations1FFEand1FFFare
notusedasmailboxes,butaspartoftherandomaccessmemory.Refer
toTruthTableIII fortheinterruptoperation.
TheIDT7005providestwoportswithseparatecontrol,addressand
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation
inmemory.TheIDT7005hasanautomaticpowerdownfeaturecontrolled
by CE. The CE controls on-chip power down circuitry that permits the
respectiveporttogointoastandbymodewhennotselected(CEHIGH).
Whenaportisenabled,accesstotheentirememoryarrayispermitted.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 1FFE
6.42
16
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
SLAVE
Dual Port
RAM
MASTER
Dual Port
RAM
CE
CE
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
CE
CE
BUSY (R)
BUSY (R)
BUSY (L) BUSY (R)
BUSY (L)
BUSY (L)
,
2738 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs.
BusyLogic
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actualwritepulsecanbeinitiatedwiththeR/Wsignal.Failuretoobserve
thistimingcanresultinaglitchedinternalwriteinhibitsignalandcorrupted
data in the slave.
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMisbusy.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
and use any BUSY indication as an interrupt source to flag the event of
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
TheBUSYoutputsontheIDT7005RAMinmastermode,arepush-
pulltypeoutputsanddonotrequirepullupresistorstooperate. Ifthese
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
Semaphores
TheIDT7005isanextremelyfastDual-Port8Kx8CMOSStaticRAM
withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.
TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port
RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby
thesystemdesignerssoftware.Asanexample,thesemaphorecanbe
usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe
Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completelyindependentofeachother.Thismeansthattheactivityonthe
leftportinnoway slowstheaccesstimeof therightport. Bothportsare
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM
enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol
on-chip power down circuitry that permits the respective port to go into
standbymodewhennotselected. Thisistheconditionwhichisshownin
Truth Table I where CE and SEM are both HIGH.
SystemswhichcanbestusetheIDT7005containmultipleprocessors
or controllers and are typically very high-speed systems which are
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
aperformanceincreaseofferedbytheIDT7005'shardwaresemaphores,
whichprovidealockoutmechanismwithoutrequiringcomplexprogram-
ming.
Width Expansion with Busy Logic
Master/SlaveArrays
WhenexpandinganIDT7005RAMarrayinwidthwhileusingBUSY
logic,onemasterpartisusedtodecidewhichsideoftheRAMarraywill
receivea BUSYindication,andtooutputthatindication.Anynumberof
slavestobeaddressedinthesameaddressrangeasthemaster,usethe
BUSYsignalasawriteinhibitsignal.ThusontheIDT7005RAMtheBUSY
pinisanoutputifthepartisusedasamaster(M/Spin=VIH),andtheBUSY
pin is an input if the part used as a slave (M/S pin = VIL) as shown in
Figure 3.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSY ononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
The BUSY arbitration on a master is based on the chip enable and
Softwarehandshaking betweenprocessorsoffersthemaximum in
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
6.42
17
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
configurations.TheIDT7005doesnotuseitssemaphoreflagstocontrol cause either signal (SEM or OE) to go inactive or the output will
anyresourcesthroughhardware,thusallowingthesystemdesignertotal never change.
flexibilityinsystemarchitecture.
AsequenceWRITE/READmustbeusedbythesemaphoreinorder
An advantage of using semaphores rather than the more common to guarantee that no system level contention will occur. A processor
methodsofhardwarearbitrationisthatwaitstatesareneverincurredin requestsaccesstosharedresourcesbyattemptingtowriteazerointoa
either processor. This can prove to be a major advantage in very semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore
high-speedsystems.
requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,
afactwhichtheprocessorwillverifybythesubsequentread(seeTruth
TableV).Asanexample,assumeaprocessorwritesazerototheleftport
atafreesemaphorelocation.Onasubsequentread,theprocessorwill
verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol
overtheresourceinquestion.Meanwhile,ifaprocessorontherightside
attemptstowriteazerotothesamesemaphoreflag itwillfail, aswillbe
verifiedbythefactthataonewillbereadfromthatsemaphoreontheright
side during subsequent read. Had a sequence of READ/WRITE been
usedinstead,systemcontentionproblemscouldhaveoccurredduringthe
gap between the read and write cycles.
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation. The
reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
semaphorerequestlatch.Shouldtheothersidessemaphorerequestlatch
havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
overtotheothersideassoonasaoneiswrittenintothefirstsidesrequest
latch.ThesecondsidesflagwillnowstayLOWuntilitssemaphorerequest
latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphorerequestlatch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-
neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives
thetoken. If onesideisearlierthantheotherinmaking therequest, the
firstsidetomaketherequestwillreceivethetoken.Ifbothrequestsarrive
at the same time, the assignment will be arbitrarily made to one port or
the other.
One caution that should be noted when using semaphores is that
semaphoresalonedonotguaranteethataccesstoaresourceissecure.
Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused
or misinterpreted, a software error can easily happen.
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
calledTokenPassingAllocation.Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
processorwantstousethisresource,itrequeststhetokenbysettingthe
latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
it. If it was successful, it proceeds to assume control over the shared
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe
sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest
thatsemaphoresstatusorremoveitsrequestforthatsemaphoretoperform
anothertaskandoccasionallyattemptagaintogaincontrolofthetokenvia
thesetandtestsequence.Oncetherightsidehasrelinquishedthetoken,
theleftsideshouldsucceedingainingcontrol.
ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting
azerointoasemaphorelatchandisreleasedwhenthesamesidewrites
aonetothatlatch.
The eight semaphore flags reside within the IDT7005 in a separate
memoryspacefromtheDual-PortRAM.This addressspaceisaccessed
byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe
semaphore flags) and using the other control pins (Address, OE, and
R/W) as they would be used in accessing a standard static RAM. Each
oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside
throughaddresspinsA0A2.Whenaccessingthesemaphores,noneof
theotheraddresspinshasanyeffect.
Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
on that side and a one on the other side (see Truth Table V). That
semaphorecannowonlybemodifiedbythesideshowingthezero.When
aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
settoaoneforbothsides(unlessasemaphorerequestfromtheotherside
ispending)andthencanbewrittentobybothsides. Thefactthattheside
whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites
fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
communications.(Athoroughdiscussionontheuseofthisfeaturefollows
shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe
storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis
freedbythefirstside.
Initializationofthesemaphoresisnotautomaticandmustbehandled
viatheinitializationprogramatpower-up.Sinceanysemaphorerequest
flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth
sidesshouldhaveaonewrittenintothematinitializationfrombothsides
to assure that they will be free when needed.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintoonesidesoutput
UsingSemaphoresSomeExamples
Perhapsthesimplestapplicationofsemaphoresistheirapplicationas
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE) resourcemarkersfortheIDT7005sDual-PortRAM.Saythe8Kx8RAM
signalsgoactive.Thisservestodisallowthesemaphorefromchanging wastobedividedintotwo4Kx8blockswhichweretobededicatedatany
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside. onetimetoservicingeithertheleftorrightport.Semaphore0couldbeused
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust toindicatethesidewhichwouldcontrolthelowersectionofmemory,and
6.42
18
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Semaphore 1 could be defined as the indicator for the upper section of evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing
memory.
Totakearesource, inthisexamplethelower4Kof Dual-PortRAM,
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
the processor on the left port could write and then read a zero in to interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring
Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse
back rather than a one), the left processor would assume control of the ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea
lower4K.Meanwhiletherightprocessorwasattemptingtogaincontrolof wasoff-limitstotheCPU,boththeCPUandtheI/Odevicescouldaccess
theresourceaftertheleftprocessor,itwouldreadbackaoneinresponse theirassignedportionsofmemorycontinuouslywithoutanywaitstates.
tothezeroithadattemptedtowriteintoSemaphore0. Atthispoint, the
SemaphoresarealsousefulinapplicationswherenomemoryWAIT
softwarecouldchoosetotryandgaincontrolofthesecond4Ksectionby stateisavailableononeorbothsides.Onceasemaphorehandshakehas
writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining been performed, both processors can access their assigned RAM
control,itwouldlockouttheleftside.
segmentsatfullspeed.
Once the left side was finished with its task, it would write a one to
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
Semaphore 0 and may then try to gain access to Semaphore 1. If case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor
Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo mayberesponsibleforbuildingandupdatingadatastructure.Theother
itssemaphorerequestandperformothertasksuntilitwasabletowrite,then processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting
readazerointoSemaphore1.Iftherightprocessorperformsasimilartask processorreadsanincompletedatastructure,amajorerrorconditionmay
withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo
4K blocks of Dual-Port RAM with each other.
differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks
The blocks do not have to be any particular size and can even be itandthenisabletogoinandupdatethedatastructure.Whentheupdate
variable, depending upon the complexity of the software using the is completed, the data structure block is released. This allows the
semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual- interpretingprocessortocomebackandreadthecompletedatastructure,
Port RAM or other shared resources into eight parts. Semaphores can therebyguaranteeingaconsistentdatastructure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
D0
D0
WRITE
D
D
Q
Q
WRITE
SEMAPHORE
READ
SEMAPHORE
,
READ
2738 drw 20
Figure 4. IDT7005 Semaphore Logic
6.42
19
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
OrderingInformation
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I
B
Commercial (0 C to +70 C)
°
°
(1)
Industrial (-40 C to +85 C)
°
°
Military (-55 C to +125 C)
°
°
Compliant to MIL-PRF-38538 QML
PF
G
J
64-pin TQFP (PN64-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
68-pin Flatpack (F64-1)
F
15
17
20
25
35
55
70
Commercial Only
Commercial Only
Commercial & Military
Commercial & Military
Commercial, Industrial & Military
Commercial, Industrial & Military
Military Only
Speed in nanoseconds
S
L
Standard Power
Low Power
7005 64K (8K x 8) Dual-Port RAM
2738 drw 21
NOTE:
1. Industrial temperature range is available on selected TQFP packages in standard power.
For other speeds, packages and powers contact your sales office.
DatasheetDocumentHistory
12/21/98:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Pages2&3Addedadditionalnotestopinconfigurations
Changeddrawingformat
6/3/99
CORPORATE HEADQUARTERS
2975 StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
831-754-4613
DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
20
相关型号：
IDT7005L55JGB
Dual-Port SRAM, 8KX8, 55ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.120 INCH HEIGHT, GREEN, PLASTIC, LCC-68
IDT
IDT7005L55JGI
Dual-Port SRAM, 8KX8, 55ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.120 INCH HEIGHT, GREEN, PLASTIC, LCC-68
IDT
IDT7005L55JI8
Dual-Port SRAM, 8KX8, 55ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.120 INCH HEIGHT, PLASTIC, LCC-68
IDT
IDT7005L55PFG
Dual-Port SRAM, 8KX8, 55ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-64
IDT
IDT7005L55PFGB
Dual-Port SRAM, 8KX8, 55ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-64
IDT
©2020 ICPDF网 联系我们和版权申明