IDT7006S15PFB 概述
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM 高速16K ×8双端口静态RAM
IDT7006S15PFB 数据手册
通过下载IDT7006S15PFB数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载IDT7006S/L
HIGH-SPEED
16K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• Battery backup operation—2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in a 68-pin PGA, a 68-pin quad flatpack, a 68-
pin PLCC, and a 64-pin TQFP
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 20/25/35/55/70ns (max.)
— Commercial: 15/17/20/25/35/55ns (max.)
• Low-power operation
— IDT7006S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7006L
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
Active: 750mW (typ.)
Standby: 1mW (typ.)
DESCRIPTION:
• IDT7006 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
• Busy and Interrupt Flags
The IDT7006 is a high-speed 16K x 8 Dual-Port Static
RAM. The IDT7006 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 16-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
FUNCTIONAL BLOCK DIAGRAM
OEL
OER
CEL
CER
R/WR
R/W
L
I/O0L- I/O7L
I/O0R-I/O7R
(1,2)
I/O
Control
I/O
Control
BUSY(1,2)
L
BUSY
R
A
13L
A
13R
0R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
0L
A
14
NOTES:
14
1. (MASTER):
BUSY is
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
R/W
L
CE
OE
R/W
R
output;
(SLAVE):
BUSY is input.
2. BUSY outputs
and INT
R
L
R
L
outputs are
non-tri-stated
push-pull.
SEM
L
SEM
R
(2)
INT (2)
L
INTR
M/S
2739 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTOBER 1996
©1996 Integrated Device Technology, Inc.
DSC-2739/5
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.07
1
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
memory system applications results in full-speed, error-free Low-power (L) versions offer battery backup data retention
operation without the need for additional discrete logic. capabilitywithtypicalpowerconsumptionof500µWfroma2V
This device provides two independent ports with separate battery.
control, address, and I/O pins that permit independent,
The IDT7006 is packaged in a ceramic 68-pin PGA, a 68-
asynchronous access for reads or writes to any location in pin quad flatpack, a 68-pin PLCC, and a 64-pin TQFP (thin
memory. An automatic power down feature controlled by CE plasticquadflatpack). Militarygradeproductismanufactured
permits the on-chip circuitry of each port to enter a very low in compliance with the latest revision of MIL-STD-883, Class
standby power mode.
B, making it ideally suited to military temperature applications
Fabricated using IDT’s CMOS high-performance technol- demanding the highest level of performance and reliability.
ogy, these devices typically operate on only 750mW of power.
PIN CONFIGURATIONS (1,2)
INDEX
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
A
A
A
A
A
A
5L
4L
3L
2L
1L
0L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59
58
57
56
55
IDT7006
J68-1
54
53
52
51
50
49
48
47
46
45
44
INT
BUSY
GND
M/
BUSY
INT
L
VCC
F68-1
L
GND
I/O0R
I/O1R
I/O2R
S
PLCC / FLATPACK
TOP VIEW(3)
R
R
VCC
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
1R
2R
3R
4R
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2739 drw 02
INDEX
1
2
3
4
5
6
48
A
A
A
A
A
4L
3L
2L
1L
0L
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
47
46
45
44
43
42
41
40
39
38
37
IDT7006
PN-64
INT
L
7
8
BUSY
L
VCC
GND
TQFP
9
GND
I/O0R
I/O1R
I/O2R
TOP VIEW(3)
M/S
10
11
12
BUSY
R
INT
R
A
A
A
A
A
0R
13
14
15
VCC
36
35
34
33
1R
2R
3R
4R
I/O3R
I/O4R
I/O5R
16
NOTES:
2739 drw 03
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the the actual part-marking.
6.07
2
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D)(1,2)
51
50
48
A
46
A
44
BUSY
42
M/S
40
INT
38
36
11
10
09
08
07
06
05
04
03
02
01
A4L
2L
0L
A1R
A
3R
L
R
A
5L
6L
53
A
52
49
47
A
45
INT
43
GND
41
BUSY
39
37
35
34
L
R
A
4R
7L
A3L
1L
A0R
A
2R
A5R
A
55
A
54
32
33
A
7R
9L
A6R
A
8L
57
A
56
A
30
31
A
9R
A8R
11L
10L
12L
13L
59
58
A
28
29
A
IDT7006
G68-1
A
11R
10R
12R
13R
V
CC
61
60
A
26
GND
27
A
N/C
68-PIN PGA
TOP VIEW(3)
63
62
24
N/C
25
A
SEM
L
CE
L
65
64
22
SEM
23
CER
R
OE
L
R/W
L
67
I/O0L
66
20
OE
21
R/WR
R
N/C
1
3
5
GND
7
9
68
I/O1L
11
13
V
15
18
I/O7R
19
N/C
GND
I/O7L
CC
I/O4L
I/O2L
I/O1R
I/O4R
2
4
6
8
10
12
14
16
17
I/O6R
I/O5L
I/O0R I/O2R I/O3R I/O5R
V
CC
I/O3L
I/O6L
A
B
C
D
E
F
G
H
J
K
L
INDEX
2739 drw 04
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left Port
Right Port
CER
Names
Chip Enable
CEL
R/WL
R/WR
Read/Write Enable
Output Enable
Address
OEL
OER
A0L – A13L
I/O0L – I/O7L
SEML
A0R – A13R
I/O0R – I/O7R
SEMR
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
INTL
INTR
BUSYL
BUSYR
M/S
VCC
Master or Slave Select
Power
GND
Ground
2739 tbl 01
6.07
3
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
Inputs(1)
Outputs
CE
R/W
OE
X
SEM
H
I/O0-7
Mode
H
X
L
High-Z
Deselected: Power-Down
Write to Memory
L
L
X
H
DATAIN
DATAOUT
High-Z
H
X
L
H
Read Memory
X
H
X
Outputs Disabled
NOTE:
2739 tbl 02
1. A0L — A13L is not equal to A0R — A13R.
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL(1)
Inputs
Outputs
CE
R/W
OE
L
SEM
I/O0-7
Mode
Read Data in Semaphore Flag Data Out
Write I/O0 into Semaphore Flag
Not Allowed
H
H
H
L
L
L
DATAOUT
DATAIN
—
X
L
X
X
NOTE:
2739 tbl 03
1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O15. These eight semaphores are addressed by A0 - A2.
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING
Symbol
Rating
Commercial
Military
Unit
TEMPERATURE AND SUPPLY VOLTAGE
(2)
Ambient
VTERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0
V
Grade
Military
Commercial
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
VCC
with Respect
to GND
5.0V ± 10%
TA
Operating
Temperature
0 to +70
–55 to +125 °C
0V
5.0V ± 10%
2739 tbl 05
TBIAS
TSTG
IOUT
Temperature
Under Bias
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
RECOMMENDED DC OPERATING
CONDITIONS
Storage
Temperature
Symbol
Parameter
Supply Voltage
Supply Voltage
Min. Typ. Max. Unit
DC Output
Current
50
50
mA
VCC
4.5
0
5.0
0
5.5
0
V
V
GND
NOTES:
2739 tbl 04
VIH
VIL
Input High Voltage
Input Low Voltage
2.2
–0.5(1)
—
—
6.0(2)
V
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of VTERM < Vcc
+ 0.5V.
0.8
NOTES:
2739 tbl 06
1. VIL≥ -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
CAPACITANCE(1)
(TA = +25°C, f = 1.0MHz)TQFP PACKAGE
Symbol
CIN
Parameter
Conditions(2) Max. Unit
Input Capacitance
VIN = 3dV
9
pF
pF
COUT
Output
VOUT = 3dV
10
Capacitance
NOTES:
2739 tbl 07
1. This parameter is determined by device characterization, but is not
production tested.
2. 3dv references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.07
4
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
IDT7006S
IDT7006L
Symbol
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
CE = VIH, VOUT = 0V to VCC
IOL = 4mA
Min.
Max.
10
Min.
—
Max.
5
Unit
µA
µA
V
|ILI|
—
—
|ILO|
VOL
VOH
10
—
5
—
0.4
—
—
0.4
—
Output High Voltage
IOH = -4mA
2.4
2.4
V
2739 tbl 08
NOTE:
1. At Vcc ≤ 2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%)
7006X15
7006X17
7006X20
7006X25
Test
Com'l. Only
Com'l. Only
Symbol
Parameter
Condition
Version Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit
ICC
Dynamic Operating CE = VIL, Outputs Open
MIL.
COM.
MIL.
S
L
—
—
—
—
—
—
—
—
160 370 155 340 mA
150 320 145 280
Current
SEM = VIH
(3)
(Both Ports Active)
f = fMAX
S
L
170 310 170 310 160 290 155 265
160 260 160 260 150 240 145 220
ISB1
ISB2
ISB3
Standby Current
CEL = CER = VIH
S
L
—
—
—
—
—
—
—
—
20
10
90
70
16
10
80 mA
65
(Both Ports — TTL SEMR = SEML = VIH
(3)
Level Inputs
f = fMAX
COM.
MIL.
S
L
20
10
60
50
20
10
60
50
20
10
60
50
16
10
60
50
(5)
Standby Current
(One Port — TTL
CE"A"=VIL and CE"B"=VIH
Active Port Outputs Open
S
L
—
—
—
—
—
—
—
—
95
85
240
210
90
80
215 mA
180
(3)
Level Inputs)
f = fMAX
COM.
MIL.
S
L
105 190 105 190
95
95
85
180
150
90
80
170
140
SEMR = SEML > VIH
160
95
160
Full Standby Current Both Ports CEL and
(Both Ports — All CER > VCC - 0.2V
S
L
—
—
—
—
—
—
—
—
1.0
0.2
30
10
1.0
0.2
30 mA
10
CMOS Level Inputs) VIN > VCC - 0.2V or
VIN < 0.2V, f = 0 (4)
COM.
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
SEMR = SEML > VCC-0.2V
Full Standby Current CE"A" < 0.2V and
(One Port — All CE"B" > VCC - 0.2V
ISB4
MIL.
S
—
—
—
—
—
—
—
—
90
225
85
200 mA
(5)
CMOS Level Inputs) SEMR = SEML > VCC-0.2V
L
80
90
200
155
75
85
170
145
VIN > VCC - 0.2V or
VIN < 0.2v
COM
.
S
100 170
100 170
Active Port Outputs Open,
f = fMAX
L
90 140
90 140
80
130
75
120
(3)
NOTES:
2739 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICC DC = 120mA (typ.).
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A"may be either left or right port. Port "B" is the port opposite port "A".
6.07
5
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Cont'd.) (VCC = 5.0V ± 10%)
7006X35
7006X55
7006X70
Mil Only
Test
Symbol
Parameter
Condition
Version
MIL.
Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit
ICC
Dynamic Operating
Current
CE = VIL, Outputs Open
SEM = VIH
S
L
150
140
300
250
150
140
300
250
140
130
300 mA
250
(3)
(Both Ports Active)
f = fMAX
COM’L.
MIL.
S
L
150
140
250
210
150
140
250
210
—
—
—
—
ISB1
ISB2
Standby Current
(Both Ports — TTL
CEL = CER = VIH
SEMR = SEML = VIH
S
L
13
10
80
65
13
10
80
65
10
8
80 mA
65
(3)
Level Inputs)
f = fMAX
COM’L.
MIL.
S
L
13
10
60
50
13
10
60
50
—
—
—
—
(5)
Standby Current
(One Port — TTL
Level Inputs)
CE"A"=VIL and CEL"B"=VIH
S
L
85
75
85
75
190
160
155
130
85
75
85
75
190
160
155
130
80
70
—
—
190 mA
Active Port Outputs Open,
160
—
(3)
f = fMAX
COM’L.
S
L
SEMR = SEML = VIH
—
ISB3
ISB4
Full Standby Current
(Both Ports — All
Both Ports CEL and
CER > VCC - 0.2V
MIL.
S
L
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30 mA
10
CMOS Level Inputs)
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
COM’L.
S
L
1.0
0.2
15
5
1.0
0.2
15
5
—
—
—
—
SEMR = SEML≥ VCC-0.2V
Full Standby Current
(One Port — All
CE"A" < 0.2V and
MIL.
S
80
175
80
175
75
175 mA
CE"B" > VCC - 0.2V(5)
CMOS Level Inputs)
SEMR = SEML≥ VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V
L
70
80
150
135
70
80
150
135
65
—
150
—
COM’L.
S
Active Port Outputs Open,
f = fMAX
L
70
110
70
110
—
—
(3)
NOTES:
2739 tbl 10
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICC DC =120mA (typ).
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B"is the opposite from port "A".
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)
(VLC = 0.2V, VHC = VCC - 0.2V)(4)
Symbol
Parameter
Test Condition
VCC = 2V
Min.
Typ.(1)
Max.
Unit
VDR
VCC for Data Retention
Data Retention Current
2.0
—
—
0
—
100
100
—
—
4000
1500
—
V
ICCDR
CE ≥ VHC
MIL.
µA
VIN ≥ VHC or ≤ VLC
SEM ≥ VHC
COM’L.
(3)
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
ns
(3)
(2)
tR
tRC
—
—
ns
NOTES:
2739 tbl 11
1. TA = +25°C, VCC = 2V, and are not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by characterization, but are not production tested.
4. At Vcc = 2V input leakages are undefined
DATA RETENTION WAVEFORM
DATA RETENTION MODE
VDR
≥
V
CC
4.5V
4.5V
2V
t
CDR
tR
VDR
V
IH
VIH
CE
2739 drw 05
6.07
6
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5V 5V
AC TEST CONDITIONS
1250Ω
Input Pulse Levels
GND to 3.0V
5ns Max.
1.5V
1250Ω
DATAOUT
BUSY
INT
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAOUT
775Ω
5pF
775Ω
30pF
1.5V
Figures 1 and 2
2739 drw 06
2739 tbl 12
Figure 1. AC Output Test Load
Figure 2. Output Load
(5pF for tLZ, tHZ, tWZ, tOW)
Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT7006X15
Com'l. Only
Min. Max.
IDT7006X17
Com'l. Only
IDT7006X20
IDT7006X25
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
READ CYCLE
tRC
tAA
Read Cycle Time
15
—
—
—
3
—
15
15
10
17
—
—
—
3
—
17
17
10
—
—
10
—
17
—
17
20
—
—
—
3
—
20
20
12
—
—
12
—
20
—
20
25
—
—
—
3
—
25
25
13
—
—
15
—
25
—
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tACE
tAOE
tOH
tLZ
Chip Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1, 2)
3
—
3
3
3
tHZ
Output High-Z Time(1, 2)
10
—
0
—
0
—
0
tPU
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
0
tPD
15
15
—
10
—
—
10
—
—
10
—
tSOP
tSAA
10
IDT7006X35
IDT7006X55
IDT7006X70
Mil. Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
READ CYCLE
tRC
tAA
Read Cycle Time
35
—
—
—
3
—
35
35
20
—
—
15
—
35
—
35
55
—
—
—
3
—
55
55
30
—
—
25
—
50
—
55
70
—
—
—
3
—
70
70
35
—
—
30
—
50
—
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tACE
tAOE
tOH
tLZ
Chip Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1, 2)
3
3
3
tHZ
Output High-Z Time(1, 2)
—
0
—
0
—
0
tPU
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
tPD
—
15
—
—
15
—
—
15
—
tSOP
tSAA
NOTES:
2739 tbl 13
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. "X" in part numbers indicates power rating (S or L).
6.07
7
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
tRC
ADDRESS
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
t
AOE
R/W
DATAOUT
BUSYOUT
t
OH
(1)
t
LZ
(4)
VALID DATA
(2)
t
HZ
(3, 4)
tBDD
2739 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDD delayisrequiredonlyincases wheretheoppositeportiscompletingawriteoperationtothesameaddresslocation. Forsimultaneousreadoperations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
TIMING OF POWER-UP POWER-DOWN
CE
tPU
tPD
I
CC
SB
50%
50%
I
2739 drw 08
6.07
8
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5)
IDT7006X15
Com'l. Only
IDT7006X17
Com'l. Only
IDT7006X20
IDT7006X25
Min. Max.
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
tEW
tAW
tAS
Write Cycle Time
Chip Enable to End-of-Write(3)
15
12
12
0
—
—
—
—
—
—
—
10
—
—
—
—
—
17
12
12
0
—
—
—
—
—
—
—
10
—
—
—
—
—
20
15
15
0
—
—
—
—
—
—
—
12
—
12
—
—
—
25
20
20
0
—
—
—
—
—
—
—
15
—
15
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End-of-Write
Address Set-up Time(3)
tWP
tWR
tDW
tHZ
Write Pulse Width
12
0
12
0
15
0
20
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1, 2)
Data Hold Time(4)
Write Enable to Output in High-Z(1, 2)
Output Active from End-of-Write(1, 2, 4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
—
0
10
—
0
15
—
0
15
—
0
tDH
tWZ
tOW
tSWRD
tSPS
—
0
—
0
—
0
—
0
5
5
5
5
5
5
5
5
IDT7006X35
IDT7006X55
IDT7006X70
Mil. Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tWC
tEW
Write Cycle Time
35
30
30
0
—
—
—
—
—
—
—
15
—
15
—
—
—
55
45
45
0
—
—
—
—
—
—
—
25
—
25
—
—
—
70
50
50
0
—
—
—
—
—
—
—
30
—
30
—
—
—
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
tAW
ns
tAS
ns
tWP
Write Pulse Width
25
0
40
0
50
0
ns
tWR
Write Recovery Time
ns
tDW
Data Valid to End-of-Write
Output High-Z Time(1, 2)
Data Hold Time(4)
Write Enable to Output in High-Z(1, 2)
Output Active from End-of-Write(1, 2, 4)
SEM Flag Write to Read Time
SEM Flag Contention Window
15
—
0
30
—
0
40
—
0
ns
tHZ
ns
tDH
ns
tWZ
—
0
—
0
—
0
ns
tOW
ns
tSWRD
tSPS
NOTES:
5
5
5
ns
5
5
5
ns
2739 tbl 14
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. "X" in part numbers indicates power rating (S or L).
6.07
9
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8)
t
WC
ADDRESS
(7)
t
HZ
OE
tAW
(9)
CE or SEM
(3)
(2)
(6)
t
WR
t
AS
tWP
R/W
DATAOUT
DATAIN
(7)
t
OW
t
WZ
(4)
(4)
t
DW
tDH
2739 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING(1,5)
tWC
ADDRESS
tAW
CE or SEM (9)
(6)
AS
(3)
(2)
tEW
tWR
t
R/W
DATAIN
tDW
tDH
2739 drw 10
NOTES:
1. R/W or CE must be High during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a Low CE and a Low R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going High to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured by +/- 500mV from steady state with the
Output Test Load (Figure 2)
8. If OE is Low during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore CE = VIH and SEM = VIL. tEW must be met for either condition.
6.07
10
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
tOH
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
tACE
tWR
tAW
tEW
SEM
tSOP
tDW
DATAIN
VALID
DATAOUT
I/O
(2)
VALID
tAS
tWP
tDH
R/W
tSWRD
tAOE
OE
Write Cycle
Read Cycle
2739 drw 11
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
A
0"A"-A2"A"
MATCH
SIDE(2) “A”
R/W"A"
SEM"A"
t
SPS
A
0"B"-A2"B"
MATCH
SIDE(2)
“B”
R/W"B"
SEM"B"
2739 drw 12
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going High to R/W"B" or SEM"B" going High.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.07
11
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
IDT7006X15 IDT7006X17
Com'l. Only Com'l. Only
IDT7006X20
IDT7006X25
Symbol
Parameter
Min. Max. Min. Max.
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S = VIH)
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3
Write Hold After BUSY(5)
—
—
—
—
5
15
15
15
15
—
18
—
—
—
—
—
5
17
17
17
17
—
18
—
—
—
—
—
5
20
20
20
17
—
30
—
—
—
—
—
5
20
20
20
17
—
35
—
ns
ns
ns
ns
ns
ns
ns
—
12
—
13
—
15
—
17
BUSY TIMING (M/S = VIL)
tWB
tWH
BUSY Input to Write(4)
Write Hold After BUSY(5)
0
—
—
0
—
0
—
—
0
—
—
ns
ns
12
13
—
15
17
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
—
—
30
25
—
—
30
25
—
—
45
35
—
—
50
35
ns
ns
IDT7006X35
IDT7006X55
IDT7006X70
Mil. Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S = VIH)
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
BUSY Access Time from Address Match
—
—
—
—
5
20
20
20
20
—
35
—
—
—
—
—
5
45
40
40
35
—
40
—
—
—
—
—
5
45
40
40
35
—
45
—
ns
ns
ns
ns
ns
ns
ns
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
—
25
—
25
—
25
BUSY TIMING (M/S = VIL)
tWB
tWH
BUSY Input to Write(4)
Write Hold After BUSY(5)
0
—
—
0
—
—
0
—
—
ns
ns
25
25
25
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
—
—
60
45
—
—
80
65
—
—
95
80
ns
tDDD
ns
NOTES:
2739 tbl 15
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited with port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention with port "A".
6. "X" is part numbers indicates power rating (S or L).
6.07
12
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(2,4,5)
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (M/S = VIH
)
tWC
MATCH
ADDR"A"
R/W"A"
tWP
tDW
tDH
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
t
DDD
NOTES:
2739 drw 13
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right port. Port "A" may be either left or right port. Port "B" is the port opposite from Port "A".
TIMING WAVEFORM OF WRITE WITH BUSY
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
tWH
(2)
R/W"B"
2739 drw 14
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on Port "B" blocking R/W"B", until BUSY"B" goes High.
3. tWB is only for the 'Slave' Version.
6.07
13
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (M/S = VIH)(1)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
(2)
t
APS
CE"B"
t
BAC
tBDC
BUSY"B"
2739 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING
(M/S = VIH)(1)
ADDRESS "N"
ADDR"A"
ADDR"B"
(2)
t
APS
MATCHING ADDRESS "N"
t
BAA
tBDA
BUSY"B"
2739 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
IDT7006X15
IDT7006X17
IDT7006X20
IDT7006X25
Com'l. Only
Com'l. Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
—
0
0
0
—
—
15
15
0
0
—
—
20
20
0
0
—
—
20
20
ns
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
—
—
—
15
15
—
—
—
—
—
—
Interrupt Reset Time
IDT7006X35
IDT7006X55
IDT7006X70
Mil. Only
Symbol
Parameter
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
0
—
—
25
25
0
0
—
—
40
40
0
0
—
—
50
50
ns
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
—
—
—
—
—
—
Interrupt Reset Time
NOTE:
2739 tbl 16
1. "X" in part numbers indicates power rating (S or L).
6.07
14
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
t
WC
INTERRUPT SET ADDRESS(2)
ADDR"A"
CE"A"
(4)
(3)
t
AS
tWR
R/W"A"
INT"B"
(3)
t
INS
2739 drw 17
tRC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
CE"B"
(3)
AS
t
OE"B"
(3)
t
INR
INT"B"
2739 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
TRUTH TABLES
TRUTH TABLE I — INTERRUPT FLAG(1,4)
Left Port
Right Port
OER A13R-A0R INTR
R/WL
CEL
L
OEL A13L-A0L INTL
R/WR
CER
X
Function
Set Right INTR Flag
L
X
X
X
L
3FFF
X
X
X
L(3)
H(2)
X
X
L
X
L
X
L(2)
H(3)
X
X
X
L
3FFF
3FFE
X
Reset Right INTR Flag
Set Left INTL Flag
X
X
X
X
L
X
X
L
3FFE
X
X
X
Reset Left INTL Flag
NOTES:
2739 tbl 17
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
6.07
15
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE II —
ADDRESS BUSY ARBITRATION
Inputs
Outputs
A0L-A13L
CER A0R-A13R BUSYL
(1)
(1)
CEL
BUSYR
Function
Normal
X
X
X
H
L
NO MATCH
MATCH
H
H
H
H
H
Normal
X
L
MATCH
H
H
Normal
Write Inhibit(3)
MATCH
(2)
(2)
NOTES:
2739 tbl 18
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the
IDT7006 are push pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs cannot be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
TRUTH TABLE III — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1,2)
Functions
D0 - D7 Left
D0 - D7 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
NOTES:
2739 tbl 19
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7006.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.
writes to memory location 3FFF (HEX) and to clear the
interrupt flag (INTR), the right port must read the memory
location 3FFF. The message (8 bits) at 3FFE or 3FFF is user-
defined, since it is an addressable SRAM location. If the
interrupt function is not used, address locations 3FFE and
3FFF are not used as mail boxes, but as part of the random
access memory. Refer to Truth Table for the interrupt opera-
tion.
FUNCTIONAL DESCRIPTION
The IDT7006 provides two ports with separate control,
addressandI/Opinsthatpermitindependentaccessforreads
or writes to any location in memory. The IDT7006 has an
automatic power down feature controlled by CE. The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE high). When a port is enabled, access to the entire
memory array is permitted.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signalstheothersidethattheRAMis“Busy”. Thebusypincan
thenbeusedtostalltheaccessuntiltheoperationon theother
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location(mailboxormessagecenter)isassignedtoeachport.
Theleftportinterruptflag(INTL)isassertedwhentherightport
writes to memory location 3FFE (HEX) where a write is
defined as CE = R/W = VIL per the Truth Table. The left port
clears the interrupt by reading address location 3FFE access
when CER = OER = VIL, R/W is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port
6.07
16
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MASTER
CE
SLAVE
CE
Dual Port
RAM
Dual Port
RAM
BUSY
R
BUSY
L
BUSY
R
BUSYL
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
CE
CE
BUSY
BUSY
R
BUSY
L
BUSYL
BUSY
R
R
BUSY
L
2739 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7006 RAMs.
data in the slave.
applications. In some cases it may be useful to logically OR
SEMAPHORES
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part in
slave mode with the M/S pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal opera-
tion can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the IDT 7006 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
TheIDT7006isanextremelyfastDual-Port16Kx8CMOS
Static RAM with an additional 8 address locations dedicated
tobinarysemaphoreflags. Theseflagsalloweitherprocessor
on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer’s software. As an example, the semaphore
can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
thattheactivityontheleftportinnowayslowstheaccesstime
oftherightport. Bothportsareidenticalinfunctiontostandard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
anon-semaphorelocation. Semaphoresareprotectedagainst
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT7006 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAMs array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7006 RAM the busy pin is
an output if the part is used as a master (M/Spin = H), and the
busy pin is an input if the part used as a slave (M/Spin = L) as
shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busyononeothersideofthearray. Thiswouldinhibitthewrite
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enableandaddresssignalsonly. Itignoreswhetheranaccess
is a read or write. In a master/slave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiated with the R/Wsignal. Failure to observe this timing can
result in a glitched internal write inhibit signal and corrupted
Systems which can best use the IDT7006 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT7006s hardware semaphores, which pro-
vide a lockout mechanism without requiring complex pro-
gramming.
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT7006 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
6.07
17
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
system architecture.
valueislatchedintooneside’soutputregisterwhenthatside's
An advantage of using semaphores rather than the more semaphore select (SEM) and output enable (OE) signals go
common methods of hardware arbitration is that wait states active. This serves to disallow the semaphore from changing
are never incurred in either processor. This can prove to be state in the middle of a read cycle due to a write cycle from the
a major advantage in very high-speed systems.
other side. Because of this latch, a repeated read of a
semaphoreinatestloopmustcauseeithersignal(SEMorOE)
to go inactive or the output will never change.
HOW THE SEMAPHORE FLAGS WORK
A sequence WRITE/READ must be used by the sema-
phore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READ/WRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a sema-
phore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
andtheothersidehigh. Thisconditionwillcontinueuntilaone
is written to the same semaphore request latch. Should the
other side’s semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side’s
request latch. The second side’s flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provideahardwareassistforauseassignmentmethodcalled
“Token Passing Allocation.” In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
overthesharedresource. Ifitwasnotsuccessfulinsettingthe
latch, it determines that the right side processor has set the
latchfirst, hasthetokenandisusingthesharedresource. The
left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT7006 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
eithersidethroughaddresspinsA0–A2. Whenaccessingthe
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If
a low level is written into an unused semaphore location, that
flagwillbesettoazeroonthatsideandaoneontheotherside
(see Table III). That semaphore can now only be modified by
thesideshowingthezero. Whenaoneiswrittenintothesame
locationfromthesameside,theflagwillbesettoaoneforboth
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communica-
tions. (Athoroughdiscussingontheuseofthisfeaturefollows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming tech-
nique, if semaphores are misused or misinterpreted, a soft-
ware error can easily happen.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
6.07
18
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Initialization of the semaphores is not automatic and must processors to swap 8K blocks of Dual-Port RAM with each
be handled via the initialization program at power-up. Since other.
any semaphore request flag which contains a zero must be
The blocks do not have to be any particular size and can
reset to a one, all semaphores on both sides should have a even be variable, depending upon the complexity of the
one written into them at initialization from both sides to assure software using the semaphore flags. All eight semaphores
that they will be free when needed.
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be as-
signed different meanings on different sides rather than being
given a common meaning as was shown in the example
above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
ofmemoryduringatransferandtheI/Odevicecannottolerate
any wait states. With the use of semaphores, once the two
deviceshasdeterminedwhichmemoryareawas“off-limits”to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory “WAIT” state is available on one or both sides. Once
a semaphore handshake has been performed, both proces-
sors can access their assigned RAM segments at full speed.
Another application is in the area of complex data struc-
tures. In this case, block arbitration is very important. For this
applicationoneprocessormayberesponsibleforbuildingand
updating a data structure. The other processor then reads
andinterpretsthatdatastructure. Iftheinterpretingprocessor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processortocomebackandreadthecompletedatastructure,
thereby guaranteeing a consistent data structure.
USING SEMAPHORES—SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7006’s Dual-Port
RAM. Say the 16K x 8 RAM was to be divided into two 8K x
8 blocks which were to be dedicated at any one time to
servicing either the left or right port. Semaphore 0 could be
usedtoindicatethesidewhichwouldcontrolthelowersection
of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 8K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore 0. If this task were success-
fully completed (a zero was read back rather than a one), the
left processor would assume control of the lower 8K. Mean-
while the right processor was attempting to gain control of the
resource after the left processor, it would read back a one in
response to the zero it had attempted to write into Semaphore
0. At this point, the software could choose to try and gain
controlofthesecond8Ksectionbywriting,thenreadingazero
into Semaphore 1. If it succeeded in gaining control, it would
lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
D0
D0
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
2739 drw 20
Figure 4. IDT7006 Semaphore Logic
6.07
19
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
B
Commercial (0°C to +70°C)
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
PF
G
J
64-pin TQFP (PN64-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
68-pin Flatpack (F68-1)
F
Commercial Only
Commercial Only
15
17
20
25
35
55
70
Speed in nanoseconds
Military Only
S
L
Standard Power
Low Power
7006 128K (16K x 8) Dual-Port RAM
2739 drw 21
6.07
20
IDT7006S15PFB 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
IDT7006S17F | IDT | HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM | 获取价格 | |
IDT7006S17FB | IDT | HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM | 获取价格 | |
IDT7006S17G | IDT | HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM | 获取价格 | |
IDT7006S17GB | IDT | HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM | 获取价格 | |
IDT7006S17GG | IDT | Dual-Port SRAM, 16KX8, 17ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, GREEN, CERAMIC, PGA-68 | 获取价格 | |
IDT7006S17J | IDT | HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM | 获取价格 | |
IDT7006S17J8 | IDT | Dual-Port SRAM, 16KX8, 17ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68 | 获取价格 | |
IDT7006S17JB | IDT | HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM | 获取价格 | |
IDT7006S17PF | IDT | HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM | 获取价格 | |
IDT7006S17PF9 | IDT | Dual-Port SRAM, 16KX8, 17ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-64 | 获取价格 |
IDT7006S15PFB 相关文章
- 2024-10-31
- 6
- 2024-10-31
- 6
- 2024-10-31
- 7
- 2024-10-31
- 8