IDT7008L55PFGB中文资料_数据手册_规格书

HIGH-SPEED

IDT7008S/L

64K x 8 DUAL-PORT

STATIC RAM

Features

◆

IDT7008 easily expands data bus width to 16 bits or

more using the Master/Slave select when cascading more

than one device

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Interrupt Flag

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

– Military:25/35/55ns(max.)

– Industrial:55ns (max.)

– Commercial:20/25/35/55ns(max.)

Low-power operation

◆

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

– IDT7008S

Active:750mW(typ.)

Standby: 5mW (typ.)

– IDT7008L

Active:750mW(typ.)

Standby: 1mW (typ.)

Dual chip enables allow for depth expansion without

external logic

◆

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

FunctionalBlockDiagram

R/WL

CE_0L

CE1L

R/W^R

CE0R

CE_1R

OE_L

OE_R

I/O

Control

I/O

Control

I/O0-7L

I/O_0-7R

(1,2)

BUSY_L

(1,2)

BUSY_R

64Kx8

MEMORY

ARRAY

7008

A15L

A^15R

Address

Decoder

Address

Decoder

A0R

A0L

16

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE_0L

CE_0R

1L

CE

1R

CE

OEL

OER

L

R/

W

R

R/W

SEM_L

INT_L

SEM^R

INTR

(2)

M/S⁽¹⁾

3198 drw 01

NOTES:

1. BUSY is an input as a Slave (M/S = V^IL) and an output when it is a Master (M/S = VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

MAY 2000

1

DSC 3198/6

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Description

The IDT7008 is a high-speed 64K x 8 Dual-Port Static RAM. The reads or writes to any location in memory. An automatic power down

IDT7008isdesignedtobeusedasastand-alone512K-bitDual-PortRAM featurecontrolledbythe chipenables(CE⁰andCE1)permittheon-chip

orasacombinationMASTER/SLAVEDual-PortRAMfor16-bit-or-more circuitry of each port to enter a very low standby power mode.

wordsystems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproach

FabricatedusingIDT’sCMOShigh-performancetechnology,these

in16-bitorwidermemorysystemapplicationsresultsinfull-speed,error- devices typicallyoperate ononly750mWofpower.

freeoperationwithouttheneedforadditionaldiscretelogic.

TheIDT7008ispackagedina84-pinCeramicPinGridArray(PGA),

This device provides two independent ports with separate control, a84-pinPlasticLeadlessChipCarrier(PLCC)anda100-pinThinQuad

address,andI/Opinsthatpermitindependent,asynchronousaccessfor Flatpack(TQFP).

PinConfigurations^(1,2,3)

INDEX

11 10 9

8

7

6

5

4

3

2

1 84 83 82 81 80 79 78 77 76 75

74

A6R

A5R

A4R

A3R

A2R

A1R

A0R

NC

12

13

14

15

16

17

I/O7R

I/O6R

I/O5R

I/O4R

I/O3R

Vcc

73

72

71

70

69

68

67

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

R

S

INT

I/O2R

I/O1R

I/O0R

GND

Vcc

IDT7008J

J84-1

BUSY

(4)

66

65

64

63

62

61

M/

84-Pin PLCC

GND

BUSYL

INTL

NC

(5)

Top View

I/O0L

I/O1L

GND

I/O2L

I/O3L

I/O4L

I/O5L

I/O6L

I/O7L

A0L

60

59

58

57

56

55

54

A1L

A2L

A3L

A4L

A5L

A6L

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

,

3198 drw 02

NOTES:

1. This text does not indicate orientation of the actual part marking.

2. All Vcc pins must be connected to power supply.

3. Package body is approximately 1.15 in x 1.15 in x .17 in.

4. This package code is used to reference the package diagram.

5. All GND pins must be connected to ground supply.

2

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Pin Configurations^(1,2,3)(con't.)

Index

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

1

NC

A7L

A8L

A9L

A10L

A11L

A12L

A13L

A14L

A15L

NC

75

NC

A7R

A8R

2

74

73

72

71

70

69

68

67

66

65

64

63

3

4

5

A9R

6

A10R

A11R

A12R

A13R

A14R

A15R

NC

GND

NC

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

IDT7008PF

PN100-1

(

4)

100-Pin TQFP

Vcc

NC

(5)

Top View

62

61

60

59

58

57

56

55

54

53

52

51

NC

CE0L

CE1L

SEML

CE0R

CE1R

SEMR

R/WR

OER

GND

NC

WL

R/

OEL

GND

NC

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

,

3198 drw 03

NOTES:

1. This text does not indicate orientation of the actual part marking.

2. All Vcc pins must be connected to power supply.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. All GND pins must be connected to ground supply.

3

6.42

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Pin Configurations^(1,2,3)(con't)

63

66

67

61

64

65

68

71

60

58

55

54

49

51

50

48

46

45

42

40

GND

11

10

09

08

A7R

A4R

A3R

A1R

A9R

A6R

A5R

A2R

A10R

A12R

A15R

SEMR OER

NC

62

59

56

47

44

43

A8R

A11R

A14R

CE0R R/WR

GND

NC

I/O6R

CE1R

57

53

52

41

39

A13R

GND

NC

I/O7R I/O5R

69

72

38

37

I/O4R I/O3R

73

74

33

35

34

BUSYR

M/S

INTR

I/O0R

I/O2R I/O1R

07

06

IDT7008G

G84-3

75

70

32

31

36

30

(4)

GND

BUSY

A0R

Vcc

L

84-Pin PGA

Top View

(5)

76

77

78

28

29

INTL

A

0L

NC

I/O1L

I/O0L

GND

05

04

79

80

26

27

A1L

A2L

A5L

A7L

I/O3L I/O2L

81

83

1

7

8

9

11

10

15

12

23

25

03

02

01

NC

A3L

A13L

A14L

Vcc

NC

I/O6L I/O4L

82

2

4

5

6

14

17

20

22

24

A4L

A8L

A11L

CE0L R/WL

GND I/O7L I/O5L

84

3

13

16

18

19

21

A6L

A9L

B

A10L

C

A12L

D

A15L

E

NC

G

SEML

OEL

GND

NC

L

CE

1L

,

A

F

H

J

K

3198 drw 04

INDEX

NOTES:

1. All Vcc pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 1.12 in x 1.12 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part marking.

PinNames

Left Port

Right Port

Names

Chip Enables

Read/Write Enable

Output Enable

Address

CE^0L

1L

CE^0R

1R

, CE

W^L

R/

W^R

R/

OE^L

A^0L- A^15L

OE^R

A^0R- A^15R

0L

7L

0R

7R

I/O - I/O

Data Input/Output

Semaphore Enable

Interrupt Flag

Busy Flag

SEM^L

INT^L

SEM^R

INT^R

BUSY^R

S

BUSY^L

M/

Master or Slave Select

Power

CC

V

GND

Ground

3198 tbl 01

4

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table I: Chip Enable⁽¹⁾

1

CE

CE⁰

Mode

V^IL

V^IH

Port Selected (TTL Active)

L

< 0.2V

V^IH

>V^CC-0.2V

X

Port Selected (CMOS Active)

Port Deselected (TTL Inactive)

Port Deselected (CMOS Inactive)

X

V^IL

H

>V^CC-0.2V

X

<0.2V

3198 tbl 02

NOTES:

1. Chip Enable references are shown above with the actual CE⁰and CE1 levels, CE is a reference only.

Truth Table II: Non-Contention Read/Write Control

Inputs⁽¹⁾

Outputs

CE⁽²⁾

H

OE

SEM

H

R/W

X

I/O^0-7

Mode

X

L

High-Z

DATA^IN

Deselected: Power-Down

Write to memory

L

H

L

H

DATA^OUTRead memory

High-Z Outputs Disabled

X

H

X

3198 tbl 03

NOTES:

1. A^0L– A15L ≠ A0R – A15R.

2. Refer to Chip Enable Truth Table.

Truth Table III: Semaphore Read/Write Control⁽¹⁾

Inputs

Outputs

(2)

R/W

I/O^0-7

Mode

CE

OE

SEM

H

L

DATA^OUTRead Semaphore Flag Data Out

H

L

↑

X

L

DATA^IN

Write I/O⁰into Semaphore Flag

Not Allowed

______

X

3198 tbl 04

NOTES:

1. There are eight semaphore flags written to via I/O⁰and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2.

2. Refer to Chip Enable Truth Table.

5

6.42

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AbsoluteMaximumRatings⁽¹⁾

RecommendedDCOperating

Conditions

Symbol

Rating

Commercial

& Industrial

Military

Unit

Symbol

Parameter

Min.

4.5

0

Typ.

Max. Unit

(2)

VTERM

Terminal Voltage

with Respect

to GND

-0.5 to +7.0

V

V^CC

Supply Voltage

5.0

5.5

0

V

GND Ground

0

TBIAS

TSTG

Temperature

Under Bias

-55 to +125

-65 to +150

50

-65 to +135

-65 to +150

50

^oC

(2)

____

V^IH

V^IL

Input High Voltage

Input Low Voltage

2.2

6.0

Storage

Temperature

(1)

____

-0.5

0.8

V

3198 tbl 07

IOUT

DC Output Current

mA

NOTES:

1. V^IL> -1.5V for pulse width less than 10ns.

2. V^TERMmust not exceed Vcc + 10%.

3198 tbl 05

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those

indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect

reliability.

Capacitance

(TA = +25°C, f = 1.0mhz) (TQFP Only)

2. V^TERMmust not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.

Symbol

Parameter⁽¹⁾

Input Capacitance

Output Capacitance

Conditions⁽²⁾

IN = 3dV

OUT = 3dV

Max. Unit

CIN

V

9

pF

COUT

V

10

pF

MaximumOperatingTemperature

andSupplyVoltage^(1,2)

Ambient

3198 tbl 08

NOTES:

1. This parameter is determined by device characterization but is not production

tested.

2. 3dV represents the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

Grade

Temperature

-55^OC to+125^OC

0^OC to +70^OC

-40^OC to +85^OC

GND

Vcc

Military

0V

5.0V + 10%

Commercial

Industrial

0V

3198 tbl 06

NOTES:

1. This is the parameter T^A. This is the "instant on" case tempreature.

2. Industrial Temperature: for other speeds, packages and powers contact your

sales office.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range⁽²⁾(VCC = 5.0V ± 10%)

7008S

7008L

Symbol

Parameter

Input Leakage Current⁽¹⁾

Output Leakage Current

Output Low Voltage

Test Conditions

VCC = 5.5V, VIN = 0V to VCC

Min.

Max.

10

Min.

Max.

Unit

µA

V

___

|ILI|

5

___

|ILO

|

10

CE = VIH, VOUT = 0V to VCC

IOL = 4mA

VOL

VOH

0.4

___

Output High Voltage

IOH = -4mA

2.4

V

3198 tbl 09

NOTES:

1. At Vcc < 2.0V, input leakages are undefined.

2. Refer to Chip Enable Truth Table.

6

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range^(1,6,7)(VCC = 5.0V ± 10%)

7008X20

Com'l Only

7008X25

Com'l &

Military

Symbol

Parameter

Dynamic Operating

Current

(Both Ports Active)

Test Condition

Version

COM'L

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

CC

I

S

L

190

180

325

285

180

170

305

265

mA

IL

CE = V , Outputs Disabled

IH

SEM = V

(3)

MAX

f = f

___

MIL &

IND

S

L

170

345

305

SB1

I

Standby Current

(Both Ports - TTL Level

Inputs)

COM'L

S

L

50

90

70

40

85

60

mA

L

R

IH

CE = CE = V

R

L

IH

SEM = SEM = V

(3)

MAX

f = f

___

MIL &

IND

S

L

40

100

80

(5)

IH

SB2

I

Standby Current

(One Port - TTL Level

Inputs)

"A"

IL

"B"

COM'L

S

L

115

215

185

105

200

170

CE = V and CE = V

Active Port Outputs Disabled,

(3)

MAX

f=f

___

R

L

IH

MIL &

IND

S

L

105

230

200

SEM = SEM = V

SB3

I

L

Full Standby Current

(Both Ports - All CMOS

Level Inputs)

Both Ports CE and

COM'L

S

L

1.0

0.2

15

5

1.0

0.2

15

5

R

CC

CE > V - 0.2V

IN

V

> V - 0.2V or

< 0.2V, f = 0

___

(4)

MIL &

IND

S

L

1.0

0.2

30

10

V

R

L

CC

SEM = SEM > V - 0.2V

SB4

I

Full Standby Current

(One Port - All CMOS

Level Inputs)

COM'L

S

L

110

190

160

100

170

145

"A"

CE < 0.2V and

(5)

"B"

CC

CE > V - 0.2V

R

L

CC

SEM = SEM > V - 0.2V

___

MIL &

IND

S

L

100

200

175

IN

CC

IN

V

> V - 0.2V or V < 0.2V

Active Port Outputs Disabled

f = f

(3)

MAX

3198 tbl 10a

7008X35

Com'l &

Military

7008X55

Com'l, Ind

& Military

Symbol

Parameter

Test Condition

Version

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

CC

I

Dynamic Operating Current

(Both Ports Active)

COM'L

S

L

160

295

255

150

270

230

mA

IL

CE = V , Outputs Disabled

IH

SEM = V

(3)

MAX

f = f

MIL &

IND

S

L

160

335

295

150

310

270

SB1

I

Standby Current

(Both Ports - TTL Level

Inputs)

COM'L

S

L

30

85

60

20

85

60

mA

L

R

IH

CE = CE = V

R

L

IH

SEM = SEM = V

MIL &

IND

S

L

20

100

80

13

100

80

(5)

IH

SB2

I

Standby Current

(One Port - TTL Level

Inputs)

COM'L

S

L

95

185

155

85

165

135

"A"

IL

"B"

CE = V and CE = V

Active Port Outputs Disabled,

(3)

MAX

f=f

MIL &

IND

S

L

95

215

185

85

195

165

R

L

IH

SEM = SEM = V

SB3

L

I

Full Standby Current

(Both Ports - All CMOS

Level Inputs)

Both Ports CE and

mA

COM'L

S

L

1.0

0.2

15

5

1.0

0.2

15

5

R

CC

CE > V - 0.2V

IN

V

CC

V

> V - 0.2V or

(4)

MIL &

IND

S

L

1.0

0.2

30

10

1.0

0.2

30

10

< 0.2V, f = 0

R

L

CC

SEM = SEM > V - 0.2V

SB4

I

Full Standby Current

(One Port - All CMOS

Level Inputs)

"A"

"B"

COM'L

S

L

90

160

135

80

135

110

CE < 0.2V and

(5)

CC

CE > V - 0.2V

R

L

CC

SEM = SEM > V - 0.2V

IN

V

CC

IN

MIL &

IND

S

L

90

190

165

80

175

150

> V - 0.2V or V < 0.2V

Active Port Outputs Disabled

(3)

MAX

f = f

3198 tbl 10b

NOTES:

1. 'X' in part numbers indicates power rating (S or L)

2. V^CC= 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

3. At f = f^MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input

levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6. Refer to Chip Enable Truth Table.

7. Industrial Temperature: for other speeds, packages and powers contact your sales office.

7

6.42

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

5V

AC Test Conditions

Input Pulse Levels

GND to 3.0V

5ns Max.

1.5V

893Ω

Ω

893

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

DATAOUT

BUSY

INT

DATAOUT

1.5V

30pF

5pF*

347Ω

347

Ω

Figures 1 and 2

3198 tbl 11

3198 drw 05

3198 drw 06

Figure 2. Output Test Load

(for t^LZ, tHZ, tWZ, tOW)

Figure 1. AC Output Test Load

* Including scope and jig.

Waveform of Read Cycles⁽⁵⁾

tRC

ADDR

(4)

tAA

(4)

tACE

CE⁽⁶⁾

(4)

t_AOE

OE

R/W

(1)

tOH

tLZ

VALID DATA⁽⁴⁾

DATAOUT

(2)

tHZ

BUSYOUT

(3,4)

3198 drw 07

tBDD

Timing of Power-Up Power-Down

CE⁽⁶⁾

PU

t

PD

t

I

CC

I

SB

,

3198 drw 08

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

3. t^BDDdelay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last t^AOE, tACE, tAA or tBDD.

5. SEM = V^IH.

6. Refer to Chip Enable Truth Table.

8

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange^(6,7)

7008X20

Com'l Only

7008X25 Com'l 7008X35 Com'l

& Military & Military

7008X55

Com'l, Ind

& Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

t^RC

Read Cycle Time

20

25

35

55

ns

____

t^AA

Address Access Time

20

25

35

55

Chip Enable Access Time⁽⁴⁾

Output Enable Access Time

____

t^ACE

t^AOE

t^OH

t^LZ

12

13

20

30

____

Output Hold from Address Change

Output Low-Z Time^(1,2)

3

____

3

Output High-Z Time^(1,2)

12

15

25

____

t^HZ

t^PU

t^PD

t^SOP

t^SAA

Chip Enab le to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

Semaphore Flag Update Pulse (OE or SEM)

Semaphore Address Access Time

0

____

20

25

35

50

____

10

12

15

____

20

25

35

55

ns

3198 tbl 12

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltage^(6,7)

7008X20

Com'l Only

7008X25

Com'l &

Military

7008X35

Com'l &

Military

7008X55

Com'l, Ind

& Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

t^WC

t^EW

t^AW

t^AS

Write Cycle Time

20

15

0

25

20

0

35

30

0

55

45

0

ns

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

t^WP

15

0

20

0

25

0

40

0

t^WR

t^DW

t^HZ

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁵⁾

15

30

____

12

15

25

____

t^DH

0

(1,2)

____

t^WZ

t^OW

t^SWRD

t^SPS

Write Enable to Output in High-Z

Output Active from End-of-Write^{(1, 2,5 )}

SEM Flag Write to Read Time

SEM Flag Contention Window

12

15

25

____

0

5

0

5

0

5

0

5

____

ns

3198 tbl 13

NOTES:

1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranted by device characterization, but is not production tested.

3. To access RAM, CE= V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. To access RAM, CE = V^ILand SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.

5. The specification for t^DHmust be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage

and temperature, the actual t^DHwill always be smaller than the actual tOW.

6. 'X' in part numbers indicates power rating (s or L).

7. Industrial Temperature: for other speeds, packages and powers contact your sales office.

9

6.42

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(1,5,8)

tWC

ADDRESS

(7)

tHZ

OE

tAW

CE or SEM^(9,10)

(3)

(2)

(6)

tWP

tWR

tAS

R/W

DATAOUT

DATAIN

(7)

tWZ

tOW

(4)

tDW

tDH

3198 drw 09

Timing Waveform of Write Cycle No. 2, CE Controlled Timing^(1,5)

t_WC

ADDRESS

t_AW

(9,10)

or

CE SEM

(3)

WR

(6)

(2)

t

EW

t_AS

R/

W

t

DW

t

DH

DATA_IN

3198 drw 10

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (t^EWor tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

3. t^WRis measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure

2).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t^WPor (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required t^DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as

the specified t^WP.

9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

10. Refer to Chip Enable Truth Table.

10

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾

tSAA

tOH

A0-A2

VALID ADDRESS

tACE

tAW

tWR

tEW

SEM

tDW

DATAIN VALID

tSOP

DATAOUT

VALID⁽²⁾

DATA0

tAS

tWP

tDH

R/W

tSWRD

tAOE

OE

tSOP

Write Cycle

Read Cycle

3198 drw 11

NOTES:

1. CE = V^IHfor the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).

2. "DATA^OUTVALID" represents all I/O's (I/O0 - I/O15) equal to the semaphore value.

Timing Waveform of Semaphore Write Contention^(1,3,4)

A0"A"-A2"A"

MATCH

SIDE⁽²⁾"A"

R/W"A"

SEM"A"

SPS

t

A0"B"-A2"B"

MATCH

SIDE⁽²⁾

"B"

R/W

"B"

SEM"B"

3198 drw 12

NOTES:

1. D^OR= DOL = VIL, CEL = CER = VIH (Refer to Chip Enable Truth Table).

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from R/W^"A"or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If t^SPSis not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

11

6.42

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange^(6,7)

7008X20

Com'l Only

7008X25

Com'l &

Military

7008X35

Com'l &

Military

7008X55

Com'l, Ind &

Military

Symbol

BUSY TIMING (M/S=V )

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Unit

IH

____

t^BAA

t_BDA

t^BAC

t^BDC

t^APS

t^BDD

t^WH

20

45

40

ns

BUSY Access Time from Address Match

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable Low

BUSY Access Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

17

20

35

____

5

____

BUSY Disable to Valid Data⁽³⁾

20

25

35

55

Write Hold After BUSY⁽⁵⁾

15

17

25

____

BUSY TIMING (M/S=V )

IL

BUSY Input to Write⁽⁴⁾

Write Hold After BUSY⁽⁵⁾

PORT-TO-PORT DELAY TIMING

t^WDD

Write Pulse to Data Delay⁽¹⁾

t^DDD

Write Data Valid to Read Data Delay⁽¹⁾

____

t^WB

0

ns

t_WH

15

17

25

____

45

30

50

35

60

45

80

65

ns

3198 tbl 14

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V^IH)".

2. To ensure that the earlier of the two ports wins.

3. t^BDDis a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 'X' in part numbers indicates power rating (S or L).

7. Industrial Temperature: for other speeds, packages and powers contact your sales office.

12

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

TimingWaveformof WritewithPort-to-PortReadandBUSY^(2,5)(M/S = VIH)⁽⁴⁾

t_WC

ADDR_"A"

MATCH

t_WP

R/

W"A"

t_DH

t_DW

DATA_{IN "A"}

VALID

(1)

t_APS

ADDR_"B"

MATCH

t_BDA

t_BDD

BUSY"B"

t_WDD

DATA_{OUT "B"}

VALID

(3)

t_DDD

NOTES:

3198 drw 13

1. To ensure that the earlier of the two ports wins. t^APSis ignored for M/S = VIL (SLAVE).

2. CE^L= CER = VIL, refer to Chip Enable Truth Table.

3. OE = V^ILfor the reading port.

4. If M/S = V^IL(SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

Timing Waveform of Write with BUSY (M/S = VIL)

tWP

R/W"A"

(3)

tWB

BUSY"B"

(1)

tWH

R/W"B"

(2)

3198 drw 14

NOTES:

1. t^WHmust be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. t^WBis only for the 'Slave' version.

13

6.42

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing^(1,3)(M/S = VIH)

ADDR"A"

ADDRESSES MATCH

and "B"

CE"A"

(2)

t

APS

CE"B"

t

BAC

t

BDC

BUSY"B"

3198 drw 15

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing⁽¹⁾(M/S = VIH)

"A"

ADDR

ADDRESS "N"

(2)

t

APS

ADDR"B"

MATCHING ADDRESS "N"

t

BAA

t

BDA

BUSY"B"

3198 drw 16

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. If t^APSis not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

3. Refer to Chip Enable Truth Table.

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange^(1,2)

7008X20

Com'l Only

7008X25

Com'l &

Military

7008X35

Com'l &

Military

7008X55

Com'l, Ind

& Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

____

t^AS

Address Set-up Time

Write Recovery Time

0

ns

t^WR

t^INS

t^INR

0

____

Interrupt Set Time

20

25

40

____

Interrupt Reset Time

ns

3198 tbl 15

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

2. Industrial Temperature: for other speeds, packages and powers contact your sales office.

14

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing^(1,5)

t

WC

INTERRUPT SET ADDRESS⁽²⁾

ADDR"A"

(3)

(4)

t

AS

t

WR

CE"A"

R/W"A"

INT"B"

(3)

t

INS

3198 drw 17

t

RC

INTERRUPT CLEAR ADDRESS⁽²⁾

ADDR"B"

t

AS⁽³⁾

CE"B"

"B"

OE

t

INR⁽³⁾

INT"B"

3198 drw 18

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. See Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

5. Refer to Chip Enable Truth Table.

Truth Table IV Interrupt Flag^(1,4,5)

Left Port

Right Port

W_L

R/

W_R

R/

A^15L-A^0L

FFFF

X

A^15R-A^0R

X

Function

CE

L

OE^L

X

INT^L

X

CE

X

L

OE^R

X

INT

R

(2)

L

X

L

Set Right INT Flag

R

(3

)

X

L

X

L

FFFF

FFFE

X

H

Reset Right INT Flag

R

(3)

X

L

X

Set Left INT Flag

L

(2)

L

FFFE

H

X

Reset Left INT Flag

L

3198 tbl 16

NOTES:

1. Assumes BUSY^L= BUSYR =VIH.

2. If BUSY^L= VIL, then no change.

3. If BUSY^R= VIL, then no change.

4. INT^Land INTR must be initialized at power-up.

5. Refer to Chip Enable Truth Table.

15

6.42

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table V Address BUSY

Arbitration⁽⁴⁾

Inputs

Outputs

AOL-A15L

AOR-A15R

(1)

Function

Normal

Write

CE^L

X

CE^R

X

BUSY^L

BUSY^R

NO MATCH

MATCH

H

X

H

MATCH

L

MATCH

(2)

(3)

Inhibit

3198 tbl 17

NOTES:

1. Pins BUSY^Land BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7008 are

push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If t^APSis not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSY^Loutputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSY^Routputs are driving LOW regardless of actual logic level on the pin.

4. Refer to Chip Enable Truth Table.

Truth Table VI Example of Semaphore Procurement Sequence^(1,2,3)

Functions

D⁰- D⁷Left

D⁰- D⁷Right

Status

No Action

1

0

1

0

1

0

1

0

1

0

1

Semaphore free

Left Port Writes "0" to Semaphore

Right Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "1" to Semaphore

Right Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left port has semaphore token

No change. Right side has no write access to semaphore

Right port obtains semaphore token

No change. Left port has no write access to semaphore

Left port obtains semaphore token

Semaphore free

Right port has semaphore token

Semaphore free

Left port has semaphore token

Semaphore free

3198 tbl 18

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7008.

2. There are eight semaphore flags written to via I/O⁰and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2.

3. CE = V^IH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

FunctionalDescription

TheIDT7008providestwoportswithseparatecontrol,addressand (INTL) is asserted when the right port writes to memory location FFFE

I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation (HEX),whereawriteisdefinedasCER=R/WR=VILpertheTruthTable.

inmemory.TheIDT7008hasanautomaticpowerdownfeaturecontrolled TheleftportclearstheinterruptthroughaccessofaddresslocationFFFE

byCE. TheCE0and CE1 control the on-chip power down circuitry that when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port

permitstherespectiveporttogointoastandbymodewhennotselected interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation

(CEHIGH).Whenaportis enabled,access totheentirememoryarray FFFF(HEX)andtocleartheinterruptflag(INTR),therightportmustread

ispermitted.

thememorylocationFFFF. Themessage(8bits)atFFFEorFFFFisuser-

definedsinceitisanaddressableSRAMlocation.Iftheinterruptfunction

isnotused,addresslocationsFFFEandFFFFarenotusedasmailboxes,

butaspartoftherandomaccessmemory.RefertoTableIVfortheinterrupt

operation.

Interrupts

Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox

ormessagecenter)is assignedtoeachport. Theleftportinterruptflag

16

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

resultina glitchedinternalwrite inhibitsignalandcorrupteddata inthe

slave.

BusyLogic

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.

TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon

theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom

thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally

topreventthewritefromproceeding.

TheuseofBUSYlogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

anduse anyBUSYindicationas aninterruptsource toflagthe eventof

anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis

notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave

modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

TheBUSYoutputsontheIDT7008RAMinmastermode,arepush-

pulltypeoutputsanddonotrequirepullupresistorstooperate.Ifthese

RAMs are being expanded in depth, then the BUSY indication for the

resulting array requires the use of an external AND gate.

Semaphores

TheIDT7008isanextremelyfastDual-Port64Kx8CMOSStaticRAM

withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.

TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port

RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby

thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe

usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe

Dual-Port RAM or any other shared resource.

The Dual-PortRAMfeatures a fastaccess time, andbothports are

completelyindependentofeachother.Thismeansthattheactivityonthe

leftportinnowayslows theaccess timeoftherightport.Bothports are

identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,

orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphorelocation.Semaphoresareprotectedagainstsuchambiguous

situationsandmaybeusedbythesystemprogramtoavoidanyconflicts

inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave

anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM

enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol

on-chippowerdowncircuitrythatpermits the respective porttogointo

standbymodewhennotselected. Thisistheconditionwhichisshownin

Truth Table II where CE and SEM are both HIGH.

A¹⁶

CE⁰

MASTER

Dual Port RAM

SLAVE

Dual Port RAM

BUSY (L) BUSY (R)

SystemswhichcanbestusetheIDT7008containmultipleprocessors

or controllers and are typically very high-speed systems which are

softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom

a per-formance increase offered by the IDT7008s hardware sema-

phores,whichprovidealockoutmechanismwithoutrequiringcomplex

programming.

CE¹

MASTER

Dual Port RAM

SLAVE

Dual Port RAM

BUSY (L) BUSY (R)

,

3198 drw 19

Softwarehandshakingbetweenprocessors offers themaximumin

systemflexibilitybypermittingsharedresourcestobeallocatedinvarying

configurations.TheIDT7008doesnotuseitssemaphoreflagstocontrol

anyresourcesthroughhardware,thusallowingthesystemdesignertotal

flexibilityinsystemarchitecture.

An advantage of using semaphores rather than the more common

methodsofhardwarearbitrationisthatwaitstatesareneverincurredin

either processor. This can prove to be a major advantage in very high-

speedsystems.

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT7008 RAMs.

WidthExpansionBusyLogic

Master/SlaveArrays

WhenexpandinganIDT7008RAMarrayinwidthwhileusingBUSY

logic,onemasterpartisusedtodecidewhichsideoftheRAMsarraywill

receivea BUSYindication,andtooutputthatindication.Anynumberof

slaves to be addressed in the same address range as the master, use

the BUSYsignalasawriteinhibitsignal.ThusontheIDT7008RAMthe

How the Semaphore Flags Work

Thesemaphorelogicisasetofeightlatcheswhichareindependent

BUSYpinisanoutputifthepartisusedasamaster(M/Spin=VIH),and oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,

theBUSYpinisaninputifthepartusedasaslave(M/Spin=VIL)as shown fromoneporttotheothertoindicatethatasharedresourceisinuse.The

in Figure 3.

semaphores provide a hardware assist for a use assignment method

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore

decisioncouldresultwithonemasterindicatingBUSYononesideofthe latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft

arrayandanothermasterindicatingBUSYononeothersideofthearray. processorwantstousethisresource,itrequeststhetokenbysettingthe

Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword. it. If it was successful, it proceeds to assume control over the shared

TheBUSYarbitration,onamaster,is basedonthechipenableand resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe

address signals only. Itignores whetheranaccess is a readorwrite. In rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe

a master/slave array, both address and chip enable must be valid long sharedresource. Theleftprocessorcantheneitherrepeatedlyrequest

enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite thatsemaphore’sstatusorremoveitsrequestforthatsemaphoretoperform

pulsecanbeinitiatedwiththeR/Wsignal.Failuretoobservethistimingcan anothertaskandoccasionallyattemptagaintogaincontrolofthetokenvia

17

6.42

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

thesetandtestsequence.Oncetherightsidehasrelinquishedthetoken, side during subsequent read. Had a sequence of READ/WRITE been

theleftsideshouldsucceedingainingcontrol. usedinstead,systemcontentionproblemscouldhaveoccurredduringthe

ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting gap between the read and write cycles.

azerointoasemaphorelatchandisreleasedwhenthesamesidewrites

aonetothatlatch.

Itisimportanttonotethatafailedsemaphorerequestmustbefollowed

byeitherrepeatedreadsorbywritingaoneintothesamelocation.The

The eightsemaphore flags reside withinthe IDT7008ina separate reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram

memoryspacefromtheDual-PortRAM.This addressspaceisaccessed ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed

byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe into a semaphore flag. Whichever latch is first to present a zero to the

semaphore flags) and using the other control pins (Address, CE, and semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother

R/W)as theywouldbeusedinaccessingastandardStaticRAM.Each sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame

oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch

throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip

theotheraddresspinshasanyeffect.

Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel

L PORT

R PORT

iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero

onthatsideandaoneontheotherside(seeTableVI).Thatsemaphore

can now only be modified by the side showing the zero. When a one is

writtenintothesamelocationfromthesameside,theflagwillbesettoa

one for both sides (unless a semaphore request from the other side is

pending)andthencanbewrittentobybothsides.Thefactthattheside

whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites

fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor

communications.(Athoroughdiscussionontheuseofthisfeaturefollows

shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe

storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis

freedbythefirstside.

Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso

thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining

azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput

registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)

signalsgoactive.Thisservestodisallowthesemaphorefromchanging

stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.

Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust

cause either signal (SEM or OE) to go inactive or the output will never

change.

AsequenceWRITE/READmustbeusedbythesemaphoreinorder

to guarantee that no system level contention will occur. A processor

requestsaccesstosharedresourcesbyattemptingtowriteazerointoa

semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore

requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,

afactwhichtheprocessorwillverifybythesubsequentread(seeTable

VI). As anexample, assume a processorwrites a zerotothe leftportat

afreesemaphorelocation.Onasubsequentread,theprocessorwillverify

thatithaswrittensuccessfullytothatlocationandwillassumecontrolover

the resource in question. Meanwhile, if a processor on the right side

attempts towriteazerotothesamesemaphoreflagitwillfail,as willbe

verifiedbythefactthataonewillbereadfromthatsemaphoreontheright

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

D0

D

Q

WRITE

SEMAPHORE

READ

SEMAPHORE

,

READ

3198 drw 20

Figure 4. IDT7008 Semaphore Logic

overtotheothersideassoonasaoneiswrittenintothefirstside’srequest

latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest

latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore

is requestedandthe processorwhichrequesteditnolongerneeds the

resource, the entire system can hang up until a one is written into that

semaphorerequestlatch.

The criticalcase ofsemaphore timingis whenbothsides requesta

single token by attempting to write a zero into it at the same time. The

semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-

neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives

thetoken.Ifonesideisearlierthantheotherinmakingtherequest,thefirst

sidetomaketherequestwillreceivethetoken.Ifbothrequestsarriveat

thesametime,theassignmentwillbearbitrarilymadetooneportorthe

other.

One caution that should be noted when using semaphores is that

semaphoresalonedonotguaranteethataccesstoaresourceissecure.

Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused

ormisinterpreted, a software errorcaneasilyhappen.

Initializationofthesemaphoresisnotautomaticandmustbehandled

viatheinitializationprogramatpower-up.Sinceanysemaphorerequest

flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth

sidesshouldhaveaonewrittenintothematinitializationfrombothsides

to assure that they will be free when needed.

18

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

OrderingInformation

IDT XXXXX

A

999

A

Device

Type

Power

Speed

Package

Process/

Temperature

Range

Blank

I⁽¹⁾

B

Commercial (0°C to +70°C)

Industrial (-40°C to + 85°C)

Military (-55°C to +125°C)

Compliant to MIL-PRF-38535 QML

PF

G

J

100-pin TQFP (PN100-1)

108-pin PGA (G108-1)

84-pin PLCC (J84-1)

Commercial Only

Commercial & Military

Commercial, Industrial

& Military

20

25

35

55

Speed in

nanoseconds

,

Standard Power

Low Power

S

L

512K (64K x 8) Dual-Port RAM

7008

3198 drw 21

NOTE:

1. IndustrialtemperaturerangeisavailableonselectedTQFPpackagesinstandardpower.

Forotherspeeds,packagesandpowerscontactyoursalesoffice.

DatasheetDocumentHistory

1/6/99:

Initiateddatasheetdocumenthistory

Convertedtonewformat

Cosmeticandtypographicalcorrections

Pages2and3Addedadditionalnotestopinconfigurations

Changeddrawingformat

6/3/99:

11/10/99:

5/8/99:

Replaced IDT logo

Page 6 Increasedstoragetemperatureparameter

ClarifiedTAparameter

Page 7 DCElectricalparamters–changedwordingfrom"open"to"disabled"

Changed±200mVto0mVinnotes

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

831-754-4613

DualPortHelp@idt.com

800-345-7015 or 408-727-5166

fax: 408-492-8674

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

19

6.42

型号	制造商	描述	价格	文档
IDT7008L55PFGI	IDT	Dual-Port SRAM, 64KX8, 55ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	获取价格
IDT7008L55PFI	IDT	HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM	获取价格
IDT7008S	IDT	HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM	获取价格
IDT7008S15G	IDT	Dual-Port SRAM, 64KX8, 15ns, CMOS, CPGA84, 1.12 X 1.12 INCH, 0.16 INCH HEIGHT, PGA-84	获取价格
IDT7008S15GG	IDT	Dual-Port SRAM, 64KX8, 15ns, CMOS, 1.12 X 1.12 INCH, 0.16 INCH HEIGHT, PGA-108	获取价格
IDT7008S15J	IDT	Dual-Port SRAM, 64KX8, 15ns, CMOS, PQCC84, 1.15 X 1.15 INCH, 0.17 INCH HEIGHT, PLASTIC, LCC-84	获取价格
IDT7008S15PF	IDT	Dual-Port SRAM, 64KX8, 15ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	获取价格
IDT7008S15PF8	IDT	Dual-Port SRAM, 64KX8, 15ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100	获取价格
IDT7008S20G	IDT	HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM	获取价格
IDT7008S20GB	IDT	HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM	获取价格

IDT7008L55PFGB

IDT7008L55PFGB 概述

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