概述
规格参数
数据手册IDT7016S15J 概述
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM 高速16K ×9双端口静态RAM 存储芯片 SRAM
IDT7016S15J 规格参数
| 是否无铅： | 含铅 | 是否Rohs认证： | 不符合 |
| 生命周期： | Obsolete | 零件包装代码： | LCC |
| 包装说明： | PLASTIC, LCC-68 | 针数： | 68 |
| Reach Compliance Code： | not_compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.32.00.41 | 风险等级： | 5.84 |
| 最长访问时间： | 15 ns | 其他特性： | SEMAPHORE; INTERRUPT FLAG; AUTOMATIC POWER DOWN; LOW POWER STANDBY MODE |
| I/O 类型： | COMMON | JESD-30 代码： | S-PQCC-J68 |
| JESD-609代码： | e0 | 长度： | 24.2062 mm |
| 内存密度： | 147456 bit | 内存集成电路类型： | DUAL-PORT SRAM |
| 内存宽度： | 9 | 湿度敏感等级： | 1 |
| 功能数量： | 1 | 端口数量： | 2 |
| 端子数量： | 68 | 字数： | 16384 words |
| 字数代码： | 16000 | 工作模式： | ASYNCHRONOUS |
| 最高工作温度： | 70 °C | 最低工作温度： | |
| 组织： | 16KX9 | 输出特性： | 3-STATE |
| 可输出： | YES | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | QCCJ | 封装等效代码： | LDCC68,1.0SQ |
| 封装形状： | SQUARE | 封装形式： | CHIP CARRIER |
| 并行/串行： | PARALLEL | 峰值回流温度（摄氏度）： | 225 |
| 电源： | 5 V | 认证状态： | Not Qualified |
| 座面最大高度： | 4.57 mm | 最大待机电流： | 0.015 A |
| 最小待机电流： | 4.5 V | 子类别： | SRAMs |
| 最大压摆率： | 0.31 mA | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 4.5 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | COMMERCIAL | 端子面层： | Tin/Lead (Sn85Pb15) |
| 端子形式： | J BEND | 端子节距： | 1.27 mm |
| 端子位置： | QUAD | 处于峰值回流温度下的最长时间： | 30 |
| 宽度： | 24.2062 mm | Base Number Matches： | 1 |
IDT7016S15J 数据手册
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IDT7016S/L
16K x 9 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than
2001V electrostatic discharge
— Military: 20/25/35ns (max.)
— Commercial:12/15/20/25/35ns (max.)
• Low-power operation
• TTL-compatible, single 5V (±10%) power supply
• Available in ceramic 68-pin PGA, 68-pin PLCC, and
an 80-pin TQFP
• Industrial temperature range (–40°C to +85°C) is
available, tested to military electrical specifications
— IDT7016S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7016L
Active: 750mW (typ.)
Standby: 1mW (typ.)
DESCRIPTION:
• IDT7016 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading
more than one device
• M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
The IDT7016 is a high-speed 16K x 9 Dual-Port Static
RAMs. The IDT7016 is designed to be used as stand-
alone Dual-Port RAM or as a combination MASTER/
SLAVE Dual-Port RAM for 18-bit-or-more wider systems.
FUNCTIONAL BLOCK DIAGRAM
OER
OEL
CER
CEL
R/WR
R/WL
I/O0L- I/O8L
I/O0R-I/O8R
I/O
Control
I/O
Control
BUSYL(1,2)
(1,2)
BUSYR
A13L
A13R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A0L
A0R
14
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CEL
OEL
CER
OER
R/WR
R/WL
SEML
INTL(2)
SEMR
(2)
INTR
M/
S
3190 drw 01
NOTES:
1. In MASTER mode: BUSY is an output and is a push-pull driver
In SLAVE mode: BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTOBER 1996
©1996 Integrated Device Technology, Inc.
DSC-3190/2
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.13
1
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Using the IDT MASTER/SLAVE Dual-Port RAM approach in standby power mode.
18-bit or wider memory system applications results in full-
Fabricated using IDT’s CMOS high-performance technol-
speed, error-free operation without the need for additional ogy, these devices typically operate on only 750mW of power.
discrete logic.
The IDT7016 is packaged in a ceramic 68-pin PGA, a 64-
This device provides two independent ports with separate pin PLCC and an 80-pin TQFP (Thin Quad FlatPack). Military
control, address, and I/O pins that permit independent, grade product is manufactured in compliance with the latest
asynchronous access for reads or writes to any location in revision of MIL-STD-883, Class B, making it ideally suited to
memory. An automatic power down feature controlled by CE militarytemperatureapplicationsdemandingthehighestlevel
permits the on-chip circuitry of each port to enter a very low of performance and reliability.
PIN CONFIGURATIONS(1,2)
INDEX
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
I/O2L 10
11
I/O4L 12
A
A
A
A
A
A
5L
4L
3L
2L
1L
0L
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O3L
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O5L
GND
I/O6L
I/O7L
INT
BUSY
GND
M/
BUSY
INT
L
IDT7016
J68-1
V
CC
L
PLCC
GND
I/O0R
I/O1R
I/O2R
S
(3)
TOP VIEW
R
R
V
CC
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
1R
2R
3R
4R
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
3190 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not imply orientation of Part-Mark.
PIN NAMES
Left Port
CEL
Right Port
CER
Names
Chip Enable
R/WL
R/WR
Read/Write Enable
Output Enable
Address
OEL
OER
A0L – A13L
I/O0L – I/O8L
SEML
A0R – A13R
I/O0R – I/O8R
SEMR
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
INTL
INTR
BUSYL
BUSYR
M/S
VCC
Master or Slave Select
Power
GND
Ground
3190 tbl 01
6.13
2
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D) (1,2)
INDEX
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC
1
2
NC
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
A
A
A
A
A
A
5L
4L
3L
2L
1L
0L
3
4
5
6
7
IDT7016
PN-80
TQFP
INT
BUSY
GND
M/
BUSY
INT
L
8
L
VCC
9
NC
GND
I/O0R
I/O1R
I/O2R
10
11
12
13
14
15
16
17
18
19
20
S
(3)
TOP VIEW
R
R
A
A
A
A
A
0R
1R
2R
3R
4R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
NC
NC
NC
3190 drw 03
7 R
I / O
51
50
48
A
46
A
44
BUSY
42
M/S
40
INT
38
36
11
10
09
08
07
06
05
04
03
02
01
A
4L
2L
1L
0L
A1R
A
3R
L
R
A
5L
6L
53
A
52
49
47
A
45
INT
43
GND
41
BUSY
39
37
35
34
L
R
A
4R
7L
A
3L
A
0R
A
2R
A
5R
6R
A
55
A
54
32
33
A
A
7R
9L
A
8L
57
A
56
A
30
31
A
9R
A
8R
11L
10L
12L
59
58
A
28
29
A
IDT7016
G68-1
68-PIN PGA
A
11R
10R
12R
V
CC
61
60
26
GND
27
A
N/C
A
13L
63
62
24
N/C
25
(3)
TOP VIEW
A
13R
SEM
L
CE
L
65
64
22
SEM
23
CER
R
OE
L
R/W
L
67
I/O0L
66
20
OE
21
R/WR
R
I/O8L
1
3
5
GND
7
9
68
I/O1L
11
13
V
15
18
I/O7R
19
I/O8R
GND
I/O7L
CC
I/O4L
I/O2L
I/O1R
I/O4R
2
4
6
8
10
12
14
16
17
I/O3L I/O5L I/O6L
I/O0R I/O2R I/O3R I/O5R I/O6R
V
CC
E
A
B
C
D
F
G
H
J
K
L
NOTES:
INDEX
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3190 drw 04
3. This text does not indicate orientation of the actual part-marking.
6.13
3
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
Inputs(1)
Outputs
CE
R/W
OE
X
SEM
H
I/O0-8
Mode
H
X
L
High-Z
Deselected: Power-Down
Write to Memory
L
L
X
H
DATAIN
DATAOUT
High-Z
H
X
L
H
Read Memory
X
H
X
Outputs Disabled
NOTE:
3190 tbl 02
1. Condition: A0L — A13L is not equal to A0R — A13R.
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL(1)
Inputs
Outputs
CE
R/W
OE
L
SEM
I/O0-8
Mode
Read Semaphore Flag Data Out (I/O0 - I/O8)
Write I/O0 into Semaphore Flag
Not Allowed
H
H
H
L
L
L
DATAOUT
DATAIN
—
X
L
X
X
3190 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O8). These eight semaphores are addressed by A0-A2.
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Symbol
Rating
Commercial
Military
Unit
(2)
VTERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0
V
Grade
Military
Commercial
Temperature
–55°C to +125°C
0°C to +70°C
GND
VCC
with Respect
to GND
0V
5.0V ± 10%
TA
Operating
0 to +70
–55 to +125 °C
0V
5.0V ± 10%
Temperature
3190 tbl 05
TBIAS
TSTG
IOUT
Temperature
Under Bias
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
RECOMMENDED DC OPERATING
CONDITIONS
Storage
Temperature
DC Output
Current
50
50
mA
Symbol
Parameter
Supply Voltage
Supply Voltage
Min. Typ. Max. Unit
VCC
4.5
0
5.0
0
5.5
0
V
V
NOTES:
3190 tbl 04
GND
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc
+ 0.5V.
VIH
VIL
Input High Voltage
Input Low Voltage
2.2
–0.5(1)
—
—
6.0(2)
V
V
0.8
NOTES:
3190 tbl 06
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
CAPACITANCE(1)
(TA = +25°C, f = 1.0MHz, TQFP ONLY)
Symbol
CIN
Parameter
Conditions(2) Max. Unit
Input Capacitance
VIN = 3dV
9
pF
COUT
Output Capacitance VOUT = 3dV
10
pF
3190 tbl 07
NOTES:
1. This parameter is determined by device characteristics but is not produc-
tion tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V .
6.13
4
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
7016S
7016L
Symbol
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
CE = VIH, VOUT = 0V to VCC
IOL = 4mA
Min.
—
Max.
10
Min.
Max.
5
Unit
µA
µA
V
|ILI|
—
—
|ILO|
VOL
VOH
—
10
5
—
0.4
—
—
0.4
—
Output High Voltage
IOH = -4mA
2.4
2.4
V
NOTE:
1. At Vcc < 2.0V, Input leakages are undefined.
3190 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%)
7016X12
7016X15
Test
Com'l. Only
Com'l. Only
Symbol
Parameter
Condition
Version
MIL.
Typ.(2) Max. Typ.(2) Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
CE = VIL, Outputs Open
SEM = VIH
S
L
S
L
—
—
—
—
—
—
—
—
mA
mA
mA
mA
(3)
f = fMAX
COM’L.
170
170
325
275
170
170
310
260
ISB1
ISB2
ISB3
Standby Current
(Both Ports — TTL
Level Inputs)
CER = CEL = VIH
MIL.
S
L
S
L
—
—
25
25
—
—
70
60
—
—
25
25
—
—
60
50
SEMR = SEML = VIH
(3)
f = fMAX
COM’L.
(5)
Standby Current
(One Port — TTL
Level Inputs)
CE"A"=VIL and CE"B" = VIH
Active Port Outputs Open
MIL.
S
L
S
L
—
—
105
105
—
—
200
170
—
—
105
105
—
—
190
160
(3)
f = fMAX
COM’L.
SEMR= SEML = VIH
Full Standby Current
(Both Ports — All
CMOS Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
MIL.
S
L
S
L
—
—
1.0
0.2
—
—
15
5
—
—
1.0
0.2
—
—
15
5
COM’L.
SEMR = SEML > VCC - 0.2V
ISB4
Full Standby Current
(One Port — All
CMOS Level Inputs)
CE"A"< 0.2V and
MIL.
S
L
—
—
—
—
—
—
—
—
mA
CE"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
VIN>VCC - 0.2V or VIN<0.2V COM'L.
Active Port Outputs Open,
f = fMAX
S
L
100
100
180
150
100
100
170
140
(3)
NOTES:
3190 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA(typ.)
3. At f = fMAX, address and I/Os are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite of port "A".
6.13
5
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Cont'd) (VCC = 5.0V ± 10%)
7016X20
7016X25
7016X35
Test
Symbol
Parameter
Condition
Version
MIL.
Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit
ICC
Dynamic Operating
Current
CE = VIL, Outputs Open
SEM = VIH
S
L
—
—
—
—
155
155
340
280
150
150
300 mA
250
(3)
(Both Ports Active)
f = fMAX
COM’L.
MIL.
S
L
160
160
290
240
155
155
265
220
150
150
250
210
ISB1
ISB2
Standby Current
(Both Ports — TTL
CEL = CER = VIH
SEMR = SEML = VIH
S
L
—
—
—
—
16
16
80
65
13
13
80 mA
65
(3)
Level Inputs)
f = fMAX
COM’L.
MIL.
S
L
20
20
60
50
16
16
60
50
13
13
60
50
(5)
Standby Current
(One Port — TTL
Level Inputs)
CE"A"=VIL and CE"B"=VIH
S
L
—
—
95
95
—
—
90
90
90
90
215
180
170
140
85
85
85
85
190 mA
160
Active Port Outputs Open
(3)
f = fMAX
COM’L.
S
L
180
150
155
SEMR = SEML = VIH
130
ISB3
ISB4
Full Standby Current
(Both Ports — All
Both Ports CEL and
CER > VCC - 0.2V
MIL.
S
L
—
—
—
—
1.0
0.2
30
10
1.0
0.2
30 mA
10
CMOS Level Inputs)
VIN > VCC - 0.2V or
COM’L.
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
Full Standby Current
(One Port — All
CE"A"< 0.2V and
MIL.
S
L
—
—
—
—
85
85
200
170
80
80
175 mA
150
CE"B" > VCC - 0.2V(5)
CMOS Level Inputs)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V
COM’L.
S
L
90
90
155
130
85
85
145
120
80
80
135
110
Active Port Outputs Open,
(3)
f = fMAX
NOTES:
3190 tbl 10
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA(typ.)
3. At f = fMAX, address and I/Os are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite of port "A".
OUTPUT LOADS AND AC TEST
CONDITIONS
5V
5V
Input Pulse Levels
Input Rise/Fall Times(1)
GND to 3.0V
5ns Max.
893Ω
893Ω
Input Timing Reference Levels 1.5V
DATAOUT
BUSY
INT
Output Reference Levels
Output Load
1.5V
DATAOUT
Figures 1 and 2
347Ω
30pF
347Ω
5pF
NOTE:
1. 3ns max for tAA = 12ns
3190 drw 06
Figure 2. Output Test Load
( for tLZ, tHZ, tWZ, tOW)
Figure 1. AC Output Test Load
Including scope and jig.
6.13
6
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT7016X12
Com'l. Only
IDT7016X15
Com'l. Only
Symbol
Parameter
Min.
Max
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
12
—
15
—
ns
tAA
Address Access Time
Chip Enable Access Time(3)
—
—
12
12
—
—
15
15
ns
ns
tACE
tAOE
tOH
tLZ
Output Enable Access Time
—
3
8
—
3
10
—
—
10
—
15
—
15
ns
ns
ns
ns
ns
ns
ns
ns
Output Hold from Address Change
Output Low-Z Time(1, 2)
Output High-Z Time(1, 2)
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
—
—
10
—
12
—
12
3
3
tHZ
—
0
—
0
tPU
tPD
—
10
—
—
10
—
tSOP
tSAA
IDT7016X20
IDT7016X25
IDT7016X35
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
READ CYCLE
tRC
tAA
Read Cycle Time
20
—
—
—
3
—
20
20
12
—
—
12
—
20
—
20
25
—
—
—
3
—
25
25
13
—
—
15
—
25
—
25
35
—
—
—
3
—
35
35
20
—
—
20
—
35
—
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tACE
tAOE
tOH
tLZ
Chip Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1, 2)
3
3
3
tHZ
Output High-Z Time(1, 2)
—
0
—
0
—
0
tPU
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
tPD
—
10
—
—
10
—
—
15
—
tSOP
tSAA
NOTES:
3190 tbl 11
1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. "X" in part numbers indicates power rating (S or L).
6.13
7
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
AOE
t
R/W
tOH
(1)
tLZ
(4)
DATAOUT
VALID DATA
(2)
HZ
t
BUSYOUT
(3, 4)
BDD
3190 drw 07
t
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDDdelayisrequiredonlyincaseswheretheoppositeportiscompletingawriteoperationtothesameaddresslocation. Forsimultaneous readoperations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last : tAOE, tACE, tAA, or tBDD.
5. SEM = VIH.
TIMING OF POWER-UP / POWER-DOWN
CE
t
PU
tPD
ICC
50%
50%
ISB
3190 drw 08
6.13
8
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)
IDT7016X12
Com'l. Only
IDT7016X15
Com'l. Only
Symbol
Parameter
Min.
Max
Min.
Max.
Unit
WRITE CYCLE
tWC
tEW
tAW
tAS
Write Cycle Time
12
10
10
0
—
—
—
—
—
—
—
10
—
10
—
—
—
15
12
12
0
—
—
—
—
—
—
—
10
—
10
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
tWP
tWR
tDW
tHZ
10
2
12
2
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1, 2)
Data Hold Time(4)
Write Enable to Output in High-Z(1, 2)
Output Active from End-of-Write(1, 2, 4)
SEM Flag Write to Read Time
10
—
0
10
—
0
tDH
tWZ
tOW
tSWRD
tSPS
—
3
—
3
5
5
SEM Flag Contention Window
5
5
IDT7016X20
IDT7016X25
IDT7016X35
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tWC
tEW
Write Cycle Time
20
15
15
0
—
—
—
—
—
—
—
12
—
12
—
—
—
25
20
20
0
—
—
—
—
—
—
—
15
—
15
—
—
—
35
30
30
0
—
—
—
—
—
—
—
20
—
20
—
—
—
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
tAW
ns
tAS
ns
tWP
Write Pulse Width
15
2
20
2
25
2
ns
tWR
Write Recovery Time
ns
tDW
Data Valid to End-of-Write
Output High-Z Time(1, 2)
Data Hold Time(4)
Write Enable to Output in High-Z(1, 2)
Output Active from End-of-Write(1, 2, 4)
SEM Flag Write to Read Time
SEM Flag Contention Window
15
—
0
15
—
0
15
—
0
ns
tHZ
ns
tDH
ns
tWZ
—
3
—
3
—
3
ns
tOW
ns
tSWRD
tSPS
NOTES:
5
5
5
ns
5
5
5
ns
3190 tbl 12
1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. "X" in part numbers indicates power rating (S or L).
6.13
9
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8)
t
WC
ADDRESS
(7)
t
HZ
OE
t
AW
CE or SEM (9)
(2)
(3)
(6)
tWR
t
AS
tWP
R/W
DATAOUT
DATAIN
(7)
t
OW
t
WZ
(4)
(4)
tDW
t
DH
3190 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING(1,5)
tWC
ADDRESS
tAW
CE or SEM(9)
(6)
AS
(3)
WR
(2)
t
t
tEW
R/W
tDW
tDH
DATAIN
3190 drw 10
NOTES:
1. R/W or CE must be High during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a Low CE and a Low R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going High to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured +/-200mV from steady state with the Output
Test load (Figure 2).
8. If OE is Low during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is high during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.13
10
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
t
AW
tWR
t
ACE
t
EW
SEM
t
OH
t
DW
t
SOP
DATAIN
VALID
DATAOUT
VALID(2)
I/O0
t
AS
tWP
tDH
R/W
t
SWRD
tAOE
OE
Write Cycle
Read Cycle
3190 drw 11
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O8) equal to the semaphore value.
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
A0"A"-A2 "A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
0"B"-A2 "B"
R/W"B"
t
SPS
MATCH
A
SIDE(2)
"B"
SEM"B"
3190 drw 12
NOTES:
1. DOR = DOL =VIH, CER = CEL =VIH.
2. All timing is the same for left and right ports. Port“A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/WA or SEM"A" going high to R/W"B" or SEM"B" going High.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
6.13
11
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
IDT7016X12
Com'l. Only
IDT7016X15
Com'l. Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
BUSY Access Time from Address Match
—
12
—
—
—
—
5
15
15
15
15
—
18
—
ns
ns
ns
ns
ns
ns
ns
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
—
—
—
5
12
12
12
—
15
—
—
11
—
13
BUSY TIMING (M/S = VIL)
tWB
tWH
BUSY Input to Write(4)
Write Hold After BUSY(5)
0
—
—
0
—
—
ns
ns
11
13
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
—
—
25
20
—
—
30
25
ns
ns
IDT7016X20
IDT7016X25
IDT7016X35
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S = VIH)
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
BUSY Access Time from Address Match
—
—
—
17
5
20
20
20
—
—
30
—
—
—
—
17
5
20
20
20
—
—
30
—
—
—
—
20
5
20
20
20
ns
—
35
—
ns
ns
ns
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
—
ns
ns
ns
—
15
—
17
—
25
BUSY TIMING (M/S = VIL)
tWB
tWH
BUSY Input to Write(4)
Write Hold After BUSY(5)
0
—
—
0
—
—
0
—
—
ns
ns
15
17
25
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
—
—
45
30
—
—
50
30
—
—
60
35
ns
tDDD
ns
NOTES:
2940 tbl 13
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveformof Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. "X" in part numbers indicates power rating (S or L).
6.13
12
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(2,4,5)
TIMING WAVEFORM OF READ WITH BUSY(M/S = VIH
)
tWC
MATCH
ADDR"A"
R/W"A"
t
WP
tDH
tDW
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBDD
t
BDA
BUSY"B"
t
WDD
DATAOUT "B"
VALID
(3)
tDDD
3190 drw 13
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
TIMING WAVEFORM OF WRITE WITH BUSY
t
WP
R/
W"A"
t
WB
BUSY"B"
(1)
tWH
R/
W"B"
(2)
NOTES:
3190 drw 14
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes High.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
6.13
13
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (M/S = VIH)(1)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
(2)
tAPS
CE"B"
t
BAC
t
BDC
BUSY"B"
3190 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING
(M/S = VIH)(1)
ADDR"A"
ADDR"B"
BUSY"B"
ADDRESS "N"
(2)
t
APS
MATCHING ADDRESS "N"
t
BAA
tBDA
3190 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
IDT7016X12
Com'l. Only
IDT7016X15
Com'l. Only
Symbol
Parameter
Min.
Max.
Min
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
0
—
—
12
12
0
0
—
—
15
15
ns
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
—
—
—
—
Interrupt Reset Time
IDT7016X20
IDT7016X25
Min. Max.
IDT7016X35
Symbol
Parameter
Min.
Max.
Min.
Max. Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
0
—
—
20
20
0
0
—
—
20
20
0
0
—
—
25
25
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
—
—
—
—
—
—
ns
Interrupt Reset Time
ns
NOTE:
2739 tbl 14
1. "X" in part numbers indicates power rating (S or L).
6.13
14
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
tWC
INTERRUPT SET ADDRESS(2)
ADDR"A"
CE"A"
(3)
(4)
t
WR
t
AS
R/W"A"
INT"B"
(3)
tINS
3190 drw 17
tRC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
CE"B"
(3)
t
AS
OE"B"
(3)
t
INR
INT"B"
3190 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
TRUTH TABLES
TRUTH TABLE I — INTERRUPT FLAG(1)
Left Port
Right Port
OER A13R-A0R INTR
R/WL
CEL
L
OEL A13L-A0L INTL
R/WR
CER
X
Function
Set Right INTR Flag
L
X
X
X
L
3FFF
X
X
X
L(3)
H(2)
X
X
L
X
L
X
L(2)
H(3)
X
X
X
L
3FFF
3FFE
X
Reset Right INTR Flag
Set Left INTL Flag
X
X
X
X
L
X
X
L
3FFE
X
X
X
Reset Left INTL Flag
NOTES:
3190 tbl 15
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
6.13
15
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE II — ADDRESS BUSY
ARBITRATION
Inputs
Outputs
A0L-A13L
CER A0R-A13R BUSYL
(1)
(1)
CEL
X
BUSYR
Function
Normal
X
X
H
L
NO MATCH
MATCH
H
H
H
H
H
Normal
X
MATCH
H
H
Normal
Write Inhibit(3)
L
MATCH
(2)
(2)
NOTES:
3190 tbl 16
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the
IDT7016 are push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs can not be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
TRUTH TABLE III — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1, 2)
Functions
D0 - D8 Left
D0 - D8 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
NOTES:
3190 tbl 17
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7016.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O8). These eight semaphores are addressed by A0 - A2.
FUNCTIONAL DESCRIPTION
memory location 3FFF and to clear the interrupt flag (INTR),
the right port must access memory location 3FFF. The
message (9 bits) at 3FFE or 3FFF is user-defined since it is in
an addressable SRAM location. If the interrupt function is not
used, address locations 3FFE and 3FFF are not used as mail
boxes but are still part of the random access memory. Refer
to Truth Table for the interrupt operation.
The IDT7016 provides two ports with separate control,
addressandI/Opinsthatpermitindependentaccessforreads
or writes to any location in memory. The IDT7016 has an
automatic power down feature controlled by CE. The CE
controls on-chip power down circuitry that permits the respec-
tive port to go into a standby mode when not selected (CE
High). When a port is enabled, access to the entire memory
array is permitted.
BUSY LOGIC
INTERRUPTS
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signalstheothersidethattheRAMis“Busy”. Thebusypincan
thenbeusedtostalltheaccessuntiltheoperationon theother
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
If the user chooses to use the interrupt function, a memory
location(mailboxormessagecenter)isassignedtoeachport.
Theleftportinterruptflag(INTL)isassertedwhentherightport
writes to memory location 3FFE where a write is defined as
the CE = R/W = VIL per the Truth Table. The left port clears
the interrupt by an address location 3FFE access when CER
=OER =VIL, R/W is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to
6.13
16
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MASTER
Dual Port
RAM
CE
SLAVE
CE
Dual Port
RAM
BUSY
R
BUSY
L
BUSY
R
BUSYL
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
CE
CE
BUSY
BUSY
R
BUSY
R
R
BUSY
L
BUSYL
BUSY
L
3190 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7016 RAMs.
can be initiated with the R/W signal. Failure to observe this
timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/Spin. Once in slave mode theBUSY
pin operates solely as a write inhibit input pin. Normal opera-
tion can be programmed by tying the BUSY pins high. If
desired, unintended write operations can be prevented to a
port by tying the busy pin for that port low.
The busy outputs on the IDT7016 RAM in master mode,
are push-pull type outputs and do not require pull up resistors
to operate. If these RAMs are being expanded in depth, then
the busy indication for the resulting array requires the use of
an external AND gate.
SEMAPHORES
The IDT7016 are extremely fast Dual-Port 16Kx9 Static
RAMs with an additional 8 address locations dedicated to
binary semaphore flags. These flags allow either processor
on the left or right side of the Dual-Port RAM to claim a
privilege over the other processor for functions defined by the
system designer’s software. As an example, the semaphore
can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port RAM or any other shared
resource.
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
that the activity on the left port in no way slows the access time
oftherightport. Bothportsareidenticalinfunctiontostandard
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
anon-semaphorelocation. Semaphoresareprotectedagainst
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IDT7016 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT7016's hardware semaphores, which pro-
vide a lockout mechanism without requiring complex pro-
gramming.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT7016 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7016 RAM the busy pin is
an output if the part is used as a master (M/Spin = H), and the
busy pin is an input if the part used as a slave (M/Spin = L) as
shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busyononeothersideofthearray. Thiswouldinhibitthewrite
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an
access is a read or write. In a master/slave array, both
address and chip enable must be valid long enough for a busy
flag to be output from the master before the actual write pulse
6.13
17
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Software handshaking between processors offers the until the semaphore is freed by the first side.
maximum in system flexibility by permitting shared resources
When a semaphore flag is read, its value is spread into all
to be allocated in varying configurations. The IDT7016 does data bits so that a flag that is a one reads as a one in all data
not use its semaphore flags to control any resources through bits and a flag containing a zero reads as all zeros. The read
hardware, thus allowing the system designer total flexibility in valueislatchedintooneside’soutputregisterwhenthatside's
system architecture.
semaphore select (SEM) and output enable (OE) signals go
An advantage of using semaphores rather than the more active. This serves to disallow the semaphore from changing
common methods of hardware arbitration is that wait states state in the middle of a read cycle due to a write cycle from the
are never incurred in either processor. This can prove to be other side. Because of this latch, a repeated read of a
a major advantage in very high-speed systems.
semaphoreinatestloopmustcauseeithersignal(SEMorOE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the sema-
phore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READ/WRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a sema-
phore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
andtheothersidehigh. Thisconditionwillcontinueuntilaone
is written to the same semaphore request latch. Should the
other side’s semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side’s
request latch. The second side’s flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provideahardwareassistforauseassignmentmethodcalled
“Token Passing Allocation.” In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
overthesharedresource. Ifitwasnotsuccessfulinsettingthe
latch, it determines that the right side processor has set the
latchfirst, hasthetokenandisusingthesharedresource. The
left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT7016 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard static RAM. Each of
the flags has a unique address which can be accessed by
eithersidethroughaddresspinsA0–A2. Whenaccessingthe
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If
a low level is written into an unused semaphore location, that
flagwillbesettoazeroonthatsideandaoneontheotherside
(see Table III). That semaphore can now only be modified by
thesideshowingthezero. Whenaoneiswrittenintothesame
locationfromthesameside,theflagwillbesettoaoneforboth
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communica-
tions. (Athoroughdiscussingontheuseofthisfeaturefollows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
6.13
18
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
resource is secure. As with any powerful programming into Semaphore 1. If the right processor performs a similar
technique, if semaphores are misused or misinterpreted, a task with Semaphore 0, this protocol would allow the two
software error can easily happen.
processors to swap 8K blocks of Dual-Port RAM with each
Initialization of the semaphores is not automatic and must other.
be handled via the initialization program at power-up. Since
The blocks do not have to be any particular size and can
any semaphore request flag which contains a zero must be even be variable, depending upon the complexity of the
reset to a one, all semaphores on both sides should have a software using the semaphore flags. All eight semaphores
one written into them at initialization from both sides to assure could be used to divide the Dual-Port RAM or other shared
that they will be free when needed.
resources into eight parts. Semaphores can even be as-
signed different meanings on different sides rather than being
given a common meaning as was shown in the example
above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
ofmemoryduringatransferandtheI/Odevicecannottolerate
any wait states. With the use of semaphores, once the two
deviceshasdeterminedwhichmemoryareawas“off-limits”to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
USING SEMAPHORES—SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7016’s Dual-Port
RAM. Say the 16K x 9 RAM was to be divided into two 8K x
9 blocks which were to be dedicated at any one time to
servicing either the left or right port. Semaphore 0 could be
usedtoindicatethesidewhichwouldcontrolthelowersection
of memory, and Semaphore 1 could be defined as the indica-
tor for the upper section of memory.
To take a resource, in this example the lower 8K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore 0. If this task were
successfully completed (a zero was read back rather than a
one), the left processor would assume control of the lower 8K.
Meanwhile the right processor was attempting to gain control
of the resource after the left processor, it would read back a
one in response to the zero it had attempted to write into
Semaphore 0. At this point, the software could choose to try
and gain control of the second 8K section by writing, then
reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
Semaphores are also useful in applications where no
memory “WAIT” state is available on one or both sides. Once
a semaphore handshake has been performed, both proces-
sors can access their assigned RAM segments at full speed.
Another application is in the area of complex data struc-
tures. In this case, block arbitration is very important. For this
applicationoneprocessormayberesponsibleforbuildingand
updating a data structure. The other processor then reads
andinterpretsthatdatastructure. Iftheinterpretingprocessor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processortocomebackandreadthecompletedatastructure,
thereby guaranteeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
D0
D0
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
3190 drw 20
Figure 4. IDT7016 Semaphore Logic
6.13
19
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
B
Commercial (0°C to +70°C)
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
PF
G
J
80-pin TQFP (PN80-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
12
15
20
25
35
Commercial Only
Commercial Only
Speed in nanoseconds
S
L
Standard Power
Low Power
7016
144K (16K x 9) Dual-Port RAM
3190 drw 21
6.13
20
IDT7016S15J 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| IDT7016S15JB | IDT | HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM | 获取价格 |
|
| IDT7016S15JG | IDT | HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM | 获取价格 |
|
| IDT7016S15JGB | IDT | HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM | 获取价格 |
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| IDT7016S15JGI | IDT | HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM | 获取价格 |
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| IDT7016S15PF | IDT | HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM | 获取价格 |
|
| IDT7016S15PF9 | IDT | Dual-Port SRAM, 16KX9, 15ns, CMOS, PQFP80, TQFP-80 | 获取价格 |
|
| IDT7016S15PFB | IDT | HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM | 获取价格 |
|
| IDT7016S15PFG | IDT | HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM | 获取价格 |
|
| IDT7016S15PFG8 | IDT | Dual-Port SRAM, 16KX9, 15ns, CMOS, PQFP80, TQFP-80 | 获取价格 |
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| IDT7016S15PFGB | IDT | HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM | 获取价格 |
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