IDT7024L55JG [IDT]
Dual-Port SRAM, 4KX16, 55ns, CMOS, PQCC84, 1.150 X 1.150 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-84;型号: | IDT7024L55JG |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Dual-Port SRAM, 4KX16, 55ns, CMOS, PQCC84, 1.150 X 1.150 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-84 静态存储器 内存集成电路 |
文件: | 总22页 (文件大小:180K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HIGH-SPEED
IDT7024S/L
4K x 16 DUAL-PORT
STATIC RAM
◆
IDT7024 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin
Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts availble, see ordering information
Features
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
◆
◆
– Military:20/25/35/55/70ns(max.)
– Industrial:55ns (max.)
◆
◆
◆
– Commercial:15/17/20/25/35/55ns(max.)
Low-power operation
◆
– IDT7024S
◆
◆
◆
◆
Active:750mW(typ.)
Standby: 5mW (typ.)
– IDT7024L
Active:750mW(typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multiplexed
◆
◆
◆
bus compatibility
FunctionalBlockDiagram
R/W
L
R/W
R
R
UB
UBL
LB
CE
OE
L
L
L
LBR
CE
R
R
OE
I/O8L-I/O15L
I/O0L-I/O7L
I/O8R-I/O15R
I/O
Control
I/O
Control
I/O0R-I/O7R
BUSY (1,2)
L
BUSYR
(1,2)
A
11R
0R
A
11L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
0L
A
12
12
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
R/W
R
CE
OE
R/W
L
L
R
R
L
SEM
R
SEM
L
(2)
INT (2)
L
M/S
INTR
2740 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
OCTOBER 2008
1
DSC 2740/13
©2008IntegratedDeviceTechnology,Inc.
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
port to enter a very low standby power mode.
The IDT7024 is a high-speed 4Kx 16 Dual-Port Static RAM. The
IDT7024isdesignedtobeusedasastand-alone64K-bitDual-PortRAM
orasacombinationMASTER/SLAVEDual-PortRAMfor32-bitormore
wordsystems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproach
in32-bitorwidermemorysystemapplicationsresultsinfull-speed,error-
freeoperationwithouttheneedforadditionaldiscretelogic.
FabricatedusingIDT’sCMOShigh-performancetechnology,these
devices typically operate on only 750mW of power. Low-power (L)
versionsofferbatterybackupdataretentioncapabilitywithtypicalpower
consumptionof500µWfroma2Vbattery.
TheIDT7024ispackagedinaceramic84-pinPGA,an84-pinFlatpack
andPLCC,anda100-pinTQFP.Militarygradeproductismanufactured
incompliancewiththelatestrevisionofMIL-PRF-38535QML,makingit
ideallysuitedtomilitarytemperatureapplicationsdemandingthehighest
levelofperformanceandreliability.
This device provides two independent ports with separate control,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
reads or writes to any location in memory. An automatic power down
featurecontrolledbychipenable(CE)permitstheon-chipcircuitryofeach
PinConfigurations(1,2,3)
INDEX
11/06/01
11 10
9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
74
I/O8L
I/O9L
A
A
A
A
A
A
A
A
7L
6L
5L
4L
3L
2L
1L
0L
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
I/O10L
I/O11L
I/O12L
I/O13L
GND
IDT7024J or F
I/O14L
I/O15L
(4)
J84-1
F84-2
INT
L
(4)
BUSY
L
VCC
84-Pin PLCC / Flatpack
GND
I/O0R
I/O1R
I/O2R
GND
(5)
Top View
M/S
BUSY
R
INT
R
VCC
A
A
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
1R
2R
3R
4R
5R
6R
Index
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
,
2740 drw 02
11/06/01
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
N/C
N/C
N/C
N/C
I/O10L
I/O11L
I/O12L
I/O13L
GND
75
N/C
N/C
N/C
N/C
2
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
3
4
5
A5L
A4L
A3L
A2L
A1L
A0L
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O14L
I/O15L
IDT7024PF
INTL
(4)
PN100-1
VCC
BUSY
GND
M/S
BUSY
INTR
L
GND
I/O0R
I/O1R
I/O2R
100-Pin TQFP
(5)
Top View
R
VCC
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
N/C
N/C
N/C
N/C
1R
2R
3R
4R
NOTES:
N/C
N/C
N/C
N/C
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.
F84-2 package body is approximately 1.17 in x 1.17 in x .11 in.
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
,
2740 drw 03
PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
11/06/01
63
I/O7L
66
I/O10L
67
I/O11L
69
I/O13L
72
I/O15L
75
I/O0R
76
I/O1R
79
I/O3R
81
I/O5R
82
I/O6R
61
I/O5L
64
I/O8L
65
I/O9L
68
I/O12L
71
I/O14L
70
60
I/O4L
62
I/O6L
58
I/O2L
59
I/O3L
55
I/O0L
56
I/O1L
57
54
51
48
46
45
42
11
10
09
08
07
06
05
04
03
02
01
A
11L
A
10L
A
7L
OE
L
SEM
L
LBL
49
50
47
44
43
40
N/C
A
9L
A
8L
6L
3L
0L
A
5L
UB
L
CEL
53
52
41
39
R/W
L
GND
VCC
A
A
4L
38
37
A
A
2L
73
33
35
34
BUSY
L
VCC
A
INT
L
IDT7024G
(4)
74
32
31
36
G84-3
GND
GND
GND
M/S
A
1L
84-Pin PGA
Top View
(5)
77
I/O2R
80
I/O4R
83
I/O7R
78
28
29
30
V
CC
A
0R
INT
R
BUSY
R
26
27
A
2R
A
1R
7
11
12
23
25
SEM
R
A
5R
GND
GND
A
3R
1
2
5
8
10
14
17
20
22
24
I/O9R
I/O10R I/O13R I/O15R
R/W
R
A
11R
A
8R
A
6R
A
4R
UB
R
84
I/O8R
3
4
6
9
15
13
16
18
19
21
I/O11R I/O12R I/O14R
N/C
A
10R
A
9R
A
7R
OER
LB
R
CER
A
B
C
D
E
F
G
H
J
K
L
2740 drw 04
Index
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. Package body is approximately 1.12 in x 1.12 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
PinNames
MaximumOperatingTemperature
andSupplyVoltage(1)
Left Port
Right Port
Names
Grade
Ambient
GND
Vcc
Chip Enable
CE
R/W
OE
L
CE
R/W
OE
R
Temperature
L
R
Read/Write Enable
Output Enable
Address
Military
-55OC to +125OC
0OC to +70OC
0V
0V
0V
5.0V
+
+
+
10%
L
R
Commercial
Industrial
5.0V
5.0V
10%
A0L - A11 L
A
0R - A11R
-40OC to +85OC
10%
I/O0L - I/O15L
I/O0R - I/O15R
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
2740 tbl 02
NOTES:
SEM
UB
LB
INT
BUSY
L
SEM
UB
LB
INT
BUSY
M/S
R
1. This is the parameter TA. This is the "instant on" case temperature.
L
R
L
R
L
R
Busy Flag
L
R
Master or Slave Select
Power
VCC
GND
Ground
2740 tbl 01
6.42
3
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
R/W
X
X
L
I/O8-15
High-Z
High-Z
DATAIN
High-Z
DATAIN
I/O0-7
High-Z
High-Z
High-Z
DATAIN
DATAIN
High-Z
DATAOUT
DATAOUT
High-Z
Mode
CE
H
X
L
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
Deselcted: Power-Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
H
H
L
L
H
L
H
L
L
L
H
L
H
H
H
X
L
H
L
H
DATAOUT
High-Z
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
L
L
H
L
H
L
L
L
H
DATAOUT
High-Z
X
H
X
X
X
Outputs Disabled
2740 tbl 03
NOTE:
1. A0L — A11L ≠ A0R — A11R
Truth Table II: Semaphore Read/Write Control(1)
Inputs(1)
Outputs
CE(2)
H
OE
L
UB
X
H
X
H
L
LB
X
H
X
H
X
L
SEM
L
R/W
H
I/O8-15
I/O0-7
Mode
Read Semaphore Flag Data Out
Read Semaphore Flag Data Out
DATAOUT
DATAOUT
DATAIN
DATAOUT
DATAOUT
DATAIN
X
H
L
L
H
X
X
X
X
L
Write I/O into Semaphore Flag
0
↑
X
L
DATAIN
DATAIN
Write I/O0 into Semaphore Flag
↑
____
____
L
X
L
Not Allowed
Not Allowed
____
____
L
X
X
L
2740 tbl 04
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0 - I/O15).
These eight semaphores are addressed by A0 - A2.
AbsoluteMaximumRatings(1)
RecommendedDCOperating
Conditions
Symbol
Rating
Commercial
& Industrial
Military
Unit
Symbol
Parameter
Supply Voltage
GND Ground
Min.
Typ. Max. Unit
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
VCC
4.5
5.0
5.5
0
V
V
V
0
0
Temperature
Under Bias
-55 to +125
-65 to +150
50
-65 to +135
-65 to +150
50
oC
oC
T
BIAS
V
IH
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
-0.5(1)
V
____
VIL
Storage
Temperature
TSTG
2740 tbl 06
NOTES:
IOUT
DC Output
Current
mA
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
2740 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. VTERM must not exceed Vcc +10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period over VTERM > Vcc + 10%.
6.42
4
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
(1)
Capacitance (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max. Unit
CIN
VIN = 3dV
9
pF
COUT
VOUT = 3dV
10
pF
2740 tbl 07
NOTES:
1. This parameter are determined by device characterization, but is not
production tested.
2. 3dV references the interpolated capacitance when the input and
output signals switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7024S
7024L
Symbol
|ILI
|ILO
Parameter
Test Conditions
Min.
Max.
10
Min.
Max.
5
Unit
µA
µA
V
(1)
___
___
|
Input Leakage Current
V
CC = 5.5V, VIN = 0V to VCC
___
___
___
___
|
Output Leakage Current
Output Low Voltage
Output High Voltage
10
5
CE = VIH, VOUT = 0V to VCC
VOL
I
OL = +4mA
0.4
0.4
___
___
VOH
IOH = -4mA
2.4
2.4
V
2740 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)
7024X15
7024X17
7024X20
7024X25
Com'l &
Military
Com'l Only
Com'l Only
Com'l, Ind
& Military
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
S
L
170
170
310
260
170
170
310
260
160
160
290
240
155
155
265
220
mA
CE = VIL
,
Outputs Disabled
SEM = VIH
____
____
____
____
____
____
____
____
(3)
MIL &
IND
S
L
160
160
370
320
155
155
340
280
f = fMAX
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
20
20
60
50
20
20
60
50
20
20
60
50
16
16
60
50
mA
mA
mA
mA
= SLEM
L
= VIH
CE
R
SEM
= CE = VIH
R
(3)
f = fMAX
____
____
____
____
____
____
____
____
MIL &
IND
S
L
20
20
90
70
16
16
80
65
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
105
105
190
160
105
105
190
160
95
95
180
150
90
90
170
140
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3 )
f=fMAX
SEM
____
____
____
____
____
____
____
____
MIL &
IND
S
L
95
95
240
210
90
90
215
180
R
= SEML = VIH
ISB3
Full Standby Current
Both Ports CE
CE > VCC - 0.2V,
IN > VCC - 0.2V or
L and
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
(Both Ports
-
R
CMOS Level Inputs)
V
____
____
____
____
____
____
____
____
V
< 0.2V, f = 0(4 )
MIL &
IND
S
L
1.0
0.2
30
10
1.0
0.2
30
10
SEINM
R
= SEML > VCC - 0.2V
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
S
L
100
100
170
140
100
100
170
140
90
90
155
130
85
85
145
120
CE < 0.2V and
CE"BA" > V - 0.2V
(5)
SEM
R
= SCECM
L > VCC - 0.2V
____
____
____
____
____
____
____
____
MIL &
IND
S
L
90
90
225
200
85
85
200
170
V
IN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
(3)
f = fMAX
2740 tbl 09a
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VCC = 5V, TA = +25°C, and are not production tested. ICC DC = 120mA (TYP.)
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.42
5
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (con’t.) (VCC = 5.0V ± 10%)
7024X35
Com'l &
Military
7024X55
Com'l, Ind
& Military
7024X70
Military Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
____
____
____
____
mA
ICC
Dynamic Operating
Current
(Both Ports Active)
S
L
150
150
250
210
150
150
250
210
CE = VIL,
Outputs Disabled
SEM = VIH
(3)
MIL &
IND
S
L
150
150
300
250
150
150
300
250
140
140
300
250
f = fMAX
____
____
____
____
mA
mA
ISB1
ISB2
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
13
13
60
50
13
13
60
50
CER = CEL = VIH
SEMR = SEML = VIH
(3)
f = fMAX
MIL &
IND
S
L
13
13
80
65
13
13
80
65
10
10
80
65
(5)
____
____
____
____
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
85
85
155
130
95
95
155
130
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
MIL &
IND
S
L
85
85
190
160
95
95
190
160
80
80
190
160
SEMR = SEML = VIH
____
____
____
____
mA
mA
ISB3
ISB4
Full Standby Current
(Both Ports -
Both Ports CEL and
CER > VCC - 0.2V,
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
CMOS Level Inputs)
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
MIL &
IND
S
L
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
____
____
____
____
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
S
L
80
80
135
110
80
80
135
110
CE"A" < 0.2V and
(5)
CE"B" > VCC - 0.2V
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
MIL &
IND
S
L
80
80
175
150
80
80
175
150
75
75
175
150
(3)
f = fMAX
2740 tbl 09b
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VCC = 5V, TA = +25°C, and are not production tested.
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
Data Retention Characteristics Over All Temperature Ranges
(4)
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
Symbol
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
V
___
___
VDR
VCC for Data Retention
VCC = 2V
2.0
___
ICCDR
Data Retention Current
µA
CE > VHC
IN > VHC or < VLC
MIL. & IND.
COM'L.
100
4000
___
V
100
1500
(3)
CDR
___
___
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
SEM > VHC
(3)
(2)
___
___
t
R
t
RC
ns
2740 tbl 10
NOTES:
1. TA = +25°C, VCC = 2V, and are by device characterization but are not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not tested.
4. At Vcc < 2.0V, input leakages are not defined.
6.42
6
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Data Retention Waveform
DATA RETENTION MODE
VDR
≥
4.5V
4.5V
VCC
2V
t
CDR
tR
V
DR
V
IH
VIH
CE
2740 drw 05
AC Test Conditions
Input Pulse Levels
GND to 3.0V
5ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1 and 2
2740 tbl 11
5V
5V
1250Ω
1250Ω
DATAOUT
BUSY
INT
DATAOUT
30pF
775Ω
5pF*
775Ω
2740 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and Jig
6.42
7
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
7024X15
7024X17
7024X20
Com'l, Ind
& Military
7024X25
Com'l &
Military
Com'l Only
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
15
17
20
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
t
Address Access Time
15
15
15
17
17
17
20
20
20
25
25
25
Chip Enable Access Time(3)
____
____
____
____
____
____
____
____
____
____
____
____
t
t
Byte Enable Access Time(3)
t
Output Enable Access Time
10
10
12
13
____
____
____
____
t
Output Hold from Address Change
Output Low-Z Time(1,2)
3
3
3
3
____
____
____
____
t
3
3
3
3
Output High-Z Time(1,2)
10
10
12
15
____
____
____
____
t
t
Chip Enable to Power Up Time(1,2)
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access(3)
0
0
0
0
____
____
____
____
____
____
____
____
t
15
17
20
25
____
____
____
____
t
10
10
10
10
____
____
____
____
t
15
17
20
25
ns
2740 tbl 12a
7024X35
Com'l &
Military
7024X55
Com'l, Ind
& Military
7024X70
Military Only
Symbol
READ CYCLE
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
35
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Address Access Time
35
35
35
55
55
55
70
70
70
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
____
____
____
____
____
t
t
t
20
30
35
____
____
____
t
3
3
3
____
____
____
t
3
3
3
Output High-Z Time(1,2)
15
25
30
____
____
____
t
t
Chip Enable to Power Up Time(1,2)
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access(3)
0
0
0
____
____
____
____
____
____
t
35
50
50
____
____
____
t
15
15
15
____
____
____
t
35
55
70
ns
2740 tbl 12b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM =VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM =VIL.
4. 'X' in part number indicates power rating (S or L).
6.42
8
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
tAOE
(4)
t
ABE
UB, LB
R/W
(1)
tOH
tLZ
VALID DATA(4)
DATAOUT
(2)
tHZ
BUSYOUT
(3,4)
2740 drw 07
tBDD
NOTES:
1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has
no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
Timing of Power-Up Power-Down
CE
tPU
t
PD
I
CC
SB
I
,
2740 drw 08
6.42
9
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
7024X15
7024X17
Com'l Only
7024X20
Com'l, Ind
& Military
7024X25
Com'l &
Military
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
15
12
12
0
17
12
12
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
12
0
12
0
15
0
20
0
t
Write Recovery Time
t
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
10
10
15
15
____
____
____
____
t
10
10
12
15
____
____
____
____
t
0
0
0
0
(1,2)
____
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
10
12
15
____
____
____
____
t
0
5
5
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
____
____
t
t
ns
2740 tbl 13a
7024X35
Com'l &
Military
7024X55
Com'l, Ind
& Military
7024X70
Military Only
Symbol
WRITE CYCLE
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
35
30
30
0
55
45
45
0
70
50
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
25
0
40
0
50
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
15
30
40
____
____
____
t
15
25
30
____
____
____
t
0
0
0
(1,2)
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
15
25
30
____
____
____
t
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
t
t
ns
2740 tbl 13b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH
and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
6.42
10
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
t
WC
ADDRESS
(7)
tHZ
OE
t
AW
CE or SEM (9)
UB or LB (9)
R/W
(3)
(2)
(6)
tWR
t
WP
tAS
(7)
t
WZ
tOW
(4)
(4)
DATAOUT
DATAIN
t
DW
tDH
2740 drw 09
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
t
WC
ADDRESS
t
AW
CE or SEM(9)
(3)
(2)
(6)
AS
t
WR
t
EW
t
UB or LB(9)
R/W
tDW
tDH
DATAIN
2740 drw 10
NOTES:
1. R/W or CE or UB & LB = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a UB or LB = VIL and a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH = VIL to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W, UB, or LB.
7. This parameter is guaranted by device characterization, but is not production tested. Transition is measured 0mV steady state with the Output Test Load
(Figure 2).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP for (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP .
9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. tEW must be
met for either condition.
6.42
11
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
t
OH
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
tWR
t
ACE
tAW
tEW
SEM
tSOP
t
DW
DATAOUT
VALID(2)
DATAIN
VALID
I/O0
t
AS
tWP
tDH
R/W
tSWRD
tAOE
OE
Write Cycle
Read Cycle
2740 drw 11
NOTES:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O15) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2)
"A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
,
2740 drw 12
NOTES:
1. D0R = D0L = VIL, CER = CEL = VIH, or both UB & LB = VIH, semaphore flag is released from both sides (reads as ones from both sides) at cycle start.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/WA or SEMA going HIGH to R/WB or SEMB going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
6.42
12
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6)
7024X15
7024X17
7024X20
Com'l, Ind
& Military
7024X25
Com'l &
Military
Com'l Only
Com'l Only
Symbol
BUSY TIMING (M/S = VIH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
17
17
17
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Match
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
t
15
17
17
17
____
____
____
____
t
5
5
5
5
____
____
____
____
BUSY Disable to Valid Data(3)
t
18
18
30
30
(5)
____
____
____
____
t
Write Hold After BUSY
12
13
15
17
BUSY INPUT TIMING (M/S = VIH
)
____
____
____
____
____
____
____
____
BUSY Input to Write(4)
t
WB
0
0
0
0
ns
ns
(5)
tWH
Write Hold After BUSY
12
13
15
17
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
30
25
30
25
45
35
50
35
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
2740 tbl 14a
7024X35
Com'l &
Military
7024X55
Com'l, Ind
& Military
7024X70
Military Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH
)
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
20
20
20
45
40
40
45
40
40
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Match
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
t
20
35
35
____
____
____
t
5
5
5
____
____
____
BUSY Disable to Valid Data(3)
t
35
40
45
(5)
____
____
____
t
Write Hold After BUSY
25
25
25
BUSY INPUT TIMING (M/S = VIH
)
____
____
____
____
____
____
BUSY Input to Write(4)
t
WB
0
0
0
ns
ns
(5)
tWH
Write Hold After BUSY
25
25
25
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
60
45
80
65
95
80
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
2740 tbl 14b
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port 'B' during contention with port 'A'.
5. To ensure that a write cycle is completed on port 'B' after contention with port 'A'.
6. 'X' in part number indicates power rating (S or L).
6.42
13
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
TimingWaveformof WritewithPort-to-PortReadandBUSY(2,4,5)(M/S =VIH)
tWC
MATCH
ADDR"A"
R/W"A"
tWP
t
DH
tDW
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBAA
tBDA
tBDD
BUSY"B"
tWDD
VALID
DATAOUT "B"
(3)
tDDD
2740 drw 13
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave) then BUSY is an input BUSY"A" = VIL and BUSY"B" = don't care, for this example.
5. All timing is the same for both left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
tWH
,
(2)
R/W"B"
2740 drw 14
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on port "B" Blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'Slave' Version.
6.42
14
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
t
APS
CE"B"
t
BAC
tBDC
BUSY"B"
2740 drw 15
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDR"B"
BUSY"B"
ADDRESS "N"
(2)
tAPS
MATCHING ADDRESS "N"
tBAA
tBDA
2740 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
7024X15
7024X17
7024X20
Com'l , Ind
& Military
7024X25
Com'l &
Military
Com'l Only
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
0
ns
ns
ns
t
0
0
0
0
____
____
____
____
t
15
15
15
15
20
20
20
20
____
____
____
____
t
Interrupt Reset Time
ns
2740 tbl 15a
7024X35
Com'l &
Military
7024X55
Com'l, Ind
& Military
7024X70
Military Only
Symbol
INTERRUPT TIMING
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
ns
ns
ns
t
0
0
0
____
____
____
t
25
25
40
40
50
50
____
____
____
t
Interrupt Reset Time
ns
2740 tbl 15b
NOTES:
1. 'X' in part number indicates power rating (S or L).
6.42
15
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
INTERRUPT SET ADDRESS (2)
ADDR"A"
(4)
(3)
t
AS
tWR
CE"A"
R/W"A"
INT"B"
(3)
t
INS
2740 drw 17
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
tAS
OE"B"
(3)
INR
t
INT"B"
2740 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III — Interrupt Flag(1,4)
Left Port
Right Port
OE
R/WL
A11L-A0L
R/WR
A
11R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CEL
OEL
INTL
CER
R
INTR
(2)
L
L
X
X
L
X
X
X
L
FFF
X
X
X
X
L
L
X
X
L
X
FFF
FFE
X
L
R
(3)
X
X
X
H
R
(3)
X
X
L
L
X
X
X
X
L
(2)
X
FFE
H
X
L
2740 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
6.42
16
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table IV —
Address BUSY Arbritration
Inputs
Outputs
A
0L-A11L
(1)
(1)
A
0R-A11R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
(3)
MATCH
(2)
(2)
Write Inhibit
2740 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7024 are
push pull, not open drain outputs. On slaves, the BUSY asserted input internally inhibits write.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D15 Left
D0
- D15 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2740 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024.
2. There are eight semaphore flags written to via I/O0 and read from all the I/O's. These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL, to access the Semaphores. Refer to the Semaphore Read/Write Control Truth Table.
FunctionalDescription
TheIDT7024providestwoportswithseparatecontrol,addressand
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation
inmemory.TheIDT7024hasanautomaticpowerdownfeaturecontrolled
by CE. The CE controls on-chip power down circuitry that permits the
respectiveporttogointoastandbymodewhennotselected(CE=VIH).
Whenaportisenabled,accesstotheentirememoryarrayispermitted.
ormessagecenter)is assignedtoeachport. Theleftportinterruptflag
(INTL) is asserted when the right port writes to memory location FFE
(HEX), whereawriteisdefinedastheCE=R/W=VILpertheTruthTable
III.TheleftportclearstheinterruptbyaccessaddresslocationFFEaccess
when CER = OER = VIL, R/W is a "don't care". Likewise, the right port
interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation
FFF(HEX)andtocleartheinterruptflag(INTR),therightportmustaccess
thememorylocationFFF. Themessage(16bits)atFFEorFFFisuser-
defined,sinceitisanaddressableSRAMlocation.Iftheinterruptfunction
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
6.42
17
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
isnotused,addresslocationsFFEandFFFarenotusedasmailboxes,
butaspartoftherandomaccessmemory.RefertoTruthTableIIIforthe
interruptoperation.
CE
CE
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
BUSY (R)
BUSY (R)
BUSY (L)
BUSY (L)
BusyLogic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
CE
CE
BUSY (R)
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
BUSY (L)
,
2740 drw 19
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7024 RAMs.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
anduse anyBUSYindicationas aninterruptsource toflagthe eventof
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
TheBUSYoutputsontheIDT7024SRAMinmastermode,arepush-
pulltypeoutputsanddonotrequirepullupresistorstooperate.Ifthese
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe
Dual-Port RAM or any other shared resource.
The Dual-PortRAMfeatures a fastaccess time, andbothports are
completelyindependentofeachother.Thismeansthattheactivityonthe
leftportinnowayslows theaccess timeoftherightport.Bothports are
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM
enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol
on-chippowerdowncircuitrythatpermits the respective porttogointo
standbymodewhennotselected.Thisistheconditionwhichisshownin
Truth Table I where CE and SEM = VIH.
SystemswhichcanbestusetheIDT7024containmultipleprocessors
or controllers and are typically very high-speed systems which are
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
aperformanceincreaseofferedbytheIDT7024'shardwaresemaphores,
whichprovidealockoutmechanismwithoutrequiringcomplexprogram-
ming.
Softwarehandshakingbetweenprocessors offers themaximumin
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations.TheIDT7024doesnotuseitssemaphoreflagstocontrol
anyresourcesthroughhardware,thusallowingthesystemdesignertotal
flexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speedsystems.
Width Expansion with BUSY Logic
Master/SlaveArrays
WhenexpandinganIDT7024RAMarrayinwidthwhileusingBUSY
logic,onemasterpartisusedtodecidewhichsideoftheRAMarraywill
receiveaBUSYindication,andtooutputthatindication.Anynumberof
slaves to be addressed in the same address range as the master, use
theBUSYsignalasawriteinhibitsignal.ThusontheIDT7024RAMthe
BUSYpinisanoutputifthepartisusedasamaster(M/Spin=VIH),and
theBUSYpinisaninputifthepartusedasaslave(M/Spin=VIL)as shown
in Figure 3.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. Itignores whetheranaccess is a readorwrite. In
a master/slave array, bothaddress andchipenable mustbe validlong
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables.Failure
toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland
corrupteddataintheslave.
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
processorwantstousethisresource,itrequeststhetokenbysettingthe
latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
Semaphores
TheIDT7024isanextremelyfastDual-Port4Kx16CMOSStaticRAM
withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.
TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port
RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby
thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe
6.42
18
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
it. If it was successful, it proceeds to assume control over the shared
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe byeitherrepeatedreadsorbywritingaoneintothesamelocation.The
rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
thatsemaphore’sstatusorremoveitsrequestforthatsemaphoretoperform into a semaphore flag. Whichever latch is first to present a zero to the
anothertaskandoccasionallyattemptagaintogaincontrolofthetokenvia semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
thesetandtestsequence.Oncetherightsidehasrelinquishedthetoken, sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
theleftsideshouldsucceedingainingcontrol.
semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch
ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
azerointoasemaphorelatchandisreleasedwhenthesamesidewrites overtotheothersideassoonasaoneiswrittenintothefirstside’srequest
aonetothatlatch.
latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest
The eightsemaphore flags reside withinthe IDT7024ina separate latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
memoryspacefromtheDual-PortRAM.This addressspaceisaccessed is requestedandthe processorwhichrequesteditnolongerneeds the
byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe resource, the entire system can hang up until a one is written into that
semaphore flags) and using the other control pins (Address, OE, and semaphorerequestlatch.
R/W)as theywouldbeusedinaccessingastandardStaticRAM.Each
The critical case of semaphore timing is when both sides request
oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside a single token by attempting to write a zero into it at the same time.
throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof The semaphore logic is specially designed to resolve this problem.
theotheraddresspinshasanyeffect.
Ifsimultaneous requests are made, the logicguarantees thatonlyone
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel sidereceivesthetoken.Ifonesideisearlierthantheotherinmakingthe
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero request, the firstside tomake the requestwillreceive the token. Ifboth
on that side and a one on the other side (see Truth Table III). That requestsarriveatthesametime,theassignmentwillbearbitrarilymade
semaphorecannowonlybemodifiedbythesideshowingthezero.When to one port or the other.
aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
One caution that should be noted when using semaphores is that
settoaoneforbothsides(unlessasemaphorerequestfromtheotherside semaphoresalonedonotguaranteethataccesstoaresourceissecure.
ispending)andthencanbewrittentobybothsides.Thefactthattheside Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused
whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites ormisinterpreted, a software errorcaneasilyhappen.
fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
Initializationofthesemaphoresisnotautomaticandmustbehandled
communications.(Athoroughdiscussionontheuseofthisfeaturefollows viatheinitializationprogramatpower-up.Sinceanysemaphorerequest
shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth
storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis sidesshouldhaveaonewrittenintothematinitializationfrombothsides
freedbythefirstside.
to assure that they will be free when needed.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
signalsgoactive.Thisservestodisallowthesemaphorefromchanging
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
cause either signal (SEM or OE) to go inactive or the output will never
change.
UsingSemaphores—SomeExamples
Perhapsthesimplestapplicationofsemaphoresistheirapplicationas
resourcemarkersfortheIDT7024’sDual-PortRAM.Saythe4Kx16RAM
was tobedividedintotwo2Kx16blocks whichweretobededicatedat
anyonetimetoservicingeithertheleftorrightport.Semaphore0could
be used to indicate the side which would control the lower section of
memory,andSemaphore1couldbedefinedastheindicatorfortheupper
sectionofmemory.
AsequenceWRITE/READmustbeusedbythesemaphoreinorder
to guarantee that no system level contention will occur. A processor
requestsaccesstosharedresourcesbyattemptingtowriteazerointoa
semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore
requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,
afactwhichtheprocessorwillverifybythesubsequentread(seeTruth
TableIII).Asanexample,assumeaprocessorwritesazerototheleftport
atafreesemaphorelocation.Onasubsequentread,theprocessorwill
verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol
overtheresourceinquestion.Meanwhile,ifaprocessorontherightside
attempts towriteazerotothesamesemaphoreflagitwillfail,as willbe
verifiedbythefactthataonewillbereadfromthatsemaphoreontheright
side during subsequent read. Had a sequence of READ/WRITE been
usedinstead,systemcontentionproblemscouldhaveoccurredduringthe
gap between the read and write cycles.
Totakearesource,inthis examplethelower2KofDual-PortRAM,
the processor on the left port could write and then read a zero in to
Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread
backratherthana one), the leftprocessorwouldassume controlofthe
lower2K.Meanwhiletherightprocessorwasattemptingtogaincontrolof
theresourceaftertheleftprocessor,itwouldreadbackaoneinresponse
tothezeroithadattemptedtowriteintoSemaphore0.Atthis point,the
softwarecouldchoosetotryandgaincontrolofthesecond2Ksectionby
writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining
control,itwouldlockouttheleftside.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo
itssemaphorerequestandperformothertasksuntilitwasabletowrite,then
6.42
19
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
readazerointoSemaphore1.Iftherightprocessorperformsasimilartask
Semaphoresarealsousefulinapplicationswherenomemory“WAIT”
withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap stateisavailableononeorbothsides.Onceasemaphorehandshakehas
2Kblocks ofDual-PortRAMwitheachother. been performed, both processors can access their assigned RAM
The blocks do not have to be any particular size and can even be segmentsatfullspeed.
variable, depending upon the complexity of the software using the
Anotherapplicationisintheareaofcomplexdatastructures. Inthis
semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual- case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor
PortRAMorothersharedresources intoeightparts. Semaphores can mayberesponsibleforbuildingandupdatingadatastructure.Theother
evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting
given a common meaning as was shown in the example above.
processorreadsanincompletedatastructure,amajorerrorconditionmay
Semaphores are a useful form of arbitration in systems like disk exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo
interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks
atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse itandthenisabletogoinandupdatethedatastructure.Whentheupdate
ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea is completed, the data structure block is released. This allows the
was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess interpretingprocessortocomebackandreadthecompletedatastructure,
theirassignedportionsofmemorycontinuouslywithoutanywaitstates. therebyguaranteeingaconsistentdatastructure.
L PORT
SEMAPHORE
R PORT
SEMAPHORE
REQUEST FLIP FLOP
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
2740 drw 20
Figure 4. IDT7024 Semaphore Logic
6.42
20
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
OrderingInformation
XXXXX
A
999
A
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Blank
Industrial (-40°C to +85°C)
Military (-55°C to +125°C)
I(1)
B
Compliant to MIL-PRF-38535 QML
G(2)
Green
PF
G
J
100-pin TQFP (PN100-1)
84-pin PGA (G84-3)
84-pin PLCC (J84-1)
84-pin Flatpack (F84-2)
F
15
17
20
25
35
55
70
Commercial Only
Commercial Only
Commercial, Industrial & Military
Commercial & Military
Commercial & Military
Commercial, Industrial & Military
Military Only
Speed in
nanoseconds
S
L
Standard Power
Low Power
7024
64K (4K x 16) Dual-Port RAM
2740 drw 21
NOTE:
1. Industrial temperature range is available on selected PLCC packages in standard power. For other speeds, packages and powers contact your sales office.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
DatasheetDocumentHistory
1/13/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Pages2and3Addedadditionalnotestopinconfigurations
Changeddrawingformat
Page 1 CorrectedDSCnumber
Replaced IDT logo
6/4/99:
4/4/00:
Page 6CorrectedtypoinData Retentionchart
Changed±500mVto0mVinnotes
5/19/00:
Page 3 ClarifiedTAparameter
Page 4 Increasedstoragetemperatureparameter
Pages 5and6DCElectricalparameters–changedwordingfrom"open"to"disabled"
Datasheet Document History continued on page 22
6.42
21
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory(continued)
9/12/01:
Page 2 & 3 Added date revision for pin configurations
Page 5 AddedIndustrialtemptothecolumnheadingfor20nstoDCElectricalCharacteristics
Pages8,10,13&15 AddedIndustrialtemptothecolumnheadingsfor20nstoACElectricalCharacteristics
Pages3,5,6,8,10,13&15 RemovedIndustrialtempnotefromalltablesfootnotes
Page 21 AddedIndustrialto20nsorderinginformation
07/25/05:
10/29/08:
Page 1 Addedgreenavailabilitytofeatures
Page 21 Addedgreenindicatortoorderinginformation
Page 1 & 21 Replaced old IDT ® logo with the new IDTTM logo
Page21Updatedaddressandphonecontactinformation
Page 21 Removed "IDT" from orderable part number
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-824-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
22
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