IDT70261L25PF9_技术文档

HIGH-SPEED

IDT70261S/L

16K x 16 DUAL-PORT

STATIC RAM WITH INTERRUPT

Features

◆

True Dual-Ported memory cells which allow simultaneous

IDT70261 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = H for BUSY output flag on Master,

M/S = L for BUSY input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in 100-pin Thin Quad Flatpack

Industrial temperature range (-40^OC to +85^OC) is available

for selected speeds

access of the same memory location

High-speed access

◆

– Commercial:15/20/25/35/55ns(max.)

– Industrial20/25ns (max.)

Low-power operation

◆

– IDT70261S

Active:750mW(typ.)

Standby: 5mW (typ.)

– IDT70261L

◆

Active:750mW(typ.)

Standby: 1mW (typ.)

Separate upper-byte and lower-byte control for multiplexed

◆

bus compatibility

FunctionalBlockDiagram

R/

UB

W

L

R/

W

R

UB

LB

CE

OE

L

LB

CE

OE

R

L

R

I/O8L-I/O15L

I/O8R-I/O15R

I/O

Control

I/O0L-I/O7L

(1,2)

I/O0R-I/O7R

(1,2)

BUSY

L

BUSY

R

A

13L

A

13R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A

0L

A

0R

14

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE

OE

R/W

R

CE

OE

R/W

L

R

L

R

L

SEM

R

(2)

SEM

L

(2)

INTR

INTL

M/S

3039 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY and INT outputs are non-tri-stated push-pull.

NOVEMBER 2001

1

DSC 3039/9

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Description

address,andI/Opinsthatpermitindependent,asynchronousaccessfor

reads or writes to any location in memory. An automatic power down

featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter

a very low standby power mode.

FabricatedusingIDT’sCMOShigh-performancetechnology,these

devices typicallyoperate ononly750mWofpower.

TheIDT70261is ahigh-speed16Kx16Dual-PortStaticRAM.The

IDT70261isdesignedtobeusedasastand-aloneDual-PortRAMoras

acombinationMASTER/SLAVEDual-PortRAMfor32-bit-or-moreword

systems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproachin32-

bitorwidermemorysystemapplicationsresultsinfull-speed,error-free

operationwithouttheneedforadditionaldiscretelogic.

The IDT70261 is packaged in a 100-pin TQFP.

This device provides two independent ports with separate control,

PinConfigurations^(1,2,3)

11/16/01

Index

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

N/C

2

3

4

A

6L

5L

4L

3L

2L

1L

0L

N/C

5

I/O10L

I/O11L

I/O12L

I/O13L

GND

I/O14L

I/O15L

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

IDT70261PF

PN100-1⁽⁴⁾

INT

L

BUSY

GND

M/S

L

VCC

GND

I/O0R

I/O1R

I/O2R

100-Pin TQFP

Top View⁽⁵⁾

BUSY

R

INT

R

A

0R

1R

2R

3R

4R

5R

VCC

I/O3R

I/O4R

I/O5R

I/O6R

N/C

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

,

3039 drw 02

PinNames

NOTES:

1. All V^CCpins must be connected to power supply.

Left Port

Right Port

Names

2. All GND pins must be connected to ground supply.

Chip Enable

CE

R/W

OE

L

CE

R/W

OE

R

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

L

R

Read/Write Enable

Output Enable

Address

L

R

A0L - A13L

A0R - A13R

I/O0L - I/O15L

I/O0R - I/O15R

Data Input/Output

Semaphore Enable

Upper Byte Select

Lower Byte Select

Interrupt Flag

SEM

UB

LB

INT

BUSY

L

SEM

UB

LB

INT

BUSY

M/S

R

L

R

L

R

L

R

Busy Flag

L

R

Master or Slave Select

Power

V

CC

GND

Ground

3039 tbl 01

6.42

2

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

MaximumOperatingTemperature

andSupplyVoltage^(1,2)

RecommendedDCOperating

Conditions

Symbol

Parameter

Supply Voltage

GND Ground

Min.

Typ. Max. Unit

Ambient

Grade

Commercial

Industrial

Temperature

0^OC to +70^OC

-40^OC to +85^OC

GND

0V

Vcc

VCC

4.5

5.0

5.5

0

V

5.0V

+

10%

0

0V

10%

V

IH

Input High Voltage

Input Low Voltage

2.2

6.0⁽²⁾

0.8

____

3039 tbl 02

VIL

-0.5⁽¹⁾

V

NOTES:

____

1. This is the parameter TA. This is the "instant on"case temperature.

3039 tbl 03

NOTES:

1. V^IL> -1.5V for pulse width less than 10ns.

2. V^TERMmust not exceed Vcc + 10%.

Truth Table I – Non-Contention Read/Write Control

Inputs⁽¹⁾

Outputs

R/W

X

L

I/O8-15

I/O0-7

Mode

CE

H

X

L

OE

X

L

UB

X

H

L

LB

X

H

L

SEM

H

High-Z

High-Z Deselected: Power-Down

High-Z Both Bytes Deselected

H

DATAIN

High-Z

DATAIN

Write to Upper Byte Only

Write to Lower Byte Only

Write to Both Bytes

L

H

L

H

L

H

DATAIN

DATAOUT

High-Z

L

H

X

L

H

L

H

High-Z Read Upper Byte Only

DATAOUT Read Lower Byte Only

DATAOUT Read Both Bytes

High-Z Outputs Disabled

L

H

L

H

L

H

DATAOUT

High-Z

X

H

X

3039 tbl 04

NOTE:

1. A^0L— A13L ≠ A0R — A13R.

Truth Table II – Semaphore Read/Write Control⁽¹⁾

Inputs

Outputs

R/W

H

I/O8-15

I/O0-7

Mode

CE

H

OE

L

UB

X

LB

X

SEM

L

DATAOUT

DATAOUT Read Data in Semaphore Flag

X

H

L

H

L

↑

H

X

L

DATAIN

Write I/O into Semaphore Flag

0

↑

X

L

X

H

L

H

X

L

DATAIN

Write I/O0 into Semaphore Flag

______

Not Allowed

______

X

3039 tbl 05

NOTE:

1. There are eight semaphore flags written to via I/O⁰and read from all I/O's(I/O0 - I/O15). These eight semaphores are addressed by A0 - A2.

3

6.42

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

AbsoluteMaximumRatings⁽¹⁾

Capacitance⁽¹⁾(TA = +25°C, f = 1.0Mhz)

Conditions⁽²⁾

IN = 3dV

OUT = 3dV

Max. Unit

Symbol

Rating

Commercial

& Industrial

Unit

Symbol

Parameter

CIN

Input Capacitance

V

9

pF

(2)

V

TERM

Terminal Voltage

with Respect

to GND

-0.5 to +7.0

V

Output

Capacitance

V

10

COUT

3039 tbl 07

Te mp e rature

Under Bias

-55 to +125

-65 to +150

50

^oC

T

BIAS

NOTES:

1. This parameter is determined by device characterization but is not production

tested.

2. 3dV represents the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

TSTG

Storage

Te mp e rature

DC Output

Current

mA

IOUT

3039 tbl 06

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those

indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect

reliability.

2. V^TERMmust not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)

70261S

70261L

Symbol

|I^LI

|I^LO

Parameter

Test Conditions

Min.

Max.

10

Min.

Max.

5

Unit

µA

V

(1)

___

|

Input Leakage Current

Output Leakage Current

Output Low Voltage

V

CC = 5.5V, VIN = 0V to VCC

___

|

10

5

CE = V^IH, VOUT = 0V to VCC

V

OL

OH

NOTE:

I

OL = 4mA

0.4

___

V

Output High Voltage

I

OH = -4mA

2.4

V

3039 tbl 08

1. At Vcc < 2.0V, input leakages are undefined.

5V

AC Test Conditions

Input Pulse Levels

GND to 3.0V

3ns

893Ω

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

DATAOUT

BUSY

INT

DATAOUT

1.5V

30pF

347Ω

5pF*

Figures 1 and 2

3039 tbl 09

3039 drw 04

3039 drw 03

Figure 1. AC Output Test Load

Figure 2. Output Test Load

(for t^LZ, tHZ, tWZ, tOW)

*Including scope and jig.

6.42

4

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range⁽¹⁾(VCC = 5.0V ± 10%)

70261X15

70261X20

Com'l & Ind

70261X25

Com'l & Ind

Com'l Only

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

ICC

Dynamic Operating Current

(Both Ports Active)

S

L

190

325

285

180

315

275

170

305

265

mA

CE = VIL, Outputs Disabled

SEM = VIH

(3)

f = fMAX

____

IND

S

L

170

345

____

180

315

I

SB1

Standby Current

(Both Ports - TTL Level

Inputs)

COM'L

IND

S

L

35

95

70

30

85

60

25

85

60

mA

CE

SEM

f = fMAX

L

= CE

R

= VIH

R

= SEM

L

(3)

____

S

L

25

100

____

30

80

(5)

ISB2

Standby Current

(One Port - TTL Level Inputs)

COM'L

S

L

125

220

190

115

210

180

105

200

170

CE^"A"= VIL and CE"B" = VIH

Active Port Outputs Disabled,

(3)

f=fMAX

SEMR = SEML = VIH

____

IND

S

L

105

230

____

115

210

I

SB3

Full Standby Current (Both

Ports - All CMOS Level

Inputs)

Both Ports CE

CE > VCC - 0.2V

IN > VCC - 0.2V or

IN < 0.2V, f = 0⁽⁴⁾

SEM = SEM > VCC - 0.2V

L

and

COM'L

IND

S

L

1.0

0.2

15

5

1.0

0.2

15

5

1.0

0.2

15

5

mA

R

V

____

S

L

1.0

30

____

0.2

10

R

L

ISB4

Full Standby Current

(One Port - All CMOS Level

Inputs)

COM'L

IND

S

L

120

195

170

110

185

160

100

170

145

CE^"A"< 0.2V and

(5)

CE^"B"> VCC - 0.2V

SEM = SEM > VCC - 0.2V

R

L

____

S

L

100

200

V

IN > VCC - 0.2V or VIN < 0.2V

____

110

185

Active Port Outputs Disabled

(3)

f = fMAX

3039 tbl 10

70261X35

Com'l Only

70261X55

Com'l Only

Symbol

Parameter

Test Condition

Version

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

I

CC

Dynamic Operating

Current

COM'L

S

L

160

295

255

150

270

230

mA

CE = VIL, Outputs Disabled

SEM = VIH

(3)

(Both Ports Active)

f = fMAX

____

IND

S

L

mA

ISB1

Standby Current

(Both Ports - TTL Level

Inputs)

COM'L

IND

S

L

20

85

60

13

85

60

CE

SEM

f = fMAX

L

= CE

R

= VIH

R

= SEM

L

(3)

____

S

L

(5)

ISB2

Standby Current

(One Port - TTL Level

Inputs)

COM'L

IND

S

L

95

185

155

85

165

135

CE"A" = VIL and CE"B" = VIH

Active Port Outputs Disabled,

(3)

f=fMAX

SEM

____

S

L

R

= SEM

L

= VIH

and

ISB3

Full Standby Current

(Both Ports - All CMOS

Level Inputs)

Both Ports CE

CE > VCC - 0.2V

IN > VCC - 0.2V or

IN < 0.2V, f = 0⁽⁴⁾

SEM = SEM > VCC - 0.2V

L

COM'L

IND

S

L

1.0

0.2

15

5

1.0

0.2

15

5

R

V

____

S

L

R

L

ISB4

Full Standby Current

(One Port - All CMOS

Level Inputs)

COM'L

IND

S

L

90

160

135

80

135

110

CE^"A"< 0.2V and

(5)

CE^"B"> VCC - 0.2V

SEM = SEM > VCC - 0.2V

R

L

____

S

L

V

IN > VCC - 0.2V or VIN < 0.2V

Active Port Outputs Disabled

(3)

f=fMAX

3039 tbl 11

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

2. V^CC= 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

3. At f = f^MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using

“AC Test Conditions” of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

5

6.42

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽⁴⁾

70261X15

70261X20

Com'l & Ind

70261X25

Com'l & Ind

Com'l Only

Symbol

Parameter

Min.

Max.

Min. Max.

Min.

Max.

Unit

READ CYCLE

____

t

RC

AA

ACE

ABE

AOE

OH

LZ

HZ

PU

PD

SOP

SAA

Read Cycle Time

15

20

25

ns

____

t

Address Access Time

15

20

25

Chip Enable Access Time⁽³⁾

Byte Enable Access Time⁽³⁾

Output Enable Access Time

____

t

10

12

13

____

t

Output Hold from Address Change

Output Low-Z Time^(1,2)

3

____

t

3

Output High-Z Time^(1,2)

10

12

15

____

t

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

Semaphore Flag Update Pulse (OE or SEM)

Semaphore Address Access Time

0

____

t

15

20

25

____

t

10

12

____

t

15

20

25

ns

3039 tbl 12a

70261X35

Com'l Only

70261X55

Com'l Only

Symbol

READ CYCLE

Parameter

Min. Max.

Unit

____

t

RC

AA

ACE

ABE

AOE

OH

LZ

HZ

PU

PD

SOP

SAA

Read Cycle Time

35

55

ns

____

t

Address Access Time

35

55

Chip Enable Access Time⁽³⁾

Byte Enable Access Time⁽³⁾

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^(1,2)

____

t

20

30

____

t

3

____

t

3

Output High-Z Time^(1,2)

15

25

____

t

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

Semaphore Flag Update Pulse (OE or SEM)

Semaphore Address Access Time

0

____

t

35

50

____

t

15

____

t

35

55

ns

3039 tbl 12b

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.

4. 'X' in part numbers indicates power rating (S or L).

6.42

6

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Waveform of Read Cycles⁽⁵⁾

t

RC

ADDR

(4)

t

AA

(4)

ACE

CE

OE

(4)

tAOE

(4)

tABE

UB, LB

R/W

t

OH

(1)

tLZ

VALID DATA⁽⁴⁾

DATAOUT

BUSYOUT

NOTES:

(2)

t

HZ

(3, 4)

3039 drw 05

tBDD

1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.

3. t^BDDdelay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last t^AOE, tACE, tAA or tBDD.

5. SEM = V^IH.

Timing of Power-Up Power-Down

CE

tPU

tPD

I

CC

SB

50%

I

,

3039 drw 06

7

6.42

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltage⁽⁵⁾

70261X15

70261X20

Com'l & Ind

70261X25

Com'l & Ind

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

t

WC

EW

AW

AS

WP

WR

DW

HZ

DH

WZ

OW

SWRD

SPS

Write Cycle Time

15

12

0

20

15

0

25

20

0

ns

t

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

t

12

0

15

0

20

0

t

Write Recovery Time

t

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

10

15

____

t

10

12

15

____

t

0

(1,2)

____

t

Write Enable to Output in High-Z

Output Active from End-of-Write^{(1, 2,4)}

SEM Flag Write to Read Time

SEM Flag Contention Window

10

12

15

____

t

0

5

0

5

0

5

____

t

ns

3039 tbl 13a

70261X35

Com'l Only

70261X55

Com'l Only

Symbol

WRITE CYCLE

Parameter

Min.

Max.

Min.

Max.

Unit

____

t

WC

EW

AW

AS

WP

WR

DW

HZ

DH

WZ

OW

SWRD

SPS

Write Cycle Time

35

30

0

55

45

0

ns

t

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

t

25

0

40

0

t

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

t

15

30

____

t

15

25

____

t

0

(1,2)

____

t

Write Enable to Output in High-Z

Output Active from End-of-Write^{(1, 2,4)}

SEM Flag Write to Read Time

SEM Flag Contention Window

15

25

____

t

0

5

0

5

____

t

ns

3039 tbl 13b

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for t^DHmust be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage

and temperature, the actual t^DHwill always be smaller than the actual tOW.

5. 'X' in part numbers indicates power rating (S or L).

6.42

8

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(1,5,8)

tWC

ADDRESS

(7)

tHZ

OE

t

AW

CE or SEM ⁽⁹⁾

UB or LB ⁽⁹⁾

R/W

(3)

(2)

(6)

t

AS

tWR

tWP

(7)

t

OW

t

WZ

(4)

DATAOUT

DATAIN

tDW

tDH

3039 drw 07

Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing^(1,5)

tWC

ADDRESS

CE or SEM⁽⁹⁾

UB or LB⁽⁹⁾

t

AW

(3)

(2)

(6)

tWR

t

AS

tEW

R/W

t

DW

tDH

DATAIN

3039 drw 08

NOTES:

1. R/W or CE or UB and LB = V^IHduring all address transitions.

2. A write occurs during the overlap (t^EWor tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.

3. t^WRis measured from the earlier of CE or R/W (or SEM or R/W) going VIH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM = V^ILtransition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure

2).

8. If OE = V^ILduring R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required t^DW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified t^WP.

9. To access RAM, CE = V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

9

6.42

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾

t

OH

t

SAA

VALID ADDRESS

A0-A2

tWR

tACE

t

AW

t

EW

SEM

tSOP

t

DW

DATAIN

VALID

DATAOUT

I/O0

(2)

VALID

t

AS

t

WP

tDH

R/W

tSWRD

tAOE

OE

Write Cycle

Read Cycle

3039 drw 09

NOTES:

1. CE = V^IHor UB and LB = VIH for the duration of the above timing (both write and read cycle).

2. "DATA^OUTVALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.

Timing Waveform of Semaphore Write Contention^(1,3,4)

A

0"A"-A2"A"

MATCH

SIDE⁽²⁾

"A"

R/W"A"

SEM"A"

tSPS

A

0"B"-A2"B"

MATCH

SIDE⁽²⁾

"B"

R/W"B"

SEM"B"

3039 drw 10

NOTES:

1. D^OR= DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.

2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/W"^A"or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If t^SPSis not satisfied, there is no guarantee which side will be granted the semaphore flag.

6.42

10

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange^(6,7)

70261X15

70261X20

Com'l & Ind

70261X25

Com'l & Ind

Com'l Only

Symbol

BUSY TIMING (M/S=VIH

Parameter

Min.

Max.

Min. Max.

Min.

Max.

Unit

)

____

t

BAA

BDA

BAC

BDC

APS

BDD

WH

15

20

ns

BUSY Access Time from Address Match

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable Low

BUSY Access Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

t

15

17

____

t

5

____

BUSY Disable to Valid Data⁽³⁾

t

18

30

t

Write Hold After BUSY⁽⁵⁾

12

15

17

____

BUSY TIMING (M/S=VIL

)

____

BUSY Input to Write⁽⁴⁾

Write Hold After BUSY⁽⁵⁾

t

WB

0

ns

tWH

12

15

17

PORT-TO-PORT DELAY TIMING

____

t

WDD

Write Pulse to Data Delay⁽¹⁾

30

25

45

30

50

35

ns

tDDD

Write Data Valid to Read Data Delay⁽¹⁾

ns

3039 tbl 14a

70261X35

Com'l Only

70261X55

Com'l Only

Symbol

BUSY TIMING (M/S=VIH

Parameter

Min.

Max.

Min.

Max.

Unit

)

____

t

BAA

BDA

BAC

BDC

APS

BDD

WH

20

45

40

ns

BUSY Access Time from Address Match

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable Low

BUSY Access Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

t

20

35

____

t

5

____

BUSY Disable to Valid Data⁽³⁾

t

35

40

t

Write Hold After BUSY⁽⁵⁾

25

____

BUSY TIMING (M/S=VIL

)

____

BUSY Input to Write⁽⁴⁾

Write Hold After BUSY⁽⁵⁾

t

WB

0

ns

tWH

25

PORT-TO-PORT DELAY TIMING

____

t

WDD

Write Pulse to Data Delay⁽¹⁾

60

45

80

65

ns

tDDD

Write Data Valid to Read Data Delay⁽¹⁾

ns

3039 tbl 14b

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Wave form of Write with Port-to-Port Read and BUSY (M/S = V^IH)".

2. To ensure that the earlier of the two ports wins.

3. t^BDDis a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 'X' in part numbers indicates power rating (S or L).

11

6.42

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

TimingWaveformof WritewithPort-to-PortReadandBUSY (M/S =VIH)^(2,4,5)

t

WC

MATCH

ADDR"A"

tWP

R/W"A"

tDW

tDH

VALID

DATAIN "A"

(1)

tAPS

MATCH

ADDR"B"

tBAA

tBDA

tBDD

BUSY"B"

tWDD

VALID

DATAOUT "B"

(3)

tDDD

3039 drw 11

NOTES:

1. To ensure that the earlier of the two ports wins. t^APSis ignored for M/S = VIL (SLAVE).

2. CE^L= CER = VIL.

3. OE = VIL for the reading port.

4. If M/S = V^IL(slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

Timing Waveform of Write with BUSY (M/S = VIL)

tWP

R/W"A"

(3)

tWB

BUSY"B"

(1)

tWH

R/W"B"

(2)

,

3039 drw 12

NOTES:

1. t^WHmust be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. t^WBis only for the “SLAVE” version.

6.42

12

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing(M/S = VIH)⁽¹⁾

ADDR"A"

and "B"

ADDRESSES MATCH

CE"A"

(2)

tAPS

CE"B"

tBAC

t

BDC

BUSY"B"

3039 drw 13

Waveform of BUSY Arbitration Cycle Controlled by

Address Match Timing(M/S = VIH)⁽¹⁾

ADDR"A"

ADDR"B"

BUSY"B"

ADDRESS "N"

(2)

tAPS

MATCHING ADDRESS "N"

t

BAA

tBDA

3039 drw 14

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. If t^APSis not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽¹⁾

70261X15

70261X20

70261X25

Com'l Only

Com'l & Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

____

t

AS

WR

INS

INR

Address Set-up Time

Write Recovery Time

Interrupt Set Time

0

ns

t

0

____

t

15

20

____

t

Interrupt Reset Time

ns

3039 tbl 15a

70261X35

Com'l Only

70261X55

Com'l Only

Symbol

INTERRUPT TIMING

Parameter

Min.

Max.

Min.

Max.

Unit

____

t

AS

WR

INS

INR

Address Set-up Time

Write Recovery Time

Interrupt Set Time

0

ns

t

0

____

t

25

40

____

t

Interrupt Reset Time

ns

3039 tbl 15b

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

13

6.42

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing⁽¹⁾

t

WC

INTERRUPT SET ADDRESS ⁽²⁾

ADDR"A"

(4)

(3)

t

AS

tWR

CE"A"

R/W"A"

INT"B"

(3)

t

INS

3039 drw 15

t

RC

INTERRUPT CLEAR ADDRESS ⁽²⁾

ADDR"B"

CE"B"

(3)

t

AS

OE"B"

(3)

t

INR

INT"B"

3039 drw 16

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. See Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

TruthTables

Truth Table III — Interrupt Flag⁽¹⁾

Left Port

Right Port

OE

R/WL

A13L-A0L

R/WR

A

13R-A0R

Function

Set Right INT Flag

Reset Right INT Flag

Set Left INT Flag

Reset Left INT Flag

CEL

OEL

INTL

CER

R

INTR

(2)

L

X

L

X

L

3FFF

X

L

X

L

X

L

X

3FFF

3FFE

X

L

R

(3)

X

H

R

(3)

X

L

X

L

(2)

X

3FFE

H

X

L

3039 tbl 16

NOTES:

1. Assumes BUSYL = BUSYR =VIH.

2. If BUSY^L= VIL, then no change.

3. If BUSY^R= VIL, then no change.

6.42

14

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

Truth Table IV —

AddressBUSY Arbitration

Inputs

Outputs

A

OL-A13L

(1)

AOR-A13R

Function

Normal

CE

L

CE

R

BUSY

L

BUSYR

X

H

X

L

X

H

L

NO MATCH

MATCH

H

MATCH

H

(3)

MATCH

(2)

Write Inhibit

3039 tbl 17

NOTES:

1. Pins BUSY^Land BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70261 are

push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If t^APSis not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSY^Loutputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSY^Routputs are driving LOW regardless of actual logic level on the pin.

Truth Table V — Example of Semaphore Procurement Sequence^(1,2,3)

Functions

D0 - D15 Left

D0

- D15 Right

Status

No Action

1

0

1

0

1

0

1

0

1

0

1

Semaphore free

Left Port Writes "0" to Semaphore

Right Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "1" to Semaphore

Right Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left port has semaphore token

No change. Right side has no write access to semaphore

Right port obtains semaphore token

No change. Left port has no write access to semaphore

Left port obtains semaphore token

Semaphore free

Right port has semaphore token

Semaphore free

Left port has semaphore token

Semaphore free

3039 tbl 18

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70261.

2. There are eight semaphore flags written to via I/O⁰and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.

3. CE = V^IH,SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

FunctionalDescription

(INT^L) is asserted when the right port writes to memory location 3FFE

(HEX), where a write is defined as CER = R/WR = VIL per Truth Table

III. The left port clears the interrupt through access of address location

3FFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right

portinterruptflag(INTR)isassertedwhentheleftportwritestomemory

location3FFF(HEX)andtocleartheinterruptflag(INTR),therightport

mustreadthememorylocation3FFF.Themessage(16bits)at3FFEor

3FFF is user-defined since it is an addressable SRAM location. If the

interruptfunctionisnotused,addresslocations3FFEand3FFFarenot

usedasmailboxes,butaspartoftherandomaccessmemory.Referto

TruthTableIIIfortheinterruptoperation.

TheIDT70261providestwoportswithseparatecontrol,addressand

I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation

in memory. The IDT70261 has an automatic power down feature

controlled by CE. The CE controls on-chip power down circuitry that

permitstherespectiveporttogointoastandbymodewhennotselected

(CE = VIH). Whena portis enabled, access tothe entire memoryarray

ispermitted.

Interrupts

Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox

ormessage center)is assignedtoeachport. The leftportinterruptflag

15

6.42

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables.Failure

toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland

corrupteddataintheslave.

BusyLogic

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.

TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon

theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom

thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally

topreventthewritefromproceeding.

Semaphores

TheIDT70261isanextremelyfastDual-Port16Kx16CMOSStatic

RAMwithanadditional8addresslocationsdedicatedtobinarysemaphore

flags.TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-

PortRAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefined

bythesystemdesigner’ssoftware.Asanexample,thesemaphorecan

beusedbyoneprocessortoinhibittheotherfromaccessingaportionof

the Dual-Port RAM or any other shared resource.

TheuseofBUSYlogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

anduse anyBUSYindicationas aninterruptsource toflagthe eventof

anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis

notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave

modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

the BUSY pins high. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port low.

TheBUSYoutputsontheIDT70261RAMinmastermode,arepush-

pulltypeoutputsanddonotrequirepullupresistorstooperate.Ifthese

RAMs are being expanded in depth, then the BUSY indication for the

resulting array requires the use of an external AND gate.

The Dual-PortRAMfeatures a fastaccess time, andbothports are

completelyindependentofeachother.Thismeansthattheactivityonthe

leftportinnowayslows theaccess timeoftherightport.Bothports are

identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,

orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphorelocation.Semaphoresareprotectedagainstsuchambiguous

situationsandmaybeusedbythesystemprogramtoavoidanyconflicts

inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave

anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM

enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol

on-chippowerdowncircuitrythatpermits the respective porttogointo

standbymodewhennotselected. Thisistheconditionwhichisshownin

Truth Table V where CE and SEM are both HIGH.

CE

MASTER

Dual Port

RAM

SLAVE

Dual Port

RAM

BUSY

L

BUSY

L

BUSY

R

BUSY

R

SystemswhichcanbestusetheIDT70261containmultipleprocessors

or controllers and are typically very high-speed systems which are

softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom

a performance increase offered by the IDT70261's hardware sema-

phores,whichprovidealockoutmechanismwithoutrequiringcomplex

programming.

MASTER

Dual Port

RAM

CE

SLAVE

Dual Port

RAM

CE

BUSY

R

BUSY

L

BUSY

L

BUSY

R

BUSYR

BUSY

L

,

3039 drw 17

Softwarehandshakingbetweenprocessors offers themaximumin

systemflexibilitybypermittingsharedresourcestobeallocatedinvarying

configurations.TheIDT70261doesnotuseitssemaphoreflagstocontrol

anyresourcesthroughhardware,thusallowingthesystemdesignertotal

flexibilityinsystemarchitecture.

An advantage of using semaphores rather than the more common

methodsofhardwarearbitrationisthatwaitstatesareneverincurredin

either processor. This can prove to be a major advantage in very high-

speedsystems.

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT70261 RAMs.

Width Expansion with Busy Logic

Master/SalveArrays

WhenexpandinganIDT70261RAMarrayinwidthwhileusingBUSY

logic,onemasterpartis usedtodecidewhichsideoftheRAMarraywill

receiveaBUSYindication,andtooutputthatindication.Anynumberof

slavestobeaddressedinthesameaddressrangeasthemaster,usethe

BUSYsignalasawriteinhibitsignal.ThusontheIDT70261RAMtheBUSY

pinisanoutputifthepartisusedasamaster(M/Spin=VIH),andtheBUSY

pin is an input if the part used as a slave (M/S pin = VIL) as shown in

Figure 3.

How the Semaphore Flags Work

Thesemaphorelogicisasetofeightlatcheswhichareindependent

oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,

fromoneporttotheothertoindicatethatasharedresourceisinuse.The

semaphores provide a hardware assist for a use assignment method

called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore

latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft

processorwantstousethisresource,itrequeststhetokenbysettingthe

latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading

it. If it was successful, it proceeds to assume control over the shared

resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe

rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe

sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

decisioncouldresultwithonemasterindicatingBUSYononesideofthe

arrayandanothermasterindicatingBUSYononeothersideofthearray.

Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.

TheBUSYarbitration,onamaster,is basedonthechipenableand

address signals only. It ignores whether an access is a read or write. In

a master/slave array, both address and chip enable must be valid long

enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite

6.42

16

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

that semaphore’s status or remove its request for that semaphore to into a semaphore flag. Whichever latch is first to present a zero to the

performanothertaskandoccasionallyattemptagaintogaincontrolofthe semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother

tokenviathesetandtestsequence.Oncetherightsidehasrelinquished sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame

thetoken,theleftsideshouldsucceedingainingcontrol.

semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch

Thesemaphoreflagsareactivelow.Atokenisrequestedbywriting havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip

azerointoasemaphorelatchandisreleasedwhenthesamesidewrites

aonetothatlatch.

L PORT

SEMAPHORE

R PORT

TheeightsemaphoreflagsresidewithintheIDT70261inaseparate

memoryspacefromtheDual-PortRAM.This addressspaceisaccessed

byplacingalowinputontheSEMpin(whichactsasachipselectforthe

semaphore flags) and using the other control pins (Address, OE, and

R/W)as theywouldbeusedinaccessingastandardStaticRAM.Each

oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside

throughaddresspinsA0 –A2. Whenaccessingthesemaphores,none

oftheotheraddresspinshasanyeffect.

SEMAPHORE

REQUEST FLIP FLOP

0

D

0

D

Q

WRITE

SEMAPHORE

READ

SEMAPHORE

READ

,

Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel

iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero

onthatsideandaoneontheotherside(seeTableV).Thatsemaphore

can now only be modified by the side showing the zero. When a one is

writtenintothesamelocationfromthesameside,theflagwillbesettoa

one for both sides (unless a semaphore request from the other side is

pending)andthencanbewrittentobybothsides.Thefactthattheside

whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites

fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor

communications.(Athoroughdiscussionontheuseofthisfeaturefollows

shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe

storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis

freedbythefirstside.

Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso

thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining

azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput

registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)

signalsgoactive.Thisservestodisallowthesemaphorefromchanging

stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.

Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust

cause either signal (SEM or OE) to go inactive or the output will never

change.

AsequenceWRITE/READmustbeusedbythesemaphoreinorder

to guarantee that no system level contention will occur. A processor

requestsaccesstosharedresourcesbyattemptingtowriteazerointoa

semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore

requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,

afactwhichtheprocessorwillverifybythesubsequentread(seeTable

V).Asanexample,assumeaprocessorwritesazerototheleftportata

freesemaphorelocation.Onasubsequentread,theprocessorwillverify

thatithaswrittensuccessfullytothatlocationandwillassumecontrolover

the resource in question. Meanwhile, if a processor on the right side

attempts towriteazerotothesamesemaphoreflagitwillfail,as willbe

verifiedbythefactthataonewillbereadfromthatsemaphoreontheright

side during subsequent read. Had a sequence of READ/WRITE been

usedinstead,systemcontentionproblemscouldhaveoccurredduringthe

gap between the read and write cycles.

3039 drw 18

Figure 4. IDT70261 Semaphore Logic

overtotheothersideassoonasaoneiswrittenintothefirstside’srequest

latch.Thesecondside’sflagwillnowstaylowuntilitssemaphorerequest

latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore

is requestedandthe processorwhichrequesteditnolongerneeds the

resource, the entire system can hang up until a one is written into that

semaphorerequestlatch.

The critical case of semaphore timing is when both sides request

a single token by attempting to write a zero into it at the same time.

The semaphore logic is specially designed to resolve this problem.

If simultaneous requests are made, the logic guarantees that only one

sidereceivesthetoken.Ifonesideisearlierthantheotherinmakingthe

request, the firstside tomake the requestwillreceive the token. Ifboth

requestsarriveatthesametime,theassignmentwillbearbitrarilymade

to one port or the other.

One caution that should be noted when using semaphores is that

semaphoresalonedonotguaranteethataccesstoaresourceissecure.

Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused

ormisinterpreted, a software errorcaneasilyhappen.

Initializationofthesemaphoresisnotautomaticandmustbehandled

viatheinitializationprogramatpower-up.Sinceanysemaphorerequest

flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth

sidesshouldhaveaonewrittenintothematinitializationfrombothsides

to assure that they will be free when needed.

UsingSemaphores—SomeExamples

Perhapsthesimplestapplicationofsemaphoresistheirapplicationas

resourcemarkersfortheIDT70261’sDual-PortRAM.Saythe16Kx16

RAMwastobedividedintotwo8Kx16blockswhichweretobededicated

atanyonetimetoservicingeithertheleftorrightport.Semaphore0could

be used to indicate the side which would control the lower section of

memory,andSemaphore1couldbedefinedastheindicatorfortheupper

sectionofmemory.

Totakearesource,inthisexamplethelower8Kof Dual-PortRAM,

the processor on the left port could write and then read a zero in to

Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread

backratherthana one), the leftprocessorwouldassume controlofthe

lower8K. Meanwhiletherightprocessorwasattemptingtogaincontrol

Itisimportanttonotethatafailedsemaphorerequestmustbefollowed

byeitherrepeatedreadsorbywritingaoneintothesamelocation.The

reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram

ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed

17

6.42

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

ofthe resourceaftertheleftprocessor,itwouldreadbackaoneinresponse

tothezeroithadattemptedtowriteintoSemaphore0.Atthis point,the

softwarecouldchoosetotryandgaincontrolofthesecond8Ksectionby

writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining

control,itwouldlockouttheleftside.

Once the left side was finished with its task, it would write a one to

Semaphore 0 and may then try to gain access to Semaphore 1. If

Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo

itssemaphorerequestandperformothertasksuntilitwasabletowrite,then

readazerointoSemaphore1.Iftherightprocessorperformsasimilartask

withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap

8Kblocks ofDual-PortRAMwitheachother.

The blocks do not have to be any particular size and can even be

variable, depending upon the complexity of the software using the

semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual-

PortRAMorothersharedresources intoeightparts. Semaphores can

evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing

given a common meaning as was shown in the example above.

Semaphores are a useful form of arbitration in systems like disk

interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring

atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse

ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea

was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess

theirassignedportionsofmemorycontinuouslywithoutanywaitstates.

Semaphoresarealsousefulinapplicationswherenomemory“WAIT”

stateisavailableononeorbothsides.Onceasemaphorehandshakehas

been performed, both processors can access their assigned RAM

segmentsatfullspeed.

Anotherapplicationisintheareaofcomplexdatastructures.Inthis

case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor

mayberesponsibleforbuildingandupdatingadatastructure.Theother

processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting

processorreadsanincompletedatastructure,amajorerrorconditionmay

exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo

differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks

itandthenisabletogoinandupdatethedatastructure.Whentheupdate

is completed, the data structure block is released. This allows the

interpretingprocessortocomebackandreadthecompletedatastructure,

therebyguaranteeingaconsistentdatastructure.

6.42

18

IDT70261S/L

High-Speed 16K x 16 Dual-Port Static RAM with Interrupt

Industrial and Commercial Temperature Ranges

OrderingInformation

IDT XXXXX

A

999

A

Device

Type

Power

Speed

Package

Process/

Temperature

Range

Blank

I⁽¹⁾

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

PF

100-pin TQFP (PN100-1)

Commercial

15

20

25

35

55

Commercial & Industrial

Speed

Commercial & Industrial

in nanoseconds

Commercial Only

S

L

Standard Power

Low Power

256K (16K x 16) Dual-Port RAM with Interrupt

70261

3039 drw 19

NOTE:

1. Contactyourlocalsales officeforIndustrialtemprangeforotherspeeds,packages andpowers.

DatasheetDocumentHistory

1/14/99:

Initiateddatasheetdocumenthistory

Convertedtonewformat

Cosmeticandtypographicalcorrections

Pages 2 Addedadditionalnotestopinconfigurations

Changeddrawingformat

6/4/99:

Page 1 CorrectedDSCnumber

2/18/00:

AddedIndustrialTemperatureRangesandremovedrelatednotes

Replaced IDT logo

Changed±200mVintableandwaveformnotes to0mV

Page 3 ClarifiedTAparameter

5/22/00:

Page 4 Increasedstoragetemperatureparameter

Page 5 DCElectricalparameters–changedwordingfromopentodisabled

Page 2 Addeddaterevisionforpinconfiguration

11/20/01:

Page 5 RemovedIndustrialtempforstandardpower20nsspeedfromDCElectricalCharacteristics

RemovedIndustrialtempforlowpower25nsspeedfromDCElectricalCharacteristics

RemovedIndustrialtempforstandardandlowpowerfor35ns & 55ns speeds fromDCElectricalCharacteristics

Pages6,8,11&13 RemovedIndustrialtempfor35nsand55nsspeedsfromACElectricalCharacteristics

Page 19 RemovedIndustrialtempfrom35nsand55nsinorderinginformation

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

408-284-2794

DualPortHelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

19

6.42


型号：	IDT70261L25PF9
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Dual-Port SRAM, 16KX16, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 静态存储器
文件：	总19页 (文件大小：179K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT70261L25PF9 [IDT]

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