IDT7026S35JI [IDT]
Dual-Port SRAM, 16KX16, 35ns, CMOS, PQCC84, PLASTIC, LCC-84;
| 型号： | IDT7026S35JI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 16KX16, 35ns, CMOS, PQCC84, PLASTIC, LCC-84 静态存储器 内存集成电路 |
| 文件： | 总18页 (文件大小：267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED
IDT7026S/L
16K X 16 DUAL-PORT
STATIC RAM
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
IDT7026 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA and 84-pin PLCC
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
◆
◆
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25/35/55ns (max.)
– Military: 20/25/35/55ns (max.)
Low-power operation
◆
◆
◆
– IDT7026S
◆
◆
◆
◆
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7026L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multi-
plexed bus compatibility
◆
FunctionalBlockDiagram
R/
W
R
R
R/
W
UBL
L
UB
LB
CE
OE
L
LB
CER
OE
R
L
L
R
I/O8L-I/O15L
I/O0L-I/O7L
I/O8R-I/O15R
I/O
Control
I/O
Control
I/O0R-I/O7R
(1,2)
L
(1,2)
R
BUSY
BUSY
A
13R
A
13L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A0R
A
0L
14
14
ARBITRATION
SEMAPHORE
LOGIC
CE
L
CE
R
SEMR
SEM
L
M/S
2939 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs are non-tri-stated push-pull.
DECEMBER 2002
1
DSC 2939/12
©2001IntegratedDeviceTechnology,Inc.
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7026 is a high-speed 16K x 16 Dual-Port Static RAM. The
IDT7026 is designed to be used as a stand-alone Dual-Port RAM or as
acombinationMASTER/SLAVEDual-PortRAMfor32-bit-or-moreword
systems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproachin32-
bitorwidermemorysystemapplicationsresultsinfull-speed,error-free
operationwithouttheneedforadditionaldiscretelogic.
featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
FabricatedusingIDT’sCMOShigh-performancetechnology,these
devices typically operate on only 750mW of power.
The IDT7026 is packaged in a ceramic 84-pin PGA, and a 84-pin
PLCC.Militarygradeproductismanufacturedincompliancewiththelatest
revision of MIL-PRF-38535 QML, making it ideally suited to military
temperatureapplicationsdemandingthehighestlevelofperformanceand
reliability.
This device provides two independent ports with separate control,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
reads or writes to any location in memory. An automatic power down
PinConfigurations(1,2,3)
11/16/01
INDEX
11 10 9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
I/O8L
I/O9L
A
A
A
A
A
A
A
A
8L
7L
6L
5L
4L
3L
2L
1L
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O10L
I/O11L
I/O12L
I/O13L
GND
I/O14L
I/O15L
A0L
IDT7026J
J84-1(4)
BUSY
GND
M/S
L
VCC
GND
I/O0R
I/O1R
I/O2R
84-Pin PLCC
Top View(5)
BUSY
R
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
,
2939 drw 02
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. Package body is approximately 1.15 in x 1.15 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
11/16/01
63
I/O7L
61
I/O5L
60
I/O4L
58
I/O2L
55
I/O0L
54
51
48
46
45
42
11
10
09
08
07
06
05
04
03
02
01
A
12L
A
11L
A
8L
OE
L
SEM
L
LB
L
66
I/O10L
64
I/O8L
62
I/O6L
59
I/O3L
56
I/O1L
49
50
47
44
43
41
40
A
10L
A
9L
7L
4L
1L
A
6L
UB
L
CE
L
A
13L
67
I/O11L
65
I/O9L
68
I/O12L
71
I/O14L
70
57
53
52
39
R/W
L
GND
V
CC
A
A
5L
69
I/O13L
38
37
A
3L
A
72
I/O15L
73
33
35
34
36
BUSY
L
A
0L
A
VCC
IDT7026G
G84-3(4)
75
I/O0R
74
32
31
GND
GND
GND
M/S
A
2L
84-Pin PGA
Top View(5)
76
I/O1R
77
I/O2R
78
28
29
26
30
VCC
A0R
BUSY
R
A
1R
79
I/O3R
80
I/O4R
27
A
2R
A
3R
81
I/O5R
82
I/O6R
83
I/O7R
7
11
12
23
25
SEM
R
A
4R
A
6R
GND
GND
1
2
5
8
10
14
17
20
18
22
24
I/O9R
I/O10R I/O13R I/O15R
R/W
R
A
12R
A
9R
A
7R
A
5R
UB
R
84
I/O8R
3
4
6
9
15
13
16
19
21
I/O11R I/O12R I/O14R
A
11R
A
10R
A
8R
OER
LB
R
CER
A
13R
A
B
C
D
E
F
G
H
J
K
L
2939 drw 03
Index
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.12 in x 1.12 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
MaximumOperatingTemperature
andSupplyVoltage(1)
Ambient
Pin Names
Grade
Temperature
-55OC to+125OC
0OC to +70OC
-40OC to +85OC
GND
Vcc
Left Port
Right Port
Names
Military
0V
5.0V
+
+
+
10%
Chip Enable
Commercial
Industrial
0V
5.0V
5.0V
10%
10%
CE
R/W
OE
L
CE
R/W
OE
R
0V
L
R
Read/Write Enable
Output Enable
2939 tbl 02
L
R
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
A
0L - A13L
I/O0L - I/O15L
SEM
UB
LB
BUSY
A
0R - A13R
I/O0R - I/O15R
SEM
UB
LB
BUSY
M/S
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Busy Flag
Capacitance(1) (TA = +25°C, f = 1.0mhz)
L
R
Symbol
Parameter
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
L
R
CIN
Input Capacitance
V
9
pF
pF
L
R
Output
Capacitance
V
10
COUT
L
R
Master or Slave Select
Power
2939 tbl 03
NOTES:
V
CC
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
GND
Ground
2939 tbl 01
6.42
3
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I – Non-Contention Read/Write Control
Inputs(1)
Outputs
R/W
X
I/O8-15
I/O0-7
High-Z
High-Z
High-Z
DATAIN
DATAIN
High-Z
Mode
Deselected: Power-Down
CE
H
X
L
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
High-Z
High-Z
X
H
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
L
H
DATAIN
High-Z
L
L
H
L
H
L
L
L
H
DATAIN
DATAOUT
High-Z
L
H
H
H
X
L
H
L
H
Read Upper Byte Only
L
L
H
L
H
DATAOUT Read Lower Byte Only
DATAOUT Read Both Bytes
L
L
L
H
DATAOUT
High-Z
X
H
X
X
X
High-Z
Outputs Disabled
2939 tbl 04
NOTE:
1. A0L — A13L ≠ A0R — A13R.
Truth Table II – Semaphore Read/Write Control(1)
Inputs
Outputs
R/W
H
I/O8-15
I/O0-7
Mode
CE
H
OE
L
UB
X
LB
X
SEM
L
L
DATAOUT
DATAOUT
DATAOUT Read Data in Semaphore Flag
DATAOUT Read Data in Semaphore Flag
X
H
L
H
H
H
↑
X
X
X
L
DATAIN
DATAIN
Write I/O
0
0
into Semaphore Flag
into Semaphore Flag
X
L
L
↑
X
X
X
X
X
H
L
H
X
L
L
L
L
DATAIN
DATAIN
Write I/O
______
______
Not Allowed
Not Allowed
______
______
X
2939 tbl 05
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.
AbsoluteMaximumRatings(1)
Commercial
Symbol
Rating
Military
Unit
& Industrial
-0.5 to +7.0
-55 to +125
-55 to +125
50
(2)
V
TE RM
BIAS
STG
OUT
Terminal Voltage with Respect to GND
-0.5 to +7.0
-65 to +135
-65 to +150
50
V
T
Temperature Under Bias
Storage Temperature
DC Output Current
oC
oC
T
I
mA
2939 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of
VTERM > Vcc + 10%.
6.42
4
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
RecommendedDCOperating
Conditions
Symbol
Parameter
Min.
Typ. Max. Unit
V
CC
Supply Voltage
4.5
5.0
5.5
0
V
V
V
GND
Ground
0
0
V
V
IH
IL
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
-0.5(1)
V
____
2939 tbl 07
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
DC Electrical Characteristics Over the Operating
Temperature and Supply Soltage Range (VCC = 5.0V ± 10%)
7026S
7026L
Symbol
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
Min.
Max.
10
Min.
Max.
Unit
µA
µA
V
___
___
|ILI|
V
CC = 5.5V, VIN = 0V to VCC
5
5
___
___
___
___
|ILO
|
10
CE = VIH, VOUT = 0V to VCC
OL = 4mA
OH = -4mA
V
OL
OH
I
0.4
0.4
___
___
V
Output High Voltage
I
2.4
2.4
V
2939 tbl 08
NOTE:
1. At Vcc = 2.0V, input leakages are undefined.
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1 and 2
2939 tbl 09
5V
5V
893Ω
893Ω
DATAOUT
BUSY
DATAOUT
30pF
347Ω
5pF*
347Ω
2939 drw 04
2939 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.
6.42
5
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (con't.) (VCC = 5.0V ± 10%)
7026X15
Com'l Only
7026X20
Com'l, Ind
& Military.
7026X25
Com'l, Ind
& Military
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating Current
(Both Ports Active)
S
L
190
190
325
285
180
180
315
275
170
170
305
265
mA
CE = VIL, Outputs Disabled
SEM = VIH
(3)
f = fMAX
___
___
___
___
MIL &
IND
S
L
180
180
355
315
170
170
345
305
I
SB1
Standby Current
(B oth Ports - TTL Level
Inputs)
COM'L
S
L
35
35
95
70
30
30
85
60
25
25
85
60
mA
mA
CE
SEM
f = fMAX
L
= CE
R
= VIH
= VIH
R
= SEM
L
(3)
___
___
___
___
MIL &
IND
S
L
30
30
100
80
25
25
100
80
(5)
ISB2
Standby Current
(One Port - TTL Level Inputs)
COM'L
S
L
125
125
220
190
115
115
210
180
105
105
200
170
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
___
___
___
___
MIL &
IND
115
115
245
210
S
L
105
105
230
200
SEMR = SEML = VIH
I
SB3
Full Standby Current (Both
Ports - All CMOS Level
Inputs)
Both Ports CE
L
and
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
mA
mA
CER
> VCC - 0.2V
V
V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(4)
___
___
___
___
MIL &
IND
1.0
0.2
30
10
S
L
1.0
0.2
30
10
SEM
R
= SEM
L
> VCC - 0.2V
ISB4
Full Standby Current
(One Port - All CMOS Level
Inputs)
COM'L
S
L
120
120
195
170
110
110
185
160
100
100
170
145
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
___
___
___
___
MIL &
IND
110
110
210
185
S
L
100
100
200
175
V
IN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
(3)
f=fMAX
2939 tbl 10
7026X35
Com'l, Ind
& Military
7026X55
Com'l, Ind
& Military
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
COM'L
S
L
160
160
295
255
150
150
270
230
mA
CE = VIL, Outputs Disabled
SEM = VIH
(3)
f = fMAX
MIL &
IND
S
L
160
160
335
295
150
150
310
270
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
COM'L
S
L
20
20
85
60
13
13
85
60
mA
mA
CE
SEM
f = fMAX
L
= CE
R
= VIH
= VIH
R
= SEM
L
(3)
MIL &
IND
S
L
20
20
100
80
13
13
100
80
(5)
ISB2
Standby Current
(One Port - TTL Level
Inputs)
COM'L
S
L
95
95
185
155
85
85
165
135
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
MIL &
IND
S
L
95
95
215
185
85
85
195
165
SEM
R
= SEM
L
= VIH
I
SB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CE
L
and
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
mA
mA
CER
> VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(4)
= SEM > VCC - 0.2V
V
V
MIL &
IND
S
L
1.0
0.2
30
10
1.0
0.2
30
10
SEMR
L
ISB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
COM'L
S
L
90
90
160
135
80
80
135
110
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEMR = SEML > VCC - 0.2V
MIL &
IND
S
L
90
90
190
165
80
80
175
150
V
IN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
(3)
f=fMAX
2939 tbl 11
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using
“AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
6.42
6
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
7026X15
7026X20
7026X25
Com'l, Ind
& Military
Com'l Only
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
15
20
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Address Access Time
15
15
15
20
20
20
25
25
25
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time
____
____
____
____
____
____
____
____
____
t
t
t
10
12
13
____
____
____
t
Output Hold from Address Change
Output Low-Z Time(1,2)
3
3
3
____
____
____
t
3
3
3
Output High-Z Time(1,2)
10
12
15
____
____
____
t
t
Chip Enable to Power Up Time (2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
0
0
0
____
____
____
____
____
____
t
15
20
25
____
____
____
t
10
10
12
____
____
____
t
15
20
25
ns
2939 tbl 12a
7026X35
Com'l, Ind
& Military
7026X55
Com'l, Ind
& Military
Symbol
READ CYCLE
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
35
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
Address Access Time
35
35
35
55
55
55
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
____
____
t
t
t
20
30
____
____
t
3
3
____
____
t
3
3
Output High-Z Time(1,2)
15
25
____
____
t
t
Chip Enable to Power Up Time (2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
0
0
____
____
____
____
t
35
50
____
____
t
15
15
____
____
t
35
55
ns
2939 tbl 12b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
6.42
7
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
WAVEFORMOFREADCYCLES(5)
t
RC
ADDR
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
tAOE
(4)
tABE
UB, LB
R/W
t
OH
(1)
tLZ
VALID DATA(4)
DATAOUT
(2)
t
HZ
BUSYOUT
(3, 4)
2939 drw 06
t
BDD
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
Timing of Power-Up Power-Down
CE
tPU
tPD
I
CC
SB
50%
50%
I
,
2939 drw 07
6.42
8
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5,6)
7026X15
7026X20
Com'l, Ind
& Military
7026X25
Com'l, Ind
& Military
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
15
12
12
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
12
0
15
0
20
0
t
Write Recovery Time
t
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
10
15
15
____
____
____
t
10
12
15
____
____
____
t
0
0
0
(1,2)
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1, 2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
12
15
____
____
____
t
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
t
t
ns
3199 tbl 13a
7026X35
Com'l, Ind
& Military
7026X55
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
35
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
25
0
40
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
15
30
____
____
t
15
25
____
____
t
0
0
(1,2)
____
____
t
Write Enable to Output in High-Z
15
25
t
Output Active from End-of-Write(1, 2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
0
5
5
0
5
5
____
____
____
____
____
____
t
t
ns
2939 tbl 13b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
6.42
9
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
t
WC
ADDRESS
(7)
tHZ
OE
tAW
CE or SEM (9)
UB or LB(9)
(3)
(2)
(6)
t
WP
t
AS
tWR
R/W
DATAOUT
DATAIN
(7)
t
OW
tWZ
(4)
(4)
tDW
tDH
2939 drw 08
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
t
WC
ADDRESS
tAW
CE or SEM(9)
(3)
(2)
(6)
tWR
t
EW
t
AS
UB or LB(9)
R/W
t
DW
tDH
DATAIN
2939 drw 09
NOTES:
1. R/W or CE or UB and LB = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a VIL CE = VIL and R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going VIH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.42
10
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tOH
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
tWR
t
ACE
tAW
tEW
SEM
t
SOP
tDW
DATAOUT
DATAIN
VALID
I/O0
(2)
VALID
t
AS
tDH
tWP
R/W
tSWRD
tAOE
OE
Read Cycle
Write Cycle
2939 drw 10
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
(2)
SIDE
"A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
(2)
SIDE
"B"
R/W"B"
SEM"B"
2939 drw 11
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
6.42
11
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6,7)
7026X15
7026X20
7026X25
Com'l, Ind
& Military
Com'l Only
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S=VIH
)
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
t
15
17
17
____
____
____
t
5
5
5
____
____
____
t
18
30
30
BUSY Disable to Valid Data
(5)
____
____
____
t
Write Hold After BUSY
12
15
17
BUSY TIMING (M/S=VIL
)
____
____
____
____
____
____
BUSY Input to Write(4)
t
WB
0
0
0
ns
ns
(5)
tWH
Write Hold After BUSY
12
15
17
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
30
25
45
30
50
35
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
2939 tbl 14a
7026X35
Com'l, Ind
& Military
7026X55
Com'l, Ind
& Military
Symbol
BUSY TIMING (M/S=VIH
Parameter
Min.
Max.
Min.
Max.
Unit
)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
20
20
20
45
40
40
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
t
20
35
____
____
t
5
5
____
____
BUSY Disable to Valid Data(3)
t
35
40
(5)
____
____
t
Write Hold After BUSY
25
25
BUSY TIMING (M/S=VIL
)
____
____
____
____
BUSY Input to Write(4)
t
WB
0
0
ns
ns
(5)
tWH
Write Hold After BUSY
25
25
PORT-TO-PORT DELAY TIMING
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
60
45
80
65
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
2939 tbl 14b
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
6.42
12
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
TimingWaveformof WritewithPort-to-PortReadandBUSY (M/S =VIH)(2,4,5)
t
WC
MATCH
ADDR"A"
R/W"A"
t
WP
tDW
t
DH
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
t
BAA
t
BDA
tBDD
BUSY"B"
tWDD
VALID
DATAOUT "B"
(3)
tDDD
2939 drw 12
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
t
WH
R/W"B"
(2)
,
2939 drw 13
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the “SLAVE” version.
6.42
13
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(M/S = VIH)(1)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
t
APS
CE"B"
t
BAC
t
BDC
BUSY"B"
2939 drw 14
Waveform of BUSY Arbitration Cycle Controlled by
Address Match Timing(M/S = VIH)(1)
ADDR"A"
ADDR"B"
BUSY"B"
ADDRESS "N"
(2)
tAPS
MATCHING ADDRESS "N"
t
BAA
tBDA
2939 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
Truth Table III — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D15 Left
D0
- D15 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2939 tbl 15
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7026.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Control Truth Table.
6.42
14
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Width Expansion with BUSY Logic
Truth Table IV —
Address BUSY Arbitration
Master/SlaveArrays
WhenexpandinganIDT7026RAMarrayinwidthwhileusingBUSY
logic,onemasterpartisusedtodecidewhichsideoftheRAMarraywill
receiveaBUSYindication,andtooutputthatindication.Anynumberof
slavestobeaddressedinthesameaddressrangeasthemasterusethe
BUSYsignalasawriteinhibitsignal.ThusontheIDT7026RAMtheBUSY
pinisanoutputifthepartisusedasamaster(M/Spin=VIH),andtheBUSY
pin is an input if the part used as a slave (M/S pin = VIL) as shown in
Figure 3.
Inputs
Outputs
A
OL-A13L
(1)
(1)
A
OR-A13R
Function
Normal
CEL
CER
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
Normal
MATCH
H
H
Normal
MATCH
(2)
(2)
Write Inhibit(3)
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
2939 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a
master. Both are inputs when configured as a slave. BUSYX outputs on the
IDT7026 are push pull, not open drain outputs. On slaves the BUSYX input
internally inhibits writes.
2. LOW if the inputs to the opposite port were stable prior to the address and enable
inputs of this port. HIGH if the inputs to the opposite port became stable after the
address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR
= LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level
on the pin.
CE
CE
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
BUSY
R
BUSY
L
BUSY
R
BUSY
L
MASTER
Dual Port
RAM
CE
SLAVE
Dual Port
RAM
CE
BUSY
R
BUSY
L
BUSY
L
BUSYR
BUSY
R
BUSY
L
2939 drw 16
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7026 RAMs.
FunctionalDescription
TheIDT7026providestwoportswithseparatecontrol,addressand
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation
inmemory.TheIDT7026hasanautomaticpowerdownfeaturecontrolled
by CE. The CE controls on-chip power down circuitry that permits the
respectiveporttogointoastandbymodewhennotselected(CE =VIH).
Whenaportisenabled,accesstotheentirememoryarrayispermitted.
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
The BUSY arbitration on a master is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables.Failure
toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland
corrupteddataintheslave.
BusyLogic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.
The BUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
Semaphores
The IDT7026 is an extremely fast Dual-Port 16K x 16 CMOS Static
RAMwithanadditional8addresslocationsdedicatedtobinarysemaphore
flags.TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-
PortRAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefined
bythesystemdesigner’ssoftware.Asanexample,thesemaphorecan
beusedbyoneprocessortoinhibittheotherfromaccessingaportionof
the Dual-Port RAM or any other shared resource.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
and use any BUSY indication as an interrupt source to flag the event of
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
TheBUSYoutputsontheIDT7026RAMinmastermode,arepush-
pulltypeoutputsanddonotrequirepullupresistorstooperate. Ifthese
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
The Dual-Port RAM features a fast access time, and both ports are
completelyindependentofeachother.Thismeansthattheactivityonthe
leftportinnowayslowstheaccesstimeoftherightport. Bothportsare
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
6.42
15
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave one for both sides (unless a semaphore request from the other side is
anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM pending)andthencanbewrittentobybothsides.Thefactthattheside
enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites
on-chip power down circuitry that permits the respective port to go into fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
standbymodewhennotselected. Thisistheconditionwhichisshownin communications.(Athoroughdiscussionontheuseofthisfeaturefollows
Truth Table I where CE and SEM = VIH.
shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe
Systems which can best use the IDT7026 contain multiple proces- storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis
sors or controllers and are typically very high-speed systems which freedbythefirstside.
are software controlled or software intensive. These systems can
When a semaphore flag is read, its value is spread into all data bits
benefitfromaperformanceincreaseofferedbytheIDT7026'shardware so that a flag that is a one reads as a one in all data bits and a flag
semaphores, which provide a lockout mechanism without requiring containing a zero reads as all zeros. The read value is latched into one
complexprogramming.
side’soutputregisterwhenthatside'ssemaphoreselect(SEM)andoutput
Softwarehandshakingbetweenprocessorsoffersthemaximumin enable(OE)signalsgoactive.Thisservestodisallowthesemaphorefrom
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying changingstateinthemiddleofareadcycleduetoawritecyclefromthe
configurations.TheIDT7026doesnotuseitssemaphoreflagstocontrol otherside.Becauseofthislatch,arepeatedreadofasemaphoreinatest
anyresourcesthroughhardware,thusallowingthesystemdesignertotal loopmustcauseeithersignal(SEMorOE)togoinactiveortheoutputwill
flexibilityinsystemarchitecture.
never change.
AsequenceWRITE/READmustbeusedbythesemaphoreinorder
An advantage of using semaphores rather than the more common
methodsofhardwarearbitrationisthatwaitstatesareneverincurredin to guarantee that no system level contention will occur. A processor
either processor. This can prove to be a major advantage in very high- requestsaccesstosharedresourcesbyattemptingtowriteazerointoa
speedsystems.
semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore
requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,
afactwhichtheprocessorwillverifybythesubsequentread(seeTable
III).Asanexample,assumeaprocessorwritesazerototheleftportata
freesemaphorelocation.Onasubsequentread,theprocessorwillverify
thatithaswrittensuccessfullytothatlocationandwillassumecontrolover
the resource in question. Meanwhile, if a processor on the right side
attemptstowriteazerotothesamesemaphoreflagitwillfail, aswillbe
verifiedbythefactthataonewillbereadfromthatsemaphoreontheright
side during subsequent read. Had a sequence of READ/WRITE been
usedinstead,systemcontentionproblemscouldhaveoccurredduringthe
gap between the read and write cycles.
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation. The
reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch
havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
overtotheothersideassoonasaoneiswrittenintothefirstside’srequest
latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest
latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphorerequestlatch.
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
processorwantstousethisresource,itrequeststhetokenbysettingthe
latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
it. If it was successful, it proceeds to assume control over the shared
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe
sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest
that semaphore’s status or remove its request for that semaphore to
performanothertaskandoccasionallyattemptagaintogaincontrolofthe
tokenviathesetandtestsequence.Oncetherightsidehasrelinquished
thetoken,theleftsideshouldsucceedingainingcontrol.
ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting
azerointoasemaphorelatchandisreleasedwhenthesamesidewrites
aonetothatlatch.
The eight semaphore flags reside within the IDT7026 in a separate
memoryspacefromtheDual-PortRAM.This addressspaceisaccessed
byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe
semaphore flags) and using the other control pins (Address, OE, and
R/W)astheywouldbeusedinaccessingastandardStaticRAM. Each
oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside
throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof
theotheraddresspinshasanyeffect.
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
onthatsideandaoneontheotherside(seeTableIII).Thatsemaphore
can now only be modified by the side showing the zero. When a one is
writtenintothesamelocationfromthesameside,theflagwillbesettoa
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-
neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives
thetoken.Ifonesideisearlierthantheotherinmakingtherequest,thefirst
sidetomaketherequestwillreceivethetoken.Ifbothrequestsarriveat
thesametime,theassignmentwillbearbitrarilymadetooneportorthe
other.
One caution that should be noted when using semaphores is that
6.42
16
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
L PORT
R PORT
sectionbywriting,thenreadingazerointoSemaphore1.Ifitsucceeded
ingainingcontrol,itwouldlockouttheleftside.
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo
itssemaphorerequestandperformothertasksuntilitwasabletowrite,then
readazerointoSemaphore1.Iftherightprocessorperformsasimilartask
withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap
8K blocks of Dual-Port RAM with each other.
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
2939 drw 17
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual-
Port RAM or other shared resources into eight parts. Semaphores can
evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring
atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse
ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea
was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess
theirassignedportionsofmemorycontinuouslywithoutanywaitstates.
Semaphoresarealsousefulinapplicationswherenomemory“WAIT”
stateisavailableononeorbothsides.Onceasemaphorehandshakehas
been performed, both processors can access their assigned RAM
segmentsatfullspeed.
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor
mayberesponsibleforbuildingandupdatingadatastructure.Theother
processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting
processorreadsanincompletedatastructure,amajorerrorconditionmay
exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo
differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks
itandthenisabletogoinandupdatethedatastructure.Whentheupdate
is completed, the data structure block is released. This allows the
interpretingprocessortocomebackandreadthecompletedatastructure,
therebyguaranteeingaconsistentdatastructure.
Figure 4. IDT7026 Semaphore Logic
semaphoresalonedonotguaranteethataccesstoaresourceissecure.
Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused
or misinterpreted, a software error can easily happen.
Initializationofthesemaphoresisnotautomaticandmustbehandled
viatheinitializationprogramatpower-up.Sinceanysemaphorerequest
flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth
sidesshouldhaveaonewrittenintothematinitializationfrombothsides
to assure that they will be free when needed.
UsingSemaphores—SomeExamples
Perhapsthesimplestapplicationofsemaphoresistheirapplication
as resource markers for the IDT7026’s Dual-Port RAM. Say the 16K x
16 RAM was to be divided into two 8K x 16 blocks which were to be
dedicatedatanyonetimetoservicingeithertheleftorrightport.Semaphore
0couldbeusedtoindicatethesidewhichwouldcontrolthelowersection
of memory, and Semaphore 1 could be defined as the indicator for the
uppersectionofmemory.
Totakearesource, inthisexamplethelower8KofDual-PortRAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was
read back rather than a one), the left processor would assume control
of the lower 8K. Meanwhile the right processor was attempting to gain
controlofthe resourceaftertheleftprocessor,itwouldreadbackaone
inresponsetothezeroithadattemptedtowriteintoSemaphore0.Atthis
point,thesoftwarecouldchoosetotryandgaincontrolofthesecond8K
6.42
17
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I
B
Commercial (0°C to +70°C)
Industrial (-40°C to + 85°C)
Military (-55°C to +125°C)
Compliant to MIL-PRF-38535 QML
G
J
84-pin PGA (G84-3)
84-pin PLCC (J84-1)
Commercial Only
15
20
25
35
55
Commercial, Industrial & Military
Commercial, Industrial & Military
Commercial, Industrial & Military
Commercial, Industrial & Military
Speed
in nanoseconds
S
L
Standard Power
Low Power
,
7026
256K (16K x 16) Dual-Port RAM
2939 drw 18
DatasheetDocumentHistory
1/14/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Pages2and3Addedadditionalnotestopinconfigurations
Changeddrawingformat
6/3/99:
Page 1 Corrected DSC number
3/10/00:
AddedIndustrialTemperatureRangesandremovedrelatednotes
Replaced IDT logo
Page 1 FixedformatinFeatures
Changed±200mVto0mVinnotes
5/22/00:
Page 3 ClarifiedTA parameter
Page 6 DCElectricalparameters–changedwordingfrom"open"to"disabled"
11/20/01:
Page1&18 VerifiedaccuracyofIndustrialtempinformationthroughoutdatasheetandupdatedwithregisteredlogo
Page 2 & 3 Added date revision for pin configurations
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