IDT7027L25PF9 [IDT]
Dual-Port SRAM, 32KX16, 25ns, CMOS, PQFP100, TQFP-100;
| 型号： | IDT7027L25PF9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 32KX16, 25ns, CMOS, PQFP100, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED
32K x 16 DUAL-PORT
STATIC RAM
IDT7027S/L
Features
◆
◆
IDT7027 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
◆
◆
– Commercial:15/20/25/35/55ns (max.)
– Industrial: 20/25ns (max.)
Low-power operation
◆
◆
◆
◆
Busy and Interrupt Flags
On-chip port arbitration logic
– IDT7027S
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin
Ceramic PinGridArray(PGA)
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7027L
◆
◆
◆
Active: 750mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for bus
◆
◆
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
matching capability.
Dual chip enables allow for depth expansion without
◆
external logic
FunctionalBlockDiagram
R/W
L
R/
WR
UB
L
UB
R
CE0L
CE0R
CE1L
CE1R
OE
LB
R
OE
LB
L
L
R
I/O 8-15L
I/O8-15R
I/O0-7R
I/O
Control
I/O
Control
0-7L
I/O
(1,2)
R
BUSY
BUSY
L
.
32Kx16
14L
A
14R
0R
A
Address
Decoder
Address
Decoder
MEMORY
ARRAY
7027
A0L
A
A
14L
A
A
CE0R
14R
0R
A
CE0L
0L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE1L
OE
CE1R
OE
L
R
R/W
L
R/W
R
SEM
INT
L
L
SEM
R
(2)
(2)
INTR
M/S(2)
3199 drw 01
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
JULY 2004
1
DSC 3199/8
©2004 IntegratedDeviceTechnology,Inc.
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
circuitry of each port to enter a very low standby power mode.
FabricatedusingIDT’sCMOShigh-performancetechnology,these
devices typically operate on only 750mW of power. The IDT7027 is
packagedina100-pinThinQuadFlatpack(TQFP)anda108-pinceramic
Pin Grid Array (PGA).
Military grade product is manufactured in compliance with the
latest revision of MIL-PRF-38535 QML, making it ideally suited to
military temperature applications demanding the highest level of
performanceandreliability.
The IDT7027 is a high-speed 32K x 16 Dual-Port Static RAM,
designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combinationMASTER/SLAVEDual-PortRAMfor32-bit-or-moreword
systems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproachin32-
bitorwidermemorysystemapplicationsresultsinfull-speed,error-free
operationwithouttheneedforadditionaldiscretelogic.
The device provides two independent ports with separate control,
address,andI/Opinsthatpermit independent,asynchronousaccessfor
reads or writes to any location in memory. An automatic power down
featurecontrolledby thechipenables(CE0 andCE1)permitstheon-chip
PinConfigurations(1,2,3)
07/23/04
INDEX
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
A
9L
A
9R
75
74
73
72
71
A
A
A
A
A
10R
11R
12R
13R
14R
2
A10L
A11L
A12L
A13L
A14L
3
4
5
6
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
NC
NC
NC
7
8
9
LB
L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LBR
IDT7027PF
(4)
UB
L
UBR
PN100-1
CE0L
CE1L
CE0R
CE1R
SEM
GND
R/W
OER
100-Pin TQFP
(5)
SEM
L
R
Top View
Vcc
R/W
OE
L
L
R
GND
GND
GND
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
.
3199 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
07/23/04
81
A
80
A
77
74
72
69
68
65
63
60
57
54
UB
R
SEM
R
GND
10R
11R
A
14R
NC
GND
NC
I/O13R I/O10R NC
12
11
10
09
08
84
83
78
76
73
70
67
64
61
59
56
53
A
7R
4R
1R
A
8R
5R
3R
A
13R
NC
CE1R R/W
R
GND I/O14R I/O12R I/O9R
NC
LB
R
87
86
82
79
75
71
66
62
58
55
51
50
CE0R OE
R
A
A
A
9R
A
12R
NC
I/O15R I/O11R
NC
I/O8R I/O7R
90
88
85
52
49
47
A
A
A
6R
2R
NC
Vcc I/O5R
92
95
91
94
89
48
46
45
INT
R
A
0R
A
I/O6R I/O4R I/O3R
93
44
43
42
GND
BUSYR
I/O2R I/O1R I/O0R
M/S
07
06
IDT7027G
G108-1
(4)
96
BUSY
97
98
NC
39
I/O1L
40
41
L
INT
L
I/O0L GND
108-Pin PGA
(5)
Top View
99
100
A
102
35
I/O4L I/O2L GND
31 34 36
I/O5L I/O3L
37
38
A0L
1L
A
3L
05
04
03
02
101
103
106
A2L
A4L
A7L
Vcc
104
105
A
1
5
6
4
7
9
8
12
17
21
25
28
32
33
A5L
6L
A
10L
A
13L
NC
CE1L GND I/O14L I/O10L
NC
I/O7L I/O6L
107
2
10
13
16
19
22
24
29
30
I/O8L
UBL
SEML
A8L
A11L
A
14L
NC
OEL
GND I/O13L I/O11L NC
108
3
11
14
15
18 20 23 26
NC I/O15L I/O12L I/O9L
27
LB
L
CE0L
A9L
A12L
NC
C
Vcc R/W
L
NC
01
.
A
B
D
E
F
G
H
J
K
L
M
3199d r w 0 3
INDEX
Pin Names
Left Port
Right Port
Names
NOTES:
Chip Enables
Read/Write Enable
Output Enable
Address
CE0L, CE1L
CE0R, CE1R
R/W
OE
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.21 in x 1.21 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
R/WL
R
OEL
R
A0L - A14L
A0R - A14R
I/O0L - I/O15L
I/O0R - I/O15R
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
SEM
UB
LB
INT
BUSY
L
SEM
UB
LB
INT
BUSY
M/S
R
L
R
L
R
L
R
Busy Flag
L
R
Master or Slave Select
Power
V
CC
GND
Ground
3199 tbl 01
3
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I – Chip Enable
CE1
Mode
CE
CE0
VIL
VIH
Port Selected (TTL Active)
L
< 0.2V
>VCC - 0.2V
X
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
VIH
X
VIL
H
>VCC - 0.2V
X
X
<0.2V
3199 tbl 02
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only.
2. Port "A" and "B" references are located where CE is used.
3. "H" = VIH and "L" = VIL.
Truth Table II – Non-Contention Read/Write Control
Inputs(1)
Outputs
(2)
R/W
X
X
L
I/O8-15
I/O0-7
Mode
CE
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
High-Z
High-Z
High-Z Deselected: Power-Down
High-Z Both Bytes Deselected
X
L
L
L
L
L
L
X
H
H
DATAIN
High-Z
High-Z
DATAIN
DATAIN
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
L
H
L
H
L
L
H
DATAIN
DATAOUT
High-Z
H
H
H
X
L
H
L
H
High-Z Read Upper Byte Only
DATAOUT Read Lower Byte Only
DATAOUT Read Both Bytes
High-Z Outputs Disabled
L
H
L
H
L
L
H
DATAOUT
High-Z
H
X
X
X
3199 tbl 03
NOTES:
1. A0L — A14L ≠ A0R — A14R.
2. Refer to Chip Enable Truth Table.
Truth Table III – Semaphore Read/Write Control
Inputs(1)
Outputs
CE(2)
OE
L
UB
X
H
X
H
L
LB
X
H
X
H
X
L
SEM
L
R/W
H
I/O8-15
I/O0-7
Mode
H
DATAOUT
DATAOUT
DATAIN
DATAOUT Read Data in Semaphore Flag
DATAOUT Read Data in Semaphore Flag
X
H
L
L
H
X
X
X
X
L
DATAIN
Write I/O into Semaphore Flag
0
↑
X
L
L
DATAIN
DATAIN
Write I/O0 into Semaphore Flag
↑
______
______
X
L
Not Allowed
Not Allowed
______
______
L
X
X
L
3199 tbl 04
NOTES:
1. There are eight semaphore flags written to via I/O0 and read from all the I/Os (I/O0 __I/O15). These eight semaphore flags are addressed by A0-A2.
2. Refer to Chip Enable Truth Table.
4
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AbsoluteMaximumRatings(1,3)
MaximumOperating
TemperatureandSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Military
Unit
Ambient
(2)
Grade
Temperature
-55OC to+125OC
0OC to +70OC
-40OC to +85OC
GND
0V
Vcc
V
TERM
Te rminal Vo ltag e
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
Military
5.0V
+
+
+
10%
Commercial
Industrial
0V
5.0V
5.0V
10%
T
BIAS
Te mp e rature
Under Bias
-55 to +125
-65 to +150
50
-65 to +135
-65 to +150
50
oC
oC
0V
10%
Storage
Te mp e rature
TSTG
3199 tbl 06
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
DC Output
Current
mA
IOUT
3199 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Capacitance(1)
(TA = +25°C, f = 1.0mhz) TQFP ONLY
Symbol
Parameter
Conditions
Max. Unit
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
C
IN
Input Capacitance
V
IN = 0V
9
pF
(2)
OUT
Output
Capacitance
C
VOUT = 0V
10
pF
3199 tbl 08
RecommendedDCOperating
Conditions
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
Symbol
Parameter
Supply Voltage
GND Ground
Min.
Typ. Max. Unit
2. COUT also references CI/O.
VCC
4.5
5.0
5.5
0
V
V
V
0
0
(2)
____
V
IH
Input High Voltage
Input Low Voltage
2.2
6.0
0.8
-0.5(1)
V
____
VIL
3199 tbl 07
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7027S
7027L
Symbol
|ILI
|ILO
Parameter
Test Conditions
Min.
Max.
10
Min.
Max.
5
Unit
µA
µA
V
(1)
___
___
|
Input Leakage Current
V
CC = 5.5V, VIN = 0V to VCC
___
___
___
___
|
Output Leakage Current
Output Low Voltage
Output High Voltage
10
5
CE = VIH, VOUT = 0V to VCC
VOL
IOL = 4mA
0.4
0.4
___
___
VOH
IOH = -4mA
2.4
2.4
V
3199 tbl 09
NOTE:
1. At Vcc < 2.0V, input leakages are undefined.
5
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6) (VCC = 5.0V ± 10%)
7027X15
7027X20
Com'l
7027X25
Com'l
Com'l Only
& Ind
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating
S
L
205
200
365
325
190
180
325
285
180
170
305
265
mA
CE = VIL, Outputs Disabled
SEM = VIH
Current
(3)
(Both Ports Active)
f = fMAX
___
___
___
___
___
___
IND
S
L
170
345
___
___
180
335
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
COM'L
IND
S
L
65
65
110
90
50
50
90
70
40
40
85
60
mA
mA
CE
SEM
f = fMAX
L
= CE
R
= VIH
= VIH
R
= SEM
L
(3)
___
___
___
___
___
___
S
L
40
100
___
___
50
85
(5)
ISB2
Standby Current
(One Port - TTL Level
Inputs)
COM'L
IND
S
L
130
130
245
215
115
115
215
185
105
105
200
170
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
___
___
___
___
___
___
S
L
105
230
SEMR = SEML = VIH
___
___
115
220
I
SB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CE
CE > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(4)
SEM = SEM > VCC - 0.2V
L
and
COM'L
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
mA
mA
R
V
V
___
___
___
___
___
___
S
L
1.0
30
___
___
0.2
10
R
L
ISB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
COM'L
IND
S
L
120
120
220
190
110
110
190
160
100
100
170
145
CE"A" < 0.2V and
(5)
CE"B" > VCC - 0.2V
SEM = SEM > VCC - 0.2V
R
L
___
___
___
___
___
___
S
L
100
200
V
IN > VCC - 0.2V or VIN < 0.2V
___
___
110
195
Active Port Outputs Disabled
(3)
f = fMAX
3199 tbl 10a
7027X35
Com'l Only
7027X55
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating Current
(Both Ports Active)
S
160
160
295
255
150
150
270
230
mA
CE = VIL, Outputs Disabled
L
SEM = VIH
(3)
f = fMAX
___
___
___
___
___
___
___
___
IND
S
L
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
COM'L
IND
S
L
30
30
85
60
20
20
85
60
mA
mA
CE
L
SEM
= CE
R
= VIH
= VIH
R
= SEM
L
___
___
___
___
___
___
___
___
S
L
(5 )
ISB2
Standby Current
(One Port - TTL Level
Inputs)
COM'L
IND
S
L
95
95
185
155
85
85
165
135
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
SEMR = SEML = VIH
___
___
___
___
___
___
___
___
S
L
I
SB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CE
CE > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(4 )
SEM = SEM > VCC - 0.2V
L
and
mA
mA
COM'L
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
R
V
V
___
___
___
___
___
___
___
___
S
L
R
L
ISB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
COM'L
IND
S
L
90
90
160
135
80
80
135
110
CE"A" < 0.2V and
(5 )
CE"B" > VCC - 0.2V
SEM = SEM > VCC - 0.2V
R
L
___
___
___
___
___
___
___
___
S
L
V
IN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
(3)
f = fMAX
3199 tbl 10b
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
6
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
dInput Pulse Levels
GND to 3.0V
5ns Max.
1.5V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
Figures 1 and 2
3199 tbl 11
5V
5V
893Ω
893Ω
DATAOUT
BUSY
INT
DATAOUT
30pF
5pF*
347Ω
347Ω
3199 drw 04
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
Figure 1. AC Output Test Load
*Including scope and jig.
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRanges(4)
7027X15
7027X20
Com'l
7027X25
Com'l
7027X35
Com'l Only
7027X55
Com'l Only
Com'l Only
& Ind
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
15
20
25
35
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
t
Address Access Time
15
15
20
20
25
25
35
35
55
55
Chip Enable Access Time(4)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
____
____
____
____
____
____
t
t
10
12
13
20
30
____
____
____
____
____
t
3
3
3
3
3
____
____
____
____
____
t
3
3
3
3
3
Output High-Z Time(1,2)
10
12
15
15
25
____
____
____
____
____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
0
0
0
0
0
____
____
____
____
____
____
____
____
____
____
t
15
20
25
35
50
____
____
____
____
____
t
10
10
12
15
15
____
____
____
____
____
t
15
20
25
35
55
ns
3199 tbl 12
NOTES:.
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
5. Refer to Chip Enable Truth Table.
7
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE(6)
OE
(4)
tAOE
(4)
tABE
UB, LB
R/W
DATAOUT
BUSYOUT
t
OH
(1)
tLZ
VALID DATA(4)
(2)
tHZ
(3,4)
3199 drw 05
tBDD
Timing of Power-Up Power-Down
CE(6)
tPU
tPD
ICC
50%
50%
ISB
.
3199 drw 06
NOTES:
1. Timing depends on which signal is asserted last, CE, OE, LB, or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer to Chip Enable Truth Table.
8
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
7027X15
7027X20
Com'l
7027X25
Com'l
& Ind
7027X35
Com'l Only
7027X55
Com'l Only
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
15
12
12
0
20
15
15
0
25
20
20
0
35
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
12
0
15
0
20
0
25
0
40
0
t
Write Recovery Time
t
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(5)
10
15
15
15
30
____
____
____
____
____
t
10
12
15
15
25
____
____
____
____
____
t
0
0
0
0
0
(1,2)
____
____
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,5)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
12
15
15
25
____
____
____
____
____
t
0
5
5
0
5
5
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
____
____
____
____
t
t
ns
3199 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. Refer to Chip Enable
Truth Table.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
9
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
t
AW
CE or SEM (9,10)
UB or LB(9)
R/W
(3)
(2)
(6)
t
WR
tAS
tWP
(7)
tOW
tWZ
(4)
(4)
DATAOUT
DATAIN
tDW
tDH
3199 drw 07
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
t
WC
ADDRESS
t
AW
CE or SEM(9,10)
UB or LB(9)
(6)
AS
(3)
(2)
t
WR
tEW
t
R/W
t
DW
tDH
DATAIN
3199 drw 08
NOTES:
1. R/W or CE or UB and LB = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Chip Enable Truth Table.
10
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
t
OH
tSAA
VALID ADDRESS
VALID ADDRESS
A0-A2
tWR
tACE
tAW
t
EW
SEM
tSOP
t
DW
DATAIN
VALID
DATAOUT
VALID(2)
I/O0
tAS
tWP
tDH
R/W
t
SWRD
tAOE
OE
Write Cycle
Read Cycle
3199 drw 09
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table.
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2)
"A"
R/W"A"
SEM"A"
t
SPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
3199 drw 10
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH (refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
11
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating TemperatureandSupplyVoltageRange(6)
7027X15
7027X20
Com'l
7027X25
Com'l
7027X35
Com'l Only
7027X55
Com'l Only
Com'l Only
& Ind
& Ind
Symbol
BUSY TIMING (M/S=VIH
Parameter
Min. Max. Min.
Max.
Min.
Max.
Min.
Max. Min.
Max. Unit
)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
20
20
20
20
20
20
20
20
20
45
40
40
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
t
15
17
17
20
35
____
____
____
____
____
t
5
5
5
5
5
____
____
____
____
____
BUSY Disable to Valid Data(3)
t
15
20
25
35
55
(5)
____
____
____
____
____
t
Write Hold After BUSY
12
15
17
25
25
BUSY TIMING (M/S=VIL
)
____
____
____
____
____
____
____
____
____
____
BUSY Input to Write(4)
t
WB
0
0
0
0
0
ns
ns
(5)
t
WH
Write Hold After BUSY
PORT-TO-PORT DELAY TIMING
Write Pulse to Data Delay
Write Data Valid to Read Data Delay(1)
12
15
17
25
25
(1)
____
____
____
____
____
____
____
____
____
____
tWDD
30
25
45
30
50
35
60
45
80
65
ns
tDDD
ns
3199 tbl 14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
12
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
TimingWaveformof WritewithPort-to-PortReadandBUSY (M/S =VIH)(2,4,5)
t
WC
MATCH
ADDR"A"
R/W"A"
t
WP
tDW
t
DH
VALID
DATAIN "A"
(1)
t
APS
MATCH
ADDR"B"
t
BAA
t
BDA
tBDD
BUSY"B"
tWDD
VALID
DATAOUT "B"
(3)
t
DDD
3199 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL (refer to Chip Enable Truth Table).
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
t
WP
R/W"A"
(3)
t
WB
BUSY"B"
(1)
tWH
.
(2)
R/W"B"
3199 drw 12
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the "Slave" version.
13
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(M/S = VIH)(1,3)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
(2)
tAPS
CE"B"
tBAC
tBDC
BUSY"B"
3199 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(M/S = VIH)(1)
ADDR"A"
ADDRESS "N"
(2)
tAPS
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
3199 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Chip Enable Truth Table.
AC Electrical Characteristics Over the
Operating TemperatureandSupplyVoltageRange(1)
7027X15
7027X20
Com'l
7027X25
Com'l
7027X35
Com'l Only
7027X55
Com'l Only
Com'l Only
& Ind
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
0
0
0
0
0
ns
ns
ns
t
Write Recovery Time
Interrupt Set Time
0
0
0
0
0
____
____
____
____
____
t
15
15
20
20
20
20
25
25
40
40
____
____
____
____
____
t
Interrupt Reset Time
ns
3199 tbl 15
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
14
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1,5)
t
WC
INTERRUPT SET ADDRESS (2)
ADDR"A"
(4)
(3)
t
AS
tWR
CE"A"
R/W"A"
INT"B"
(3)
t
INS
3199 drw 15
t
RC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
t
AS
OE"B"
(3)
INR
t
INT"B"
NOTES:
3199 drw 16
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See the Interrupt Truth Table IV.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Chip Enable Truth Table.
Truth Table IV — Interrupt Flag(1,4)
Left Port
Right Port
OE
R/WL
A14L-A0L
R/WR
A
14R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CEL
OEL
INTL
CER
R
INTR
(2)
L
L
X
X
L
X
X
X
L
7FFF
X
X
X
X
L
X
L
L
X
X
L
X
7FFF
7FFE
X
L
R
(3)
X
X
H
R
(3)
X
X
L
X
X
X
L
(2)
X
7FFE
H
X
X
L
3199 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. Refer to Chip Enable Truth Table.
15
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table V —
Address Bus Arbitration(4)
Inputs
Outputs
A
OL-A14L
(1)
(1)
A
OR-A14R
Function
Normal
Normal
Normal
Write
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
X
X
H
NO MATCH
MATCH
H
H
H
H
H
H
MATCH
L
L
MATCH
(2)
(2)
(3)
Inhibit
3199 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7027 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of the actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of the actual logic level on the pin.
4. Refer to Chip Enable Truth Table.
Truth Table VI — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D15 Left
D0
- D15 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
3199 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7027.
2. There are eight semaphore flags written to via I/O0 and read from all the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL, to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
FunctionalDescription
TheIDT7027providestwoportswithseparatecontrol,addressand
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation
inmemory.TheIDT7027hasanautomaticpowerdownfeaturecontrolled
by CE0 and CE1. The CE0 and CE1 control the on-chip power down
circuitrythatpermitstherespectiveporttogointoastandbymodewhen
not selected (CE = VIH). When a port is enabled, access to the entire
memoryarrayispermitted.
(INTL) is asserted when the right port writes to memory location 7FFE
(HEX), where a write is defined as CER = R/WR = VIL per Truth Table
IV. The leftportclears the interruptthroughaccess ofaddress location
7FFEwhenCEL=OEL=VIL,R/Wisa"don'tcare".Likewise,therightport
interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation
7FFF(HEX)andtocleartheinterruptflag(INTR),therightportmustread
the memory location 7FFF. The message (16 bits) at 7FFE or 7FFF is
user-defined since it is an addressable SRAM location. If the interrupt
functionisnotused,addresslocations7FFEand7FFFarenotusedas
mail-boxes by ignoring the interrupt, but as part of the random access
memory.RefertoTruthTableIVfortheinterruptoperation.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessagecenter)is assignedtoeachport. Theleftportinterruptflag
16
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables.Failure
toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland
corrupteddataintheslave.
BusyLogic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
Semaphores
TheIDT7027isafastDual-Port32Kx16CMOSStaticRAMwithan
additional8addresslocationsdedicatedtobinarysemaphoreflags.These
flagsalloweitherprocessorontheleftorrightsideoftheDual-PortSRAM
toclaimaprivilegeovertheotherprocessorforfunctionsdefinedbythe
systemdesigner’ssoftware.Asanexample,thesemaphorecanbeused
byoneprocessortoinhibittheotherfromaccessingaportionoftheDual-
Port SRAM or any other shared resource.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
anduse anyBUSYindicationas aninterruptsource toflagthe eventof
anillegalorillogicaloperation.Ifthewriteinhibitfunctionofbusylogicisnot
desirable,theBUSYlogiccanbedisabledbyplacingthepartinslavemode
withtheM/Spin.OnceinslavemodetheBUSYpinoperatessolelyasa
writeinhibitinputpin.Normaloperationcanbeprogrammedbytyingthe
BUSY pins HIGH. If desired, unintended write operations can be pre-
ventedtoa portbytyingthe BUSYpinforthatportLOW.
TheBUSYoutputsontheIDT7027RAMinmastermode,arepush-
pulltypeoutputsanddonotrequirepullupresistorstooperate.Ifthese
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
TheDual-PortSRAMfeaturesafastaccesstime,andbothportsare
completelyindependentofeachother.Thismeansthattheactivityonthe
leftportinnowayslows theaccess timeoftherightport.Bothports are
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
in the non-semaphore portion of the Dual-Port SRAM. These devices
haveanautomaticpower-downfeaturecontrolledbyCE theDual-Port
SRAMenable,andSEM,thesemaphoreenable.TheCEandSEMpins
controlon-chippowerdowncircuitrythatpermitstherespectiveporttogo
intostandbymodewhennotselected. Thisistheconditionwhichisshown
in Truth Table II where CE and SEM = VIH.
A15
CE0
CE0
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSY
R
BUSY
R
BUSY
L
BUSYL
SystemswhichcanbestusetheIDT7027containmultipleprocessors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit
from a performance increase offered by the IDT7027's hardware
semaphores, which provide a lockout mechanism without requiring
complexprogramming.
CE
1
CE1
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSY
R
BUSY
R
BUSY
R
BUSY
L
BUSYL
BUSY
L
3199 drw 17
Softwarehandshakingbetweenprocessors offers themaximumin
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations.TheIDT7027doesnotuseitssemaphoreflagstocontrol
anyresourcesthroughhardware,thusallowingthesystemdesignertotal
flexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methodsofhardwarearbitrationisthatwaitstatesareneverincurredin
either processor. This can prove to be a major advantage in very high-
speedsystems.
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7027 RAMs.
Width Expansion with Busy Logic
Master/SlaveArrays
WhenexpandinganIDT7027RAMarrayinwidthwhileusingBUSY
logic, one master part is used to decide which side of the RAM array
willreceiveaBUSYindication,andtooutputthatindication.Anynumber
ofslavestobeaddressedinthesameaddressrangeasthemaster,use
theBUSYsignalasawriteinhibitsignal.ThusontheIDT7027RAMthe
BUSYpinisanoutputifthepartisusedasaMaster(M/Spin=VIH),and
theBUSYpinisaninputifthepartusedasaSlave(M/Spin=VIL)asshown
in Figure 3.
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortSRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
processorwantstousethisresource,itrequeststhetokenbysettingthe
latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
it. If it was successful, it proceeds to assume control over the shared
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe
sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest
that semaphore’s status or remove its request for that semaphore to
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. Itignores whetheranaccess is a readorwrite. In
a master/slave array, bothaddress andchipenable mustbe validlong
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
17
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
performanothertaskandoccasionallyattemptagaintogaincontrolofthe side during subsequent read. Had a sequence of READ/WRITE been
tokenviathesetandtestsequence.Oncetherightsidehasrelinquished usedinstead,systemcontentionproblemscouldhaveoccurredduringthe
thetoken,theleftsideshouldsucceedingainingcontrol.
gap between the read and write cycles.
Thesemaphoreflagsareactivelow.Atokenisrequestedbywriting
It isimportanttonotethatafailedsemaphorerequestmustbefollowed
azerointoasemaphorelatchandisreleasedwhenthesamesidewrites byeitherrepeatedreadsorbywritingaoneintothesamelocation.The
aonetothatlatch. reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
The eightsemaphore flags reside withinthe IDT7027ina separate ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
memoryspacefromtheDual-PortSRAM.Thisaddressspaceisaccessed into a semaphore flag. Whichever latch is first to present a zero to the
byplacingalowinputontheSEMpin(whichactsasachipselectforthe
semaphore flags) and using the other control pins (Address, OE, and
L PORT
R PORT
R/W)as theywouldbeusedinaccessingastandardStaticRAM.Each
oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside
throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof
theotheraddresspinshasanyeffect.
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
on that side and a one on the other side (see Truth Table VI). That
semaphorecannowonlybemodifiedbythesideshowingthezero.When
aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
settoaoneforbothsides(unlessasemaphorerequestfromtheotherside
ispending)andthencanbewrittentobybothsides.Thefactthattheside
whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites
fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
communications.(Athoroughdiscussionontheuseofthisfeaturefollows
shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe
storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis
freedbythefirstside.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
signalsgoactive.Thisservestodisallowthesemaphorefromchanging
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
cause either signal (SEM or OE) to go inactive or the output will never
change.
AsequenceWRITE/READmustbeusedbythesemaphoreinorder
to guarantee that no system level contention will occur. A processor
requestsaccesstosharedresourcesbyattemptingtowriteazerointoa
semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore
requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,
afactwhichtheprocessorwillverifybythesubsequentread(seeTruth
TableVI).Asanexample,assumeaprocessorwritesazerototheleftport
atafreesemaphorelocation.Onasubsequentread,theprocessorwill
verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol
overtheresourceinquestion.Meanwhile,ifaprocessorontherightside
attempts towriteazerotothesamesemaphoreflagitwillfail,as willbe
verifiedbythefactthataonewillbereadfromthatsemaphoreontheright
SEMAPHORE
READ
SEMAPHORE
READ
.
3199 drw 18
Figure 4. IDT7027 Semaphore Logic
semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch
havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
overtotheothersideassoonasaoneiswrittenintothefirstside’srequest
latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest
latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
is requestedandthe processorwhichrequesteditnolongerneeds the
resource, the entire system can hang up until a one is written into that
semaphorerequestlatch.
The criticalcase ofsemaphore timingis whenbothsides requesta
single token by attempting to write a zero into it at the same time. The
semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-
neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives
thetoken.Ifonesideis earlierthantheotherinmakingtherequest,the
first side to make the request will receive the token. If both requests
arriveatthesametime,theassignmentwillbearbitrarilymadetooneport
or the other.
One caution that should be noted when using semaphores is that
semaphoresalonedonotguaranteethataccesstoaresourceissecure.
Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused
ormisinterpreted, a software errorcaneasilyhappen.
Initializationofthesemaphoresisnotautomaticandmustbehandled
viatheinitializationprogramatpower-up.Sinceanysemaphorerequest
flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth
sidesshouldhaveaonewrittenintothematinitializationfrombothsides
to assure that they will be free when needed.
18
6.42
IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I(1)
B
Commercial (0°C to +70°C)
Industrial (-40°C to + 85°C)
Military (-55°C to +125°C)
Compliant to MIL-PRF-38535 QML
PF
G
100-pin TQFP (PN100-1)
108-pin PGA (G108-1)
15
20
25
35
55
Commercial Only
Commercial & Industrial
Commercial & Industrial
Commercial Only
Commercial Only
Speed in nanoseconds
.
S
L
Standard Power
Low Power
7027
512K (32K x 16) Dual-Port RAM
3199 drw 19
NOTE:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
DatasheetDocumentHistory
1/15/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Pages2and3Addedadditionalnotestopinconfigurations
Pages 4 and 16 Fixed typographical errors
Changeddrawingformat
5/19/99:
6/3/99:
Page 1 CorrectedDSCnumber
Replaced IDT logo
Page 5 Increasedstoragetemperatureparameter
ClarifiedTAparameter
11/10/99:
5/22/00:
Page 6 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed±200mVto0mVinnotes
7/23/04
Page 2 & 3 Added date revision for pin configurations
Page 5 UpdatedCapacitancetable
Page 6 Added15nscommercialspeedgradetotheDCElectricalCharacteristics
Added 20nsIndustrialtempforlowpower toDCElectricalCharacteristics
Removedmilitarytemprangefor25/35/55nsfromDCElectricalCharacteristics
Page 7, 9, 12&14 Added15ns commercialspeedgrade toACElectricalCharacteristics
Added20nsIndustrialtempforlowpowertoACElectricalCharacteristicsforRead,Write,BusyandInterrupt
Removedmilitarytemprangefor25/35/55nsfromACElectricalCharacteristics
Page 19 AddedCommercialspeedgradefor15nsandIndustrialtempto20nsinorderinginformation
Page 1 & 19 Replaced old TM logo with new TM logo
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19
6.42
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