IDT7035L20PF9 [IDT]
Dual-Port SRAM, 8KX8, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100;
| 型号： | IDT7035L20PF9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 8KX8, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 静态存储器 |
| 文件： | 总19页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED
8K x 18 DUAL-PORT
STATIC RAM
IDT7035S/L
Features
◆
True Dual-Ported memory cells which allow simultaneous
using the Master/Slave select when cascading more than
one device
M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
reads of the same memory location
High-speed access
◆
◆
– Commercial:15/20ns (max.)
– Industrial:20ns (max.)
Low-power operation
◆
◆
◆
◆
– IDT7035S
Full on-chip hardware support of semaphore signaling
between ports
Active:800mW(typ.)
Standby: 5mW (typ.)
– IDT7035L
◆
◆
◆
◆
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 100-pin Thin Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Active:800mW(typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multiplexed
◆
bus compatibility
IDT7035 easily expands data bus width to 36 bits or more
◆
FunctionalBlockDiagram
R/WL
R/
W
R
R
UBL
UB
LB
CE
OE
L
L
L
LB
CE
OE
R
R
R
I/O9L-I/O17L
I/O0L-I/O8L
I/O9R-I/O17R
I/O
Control
I/O
Control
I/O0R-I/O8R
(1,2)
L
(1,2)
R
BUSY
BUSY
A
12L
A
12R
0R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
0L
A
13
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
L
L
CE
OE
R/
R
R
R/WL
W
R
SEM
R
SEM
INTL
L
(2)
(2)
INTR
M/S
4088 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
AUGUST 2001
1
DSC 4088/8
©2001IntegratedDeviceTechnology,Inc.
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
port to enter a very low standby power mode.
The IDT7035 is a high-speed 8K x 18 Dual-Port Static RAM. The
IDT7035isdesignedtobeusedasastand-alone144K-bitDual-PortRAM
orasacombinationMASTER/SLAVEDual-PortRAMfor36-bitormore
wordsystems. UsingtheIDTMASTER/SLAVEDual-PortRAMapproach
in36-bitorwidermemorysystemapplicationsresultsinfull-speed,error-
freeoperationwithouttheneedforadditionaldiscretelogic.
TheIDT7035utilizes a18-bitwidedatapathtoalowforparityatthe
user's option. This feature is especiallyusefulindata communications
applications where it is necessary to use a parity bit for transmission/
receptionerrorchecking.
FabricatedusingIDT’sCMOShigh-performancetechnology,these
devices typically operate on only 800mW of power. Low-power (L)
versionsofferbatterybackupdataretentioncapabilitywithtypical power
consumptionof500µWfroma2Vbattery.
This device provides two independent ports with separate control,
address,andI/Opinsthatpermitindependent, asynchronousaccessfor
reads or writes to any location in memory. An automatic power down
featurecontrolledbyChipEnable(CE)permitstheon-chipcircuitryofeach
PinConfigurations(1,2,3)
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
N/C
N/C
I/O8L
I/O17L
I/O11L
I/O12L
I/O13L
I/O14L
GND
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N/C
N/C
N/C
N/C
2
3
4
5
A5L
A4L
A3L
A2L
A1L
A0L
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O15L
I/O16L
IDT7035PF
PN100-1
INTL
(4)
VCC
BUSY
GND
M/S
L
GND
I/O0R
I/O1R
I/O2R
100-Pin TQFP
(5)
Top View
BUSY
R
INTR
VCC
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
I/O8R
I/O17R
N/C
1R
2R
3R
4R
N/C
N/C
N/C
N/C
N/C
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
4088 drw 02
.
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
Names
Chip Enable
CE
R/W
OE
L
CE
R/W
OE
R
L
R
Read/Write Enable
Output Enable
Address
L
R
A0L - A12L
A0R - A12R
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
SEM
UB
LB
INT
BUSY
L
SEM
UB
LB
INT
BUSY
M/S
R
L
R
L
R
L
R
Busy Flag
L
R
Master or Slave Select
Power
V
CC
GND
Ground
4088 tbl 01
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
R/W
X
X
L
I/O9-17
High-Z
High-Z
DATAIN
High-Z
DATAIN
I/O0-8
High-Z
High-Z
High-Z
DATAIN
DATAIN
High-Z
DATAOUT
DATAOUT
High-Z
Mode
Deselected: Power-Down
CE
H
X
L
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
H
L
L
H
L
H
L
L
L
H
L
H
H
H
X
L
H
L
H
DATAOUT
High-Z
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
L
L
H
L
H
L
L
L
H
DATAOUT
High-Z
X
H
X
X
X
Outputs Disabled
4088 tbl 02
NOTE:
1. A0L — A12L ≠ A0R — A12R
3
6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
R/W
H
I/O9-17
I/O0-8
Mode
Read Data in Semaphore Flag
Read Data in Semaphore Flag
CE
H
OE
L
UB
X
LB
X
SEM
L
DATAOUT
DATAOUT
DATAOUT
DATAOUT
X
H
L
H
H
L
H
↑
X
X
X
L
DATAIN
DATAIN
Write I/O into Semaphore Flag
0
X
L
L
↑
X
X
X
X
X
H
L
H
X
L
L
L
L
DATAIN
DATAIN
Write I/O0 into Semaphore Flag
______
______
Not Allowed
Not Allowed
______
______
X
4088 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O17. These eight semaphores are addressed by A0 - A2.
AbsoluteMaximumRatings(1)
MaximumOperating
TemperatureandSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Unit
Ambient
(2)
Grade
Commercial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
Vcc
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
5.0V
5.0V
+
+
10%
Industrial
0V
10%
Te mp e rature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
T
BIAS
4088 tbl 05
NOTES:
Storage
Te mp e rature
TSTG
1. This is the parameter TA. This is the "instant on" case temperature.
DC Output
Current
mA
IOUT
4088 tbl 04
NOTES:
RecommendedDCOperating
Conditions
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Symbol
Parameter
Supply Voltage
GND Ground
Min.
Typ. Max. Unit
VCC
4.5
5.0
5.5
0
V
V
V
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20 mA for the period over VTERM > Vcc + 10%.
0
0
V
IH
IL
NOTES:
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
-0.5(1)
V
____
V
4088 tbl 06
Capacitance(TA = +25°C, f = 1.0MHz) (1)
Symbol
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
Parameter
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
CIN
Input Capacitance
V
9
pF
pF
Output
Capacitance
V
10
COUT
4088 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested. For TQFP Package Only.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
6.42
4
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
7035S
7035L
Symbol
Parameter
Test Conditions
Min.
Max.
10
Min.
Max.
5
Unit
µA
µA
V
(1)
___
___
|ILI|
Input Leakage Current
Output Leakage Current
Output Low Voltage
V
CC = 5.5V, VIN = 0V to VCC
___
___
___
___
|ILO
|
10
5
CE = VIH, VOUT = 0V to VCC
VOL
I
OL = 4mA
0.4
0.4
___
___
VOH
Output High Voltage
IOH = -4mA
2.4
2.4
V
4088 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)
7035X15
Com'l Only
Typ.(2) Max.
7035X20
Com'l & Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2) Max.
Unit
ICC
Dynamic Operating Current
(Both Ports Active)
S
L
170
170
310
260
160
160
290
240
mA
CE = VIL, Outputs Disabled
SEM = VIH
(3)
f = fMAX
____
____
____
____
IND
S
L
160
160
370
320
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
COM'L
IND
S
L
20
20
60
50
20
20
60
50
mA
mA
CE
L
SEM
= CE
R
= VIH
= VIH
R
= SEM
L
(3)
f = fMAX
____
____
____
____
S
L
20
20
90
70
(5)
ISB2
Standby Current
(One Port - TTL Level Inputs)
COM'L
S
L
105
105
190
160
95
95
180
150
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
SEM
R
= SEML = VIH
____
____
____
____
IND
S
L
95
95
240
210
I
SB3
Full Standby Current (Both
Ports - All CMOS Level
Inputs)
Both Ports CE
CE > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(4)
SEM = SEM > VCC - 0.2V
L
and
S
L
1.0
0.2
1.0
0.2
15
5
mA
mA
COM'L
IND
15
5
R
V
V
____
____
____
____
S
L
1.0
0.2
30
10
R
L
ISB4
Full Standby Current
(One Port - All CMOS Level
Inputs)
COM'L
IND
S
L
100
100
170
140
90
90
155
130
CE"A" < 0.2V and
(5)
CE"B" > VCC - 0.2V
SEM = SEM > VCC - 0.2V
IN > VCC - 0.2V or VIN < 0.2V
R
L
____
____
____
____
S
L
90
90
225
200
V
Active Port Outputs Disabled
(3)
f = fMAX
4088 tbl 09
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. VCC = 5V, TA = +25°C, and are not production tested. Icc dc = 120mA (TYP)
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5
6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Data retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)(4)
Symbol
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
V
___
___
V
DR
VCC for Data Retention
VCC = 2V
2.0
___
ICCDR
Data Retention Current
µA
CE > VHC
IN > VHC or < VLC
IND.
100
4000
___
V
COM'L.
100
1500
(3)
CDR
___
___
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
SEM > VHC
(3)
(2)
___
___
t
R
t
RC
ns
4088 tbl 10
NOTES:
1. TA = +25°C, VCC = 2V, not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by characterization, but is not production tested.
4. At Vcc < 2.0V input leakages are undefined.
Data Retention Waveform
DATA RETENTION MODE
VDR
≥
4.5V
4.5V
2V
VCC
tCDR
tR
VDR
VIH
VIH
CE
4088 drw 03
AC Test Conditions
Input Pulse Levels
5V
5V
GND to 3.0V
5ns Max.
1.5V
893Ω
893Ω
Input Rise/Fall Times
DATAOUT
BUSY
INT
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAOUT
1.5V
5pF*
347Ω
30pF
347Ω
Figures 1 and 2
4088 tbl 11
4088 drw 04
Figure 1. AC Output Test Load
Figure 2. Output Test Load
( for tLZ, tHZ, tWZ, tOW)
* including scope and jig.
6.42
6
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
7035X15
Com'l Only
7035X20
Com'l & Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
Address Access Time
15
15
15
20
20
20
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
____
____
t
t
t
10
12
____
____
t
3
3
____
____
t
3
3
Output High-Z Time(1,2)
10
12
____
____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
0
0
____
____
____
____
t
15
20
(3)
____
____
t
Semaphore Flag Update Pulse (OE or SEM)
10
10
Semaphore Address Access Time(3)
15
20
ns
____
____
t
4088 tbl 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
Waveform of Read Cycles(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
tAOE
(4)
tABE
UB, LB
R/W
(1)
tOH
tLZ
VALID DATA(4)
DATAOUT
BUSYOUT
(2)
tHZ
(3,4)
4088 drw 05
tBDD
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY has
no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
7
6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing of Power-Up Power-Down
CE
tPU
tPD
I
CC
SB
50%
50%
I
.
4088 drw 06
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
7035X15
Com'l Only
7035X20
Com'l & Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
15
12
12
0
20
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
12
0
15
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
10
15
____
____
t
10
12
____
____
t
0
0
Write Enable to Output in High-Z (1,2)
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
10
12
____
____
t
____
____
t
0
5
5
0
5
5
____
____
____
____
t
t
ns
SEM Flag Contention Window
4088 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the
entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
6.42
8
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
t
WC
ADDRESS
(7)
tHZ
OE
tAW
CE or SEM(9)
UB or LB(9)
R/W
(3)
WR
(2)
tWP
(6)
t
tAS
(7)
tWZ
tOW
(4)
(4)
DATAOUT
DATAIN
tDW
tDH
4088 drw 07
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
t
WC
ADDRESS
CE or SEM(9)
UB or LB(9)
R/W
tAW
(3)
(2)
(6)
t
WR
t
AS
tEW
t
DW
tDH
DATAIN
4088 drw 08
NOTES:
1. R/W or CE or UB & LB must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W, or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. tEW must be met
for either condition.
9
6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
t
OH
t
SAA
A0 - A2
VALID ADDRESS
VALID ADDRESS
t
AW
t
WR
t
ACE
t
t
EW
SEM
t
SOP
t
DW
OUT
DATA
DATA
0
VALID(2)
DATAIN VALID
t
AS
WP
tDH
R/W
t
SWRD
t
AOE
OE
t
SOP
Read Cycle
Write Cycle
4088 drw 09
NOTE:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID' represents all I/Os (I/O0-I/O17) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2)
"A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
4088 drw 10
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
6.42
10
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating TemperatureandSupplyVoltageRange(6)
7035X15
Com'l Only
7035X20
Com'l & Ind
Symbol
BUSY TIMING (M/S=VIH
Parameter
Min.
Max.
Min.
Max.
Unit
)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
t
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
15
17
____
____
t
5
5
____
____
BUSY Disable to Valid Data(3)
t
18
30
t
Write Hold After BUSY(5)
12
15
____
____
BUSY TIMING (M/S=VIL
)
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
0
ns
ns
tWH
12
15
PORT-TO-PORT DELAY TIMING
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
30
25
45
30
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
4088 tbl 14
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH)" or "Timing Waveform of Write with
Port-To-Port Delay (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention with Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention with Port "A".
6. 'X' in part numbers indicates power rating (S or L).
11
6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Port-to-Port Read and BUSY(2,5) (M/S = VIH)(4)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
tDH
DATAIN "A"
VALID
(1)
tAPS
ADDR"B"
MATCH
tBAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
4088 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE) then BUSY is an input BUSY"A" = VIL and BUSY"B" = "don't care."
5. All timing is the same for left and right ports. Port "A" may be either the left of right port. Port "B" is the opposite port from Port "A".
Timing Waveform of Write with BUSY
t
WP
R/W"A"
t
WB(3)
BUSY"B"
t
WH(1)
R/W"B"
,
(2)
4088 drw 12
NOTES:
1. tWH must be met for both BUSY input (slave) output master.
2. BUSY is asserted on port "B" Blocking R/W"B", until BUSY"B" goes HIGH
3. tWB is only for the 'Slave' Version.
6.42
12
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
APS
t
CE"B"
tBAC
t
BDC
BUSY"B"
4088 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDRESS "N"
(2)
tAPS
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
4088 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
7035X15
7035X20
Com'l Only
Com'l & Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
0
____
____
t
15
15
20
20
____
____
t
Interrupt Reset Time
ns
4088 tbl 15
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
13
6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
t
WC
INTERRUPT SET ADDRESS (2)
ADDR"A"
(4)
(3)
t
AS
tWR
CE"A"
R/W"A"
INT"B"
(3)
INS
t
4088 drw 15
t
RC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
tAS
OE"B"
(3)
tINR
INT"B"
4088 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Flag Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III — Interrupt Flag(1,2)
Left Port
Right Port
R/W
L
A
0L-A12L
R/W
R
A
0R-A12R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CE
L
OE
L
INT
L
CE
R
OE
R
INTR
(2)
L
X
X
X
L
X
X
L
X
X
X
L
1FFF
X
X
X
X
L
L
X
X
L
X
1FFF
1FFE
X
L
R
(3)
X
X
H
R
(3)
X
L
L
X
X
X
L
(2)
1FFE
H
X
X
L
4088 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
6.42
14
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
A
OL-A12L
(1)
(1)
AOR-A12R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
(3)
MATCH
(2)
(2)
Write Inhibit
4088 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. BUSY are inputs when configured as a slave. BUSYx outputs on the IDT7035
are push pull, not open drain outputs. On slaves the BUSY asserted internally inhibits write.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D17 Left
D0
- D17 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
4088 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7035.
2. There are eight semaphore flags written to via I/O0 and read from all I/0's. These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
FunctionalDescription
(INTL) is asserted when the right port writes to memory location 1FFE
(HEX),whereawriteisdefinedastheCER=R/WR=VIL perTruthTable
III.Theleftportclearstheinterruptbyanaddresslocation1FFEaccess
when CEL = OEL = VIL, R/WL is a "don't care". Likewise, the right port
interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation
1FFF(HEX)andtocleartheinterruptflag(INTR),therightportmustaccess
the memory location 1FFF, The message (18 bits) at 1FFE or 1FFF is
user-defined, since itis anaddressable SRAMlocation. Ifthe interrupt
functionisnotused,addresslocations1FFEand1FFFarenotusedas
TheIDT7035providestwoportswithseparatecontrol,addressand
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation
inmemory.TheIDT7035hasanautomaticpowerdownfeaturecontrolled
by CE. The CE controls on-chip power down circuitry that permits the
respectiveporttogointoastandbymodewhennotselected(CEHIGH).
Whenaportisenabled,accesstotheentirememoryarrayispermitted.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox mailboxes,butaspartoftherandomaccessmemory.RefertoTruthTable
ormessage center)is assignedtoeachport. The leftportinterruptflag IIIfortheinterruptoperation.
15
6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Busy Logic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
CE
CE
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
BUSY
R
BUSY
L
BUSY
R
BUSY
L
CE
MASTER
Dual Port
RAM
CE
SLAVE
Dual Port
RAM
BUSY
R
BUSY
R
BUSY
R
BUSY
L
BUSYL
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
anduse anyBUSYindicationas aninterruptsource toflagthe eventof
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
TheBUSYoutputsontheIDT7035RAMinmastermode,arepush-
pulltypeoutputsanddonotrequirepullupresistorstooperate.Ifthese
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
BUSY
L
.
4088 drw 17
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7035 RAMs.
leftportinnowayslows theaccess timeoftherightport.Bothports are
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM
enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol
on-chippowerdowncircuitrythatpermits the respective porttogointo
standbymodewhennotselected. Thisistheconditionwhichisshownin
Truth Table I where CE and SEM = VIH.
SystemswhichcanbestusetheIDT7035containmultipleprocessors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit
from a performance increase offered by the IDT7035's hardware
semaphores, which provide a lockout mechanism without requiring
complexprogramming.
Width Expansion with BUSY Logic
Master/SlaveArrays
WhenexpandinganIDT7035RAMarrayinwidthwhileusingBUSY
logic,onemasterpartisusedtodecidewhichsideoftheRAMarraywill
receiveaBUSYindication,andtooutputthatindication.Anynumberof
slaves to be addressed in the same address range as the master, use
theBUSYsignalasawriteinhibitsignal.ThusontheIDT7035RAMthe
BUSYpinisanoutputifthepartisusedasamaster(M/S=VIH),andthe
BUSYpin is an input if the part used as a slave (M/S =VIL) as shown in
Figure 3.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. Itignores whetheranaccess is a readorwrite. In
a master/slave array, bothaddress andchipenable mustbe validlong
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables.Failure
toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland
corrupteddataintheslave.
Softwarehandshakingbetweenprocessors offers themaximumin
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations.TheIDT7035doesnotuseitssemaphoreflagstocontrol
anyresourcesthroughhardware,thusallowingthesystemdesignertotal
flexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methodsofhardwarearbitrationisthatwaitstatesareneverincurredin
either processor. This can prove to be a major advantage in very high-
speedsystems.
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
processorwantstousethisresource,itrequeststhetokenbysettingthe
latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
it. If it was successful, it proceeds to assume control over the shared
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe
Semaphores
TheIDT7035isanextremelyfastDual-Port8Kx18CMOSStaticRAM
withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.
TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port
RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby
thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe
usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe
Dual-Port RAM or any other shared resource.
The Dual-PortRAMfeatures a fastaccess time, andbothports are
completelyindependentofeachother.Thismeansthattheactivityonthe
6.42
16
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
that semaphore’s status or remove its request for that semaphore to into a semaphore flag. Whichever latch is first to present a zero to the
performanothertaskandoccasionallyattemptagaintogaincontrolofthe semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
tokenviathesetandtestsequence.Oncetherightsidehasrelinquished sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
thetoken,theleftsideshouldsucceedingainingcontrol.
semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch
ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
azerointoasemaphorelatchandisreleasedwhenthesamesidewrites overtotheothersideassoonasaoneiswrittenintothefirstside’srequest
aonetothatlatch.
latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest
The eightsemaphore flags reside withinthe IDT7035ina separate latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
memoryspacefromtheDual-PortRAM.This addressspaceisaccessed is requestedandthe processorwhichrequesteditnolongerneeds the
byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe resource, the entire system can hang up until a one is written into that
semaphore flags) and using the other control pins (Address, OE, and semaphorerequestlatch.
R/W)astheywouldbeusedinaccessingastandardStaticRAM. Each
The criticalcase ofsemaphore timingis whenbothsides requesta
oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside single token by attempting to write a zero into it at the same time. The
throughaddresspinsA0 –A2. Whenaccessingthesemaphores,none semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-
oftheotheraddresspinshasanyeffect.
neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel thetoken.Ifonesideisearlierthantheotherinmakingtherequest,thefirst
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero sidetomaketherequestwillreceivethetoken.Ifbothrequestsarriveat
on that side and a one on the other side (see Truth Table V). That thesametime,theassignmentwillbearbitrarilymadetooneportorthe
semaphorecannowonlybemodifiedbythesideshowingthezero.When other.
aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
One caution that should be noted when using semaphores is that
settoaoneforbothsides(unlessasemaphorerequestfromtheotherside semaphoresalonedonotguaranteethataccesstoaresourceissecure.
ispending)andthencanbewrittentobybothsides. Thefactthattheside Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused
whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites ormisinterpreted, a software errorcaneasilyhappen.
fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
Initializationofthesemaphoresisnotautomaticandmustbehandled
communications.(Athoroughdiscussionontheuseofthisfeaturefollows viatheinitializationprogramatpower-up.Sinceanysemaphorerequest
shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth
storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis sidesshouldhaveaonewrittenintothematinitializationfrombothsides
freedbythefirstside.
to assure that they will be free when needed.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
signalsgoactive.Thisservestodisallowthesemaphorefromchanging
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
cause either signal (SEM or OE) to go inactive or the output will never
change.
UsingSemaphores—SomeExamples
Perhapsthesimplestapplicationofsemaphoresistheirapplicationas
resourcemarkersfortheIDT7035’sDual-PortRAM.Saythe8Kx18RAM
was tobedividedintotwo4Kx18blocks whichweretobededicatedat
anyonetimetoservicingeithertheleftorrightport.Semaphore0could
be used to indicate the side which would control the lower section of
memory,andSemaphore1couldbedefinedasthe indicatorfortheupper
sectionofmemory.
AsequenceWRITE/READmustbeusedbythesemaphoreinorder
to guarantee that no system level contention will occur. A processor
requestsaccesstosharedresourcesbyattemptingtowriteazerointoa
semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore
requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,
afactwhichtheprocessorwillverifybythesubsequentread(seeTruth
TableV).Asanexample,assumeaprocessorwritesazerototheleftport
atafreesemaphorelocation.Onasubsequentread,theprocessorwill
verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol
overtheresourceinquestion.Meanwhile,ifaprocessorontherightside
attempts towriteazerotothesamesemaphoreflagitwillfail,as willbe
verifiedbythefactthataonewillbereadfromthatsemaphoreontheright
side during subsequent read. Had a sequence of READ/WRITE been
usedinstead,systemcontentionproblemscouldhaveoccurredduringthe
gap between the read and write cycles.
Totakearesource,inthis examplethelower4KofDual-PortRAM,
the processor on the left port could write and then read a zero in to
Semaphore0.Ifthistaskwassuccessfullycompleted(azerowasread
back rather than a one), the left processor would assume control
of the lower 4K. Meanwhile the right processor was attempting to gain
controlofthe resourceaftertheleftprocessor,itwouldreadbackaone
inresponsetothezeroithadattemptedtowriteintoSemaphore0.Atthis
point,thesoftwarecouldchoosetotryandgaincontrolofthesecond4K
sectionbywriting,thenreadingazerointoSemaphore1.Ifitsucceeded
ingainingcontrol,itwouldlockouttheleftside.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo
itssemaphorerequestandperformothertasksuntilitwasabletowrite,then
readazerointoSemaphore1.Iftherightprocessorperformsasimilartask
withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap
4Kblocks ofDual-PortRAMwitheachother.
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation.The
reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
17
6.42
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
The blocks do not have to be any particular size and can even be been performed, both processors can access their assigned RAM
variable, depending upon the complexity of the software using the segmentsatfullspeed.
semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual-
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
PortRAMorothersharedresources intoeightparts. Semaphores can case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor
evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing mayberesponsibleforbuildingandupdatingadatastructure.Theother
given a common meaning as was shown in the example above.
processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting
Semaphores are a useful form of arbitration in systems like disk processorreadsanincompletedatastructure,amajorerrorconditionmay
interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo
atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks
ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea itandthenisabletogoinandupdatethedatastructure.Whentheupdate
was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess is completed, the data structure block is released. This allows the
theirassignedportionsofmemorycontinuouslywithoutanywaitstates. interpretingprocessortocomebackandreadthecompletedatastructure,
Semaphoresarealsousefulinapplicationswherenomemory“WAIT” therebyguaranteeingaconsistentdatastructure.
stateisavailableononeorbothsides.Onceasemaphorehandshakehas
L PORT
SEMAPHORE
R PORT
SEMAPHORE
REQUEST FLIP FLOP
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
4088 drw 18
Figure 4. IDT7035 Semaphore Logic
6.42
18
IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to + 85°C)
PF
100-pin TQFP (PN100-1)
Commercial Only
15
20
Speed in nanoseconds
Commercial & Industrial
S
L
Standard Power
Low Power
7035
144K (8K x 18) Dual-Port RAM
4088 drw 19
DatasheetDocumentHistory
1/18/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmetictypographicalcorrections
Addedadditionalnotestopinconfigurations
Page 9 Fixed typographical error
Changeddrawingformat
5/19/99:
6/4/99:
Page 1 Corrected DSC number
RemovedPreliminary
9/1/99:
10/4/99:
11/10/99:
5/23/00:
AddedIndustrialTemperatureRanges andremovedcorrespondingnotes
Replaced IDT logo
Page 4 Increasedstoragetemperatureparameter
ClarifiedTAparameter
Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed±500mVto0mVinnotes
8/20/01:
Page 14 Correctednote superscriptinTruthTable III
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www.idt.com
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19
6.42
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