IDT70824S20G [IDT]
HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM⑩); HIGH -SPEED 4K X 16顺序存取随机存取存储器（ SARAM⑩ ）
| 型号： | IDT70824S20G |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM⑩) |
| 文件： | 总21页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH SPEED 64K (4K X 16 BIT)
SEQUENTIAL ACCESS
IDT70824S/L
RANDOM ACCESS MEMORY (SARAM™)
Features
◆
◆
High-speed access
Compatible with Intel BMIC and 82430 PCI Set
Width and Depth Expandable
Sequential side
– Address based flags for buffer control
◆
– Military:35/45ns(max.)
◆
– Commercial:20/25/35/45ns(max.)
Low-power operation
◆
– IDT70824S
– Pointer logic supports up to two internal buffers
Battery backup operation - 2V data retention
TTL-compatible, single 5V (+10%) power supply
Available in 80-pin TQFP and 84-pin PGA
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
Active:775mW(typ.)
Standby: 5mW (typ.)
– IDT70824L
◆
◆
◆
Active:775mW(typ.)
Standby: 1mW (typ.)
◆
◆
™
4Kx16SequentialAccess RandomAccess Memory (SARAM )
– Sequential Access from one port and standard Random
Access from the other port
– Separate upper-byte and lower-byte control of the
RandomAccessPort
High speed operation
– 20ns tAA for random access port
– 20ns tCD for sequential port
Description
TheIDT70824isahigh-speed4Kx16-BitSequentialAccessRandom
AccessMemory(SARAM).TheSARAMoffersasingle-chipsolutionto
bufferdatasequentiallyononeport,andbeaccessedrandomly(asyn-
chronously) through the other port. The device has a Dual-Port RAM
based architecture with a standard SRAM interface for the random
(asynchronous) access port, and a clocked interface with counter se-
◆
◆
– 25nsclockcycletime
Architecture based on Dual-Port RAM cells
FunctionalBlockDiagram
12
RST
SCLK
CNTEN
A0-11
CE
OE
Random
Sequential
SOE
Access
Access
SSTRT1
Port
R/W
Port
Controls
LB LSB
UB MSB
SSTRT2
Controls
SCE
SR/W
SLD
4K X 16
Memory
Array
CMD
16
16
16
DataR
AddrR
Reg.
12
DataL
AddrL
I/O0-15
SI/O0-15
,
12
12
RST
12
Pointer/
Counter
12
12
Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
End Address for Buffer #2
Flow Control Buffer
Flag Status
12
EOB1
EOB2
COMPARATOR
3099 drw 01
APRIL 2000
1
©2000IntegratedDeviceTechnology,Inc.
DSC-3099/5
6.07
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
The IDT70824is packagedina 80-pinThinQuadFlatpack(TQFP)
or84-pinPinGridArray(PGA).Militarygradeproductis manufactured
incompliancewiththelatestrevisionofMIL-PRF-38535QML,makingit
ideallysuitedtomilitarytemperatureapplicationsdemandingthehighest
levelofperformanceandreliability.
quencingforthesequential(synchronous)accessport.
FabricatedusingCMOShigh-performancetechnology,thismemory
devicetypicallyoperatesonlessthan775mWofpoweratmaximumhigh-
speed clock-to-data and Random Access. An automatic power down
feature,controlledbyCE,permitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
PinConfigurations(1,2,3)
INDEX
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
SI/O1
SI/O0
GND
N/C
SCE
SR/W
RST
SLD
SSTRT2
SSTRT1
GND
GND
CNTEN
SOE
SCLK
GND
EOB2
EOB1
VCC
A11
A10
A9
A8
A7
A6
A5
A4
A3
60
59
1
2
58
57
56
55
54
3
4
5
6
7
8
53
52
51
9
IDT70824PF
PN80-1(4)
A2
10
11
12
13
14
15
16
17
18
19
20
50
49
VCC
VCC
A1
80-Pin TQFP
Top View(5)
48
47
A0
46 CMD
45
CE
LB
UB
44
43
42
41
R/
W
OE
I/O0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
,
3099 drw 02
63
61
60
58
55
54
48
46
45
42
51
11
EOB1
SSTRT2
NC
SR/
W
I/O1
V
CC
CNTEN
GND
GND
GND NC
66
64
62
59
56
49
47
44
43
40
50
10
09
08
07
06
05
04
03
02
01
EOB2 SOE RST
SCE SI/O0 SI/O1
I/O2
SLD
NC
SI/O3
I/O0
67
65
57
53
41
39
52
1
SSTRT
2
I/O3 GND
SCLK GND
SI/O
V
CC
69
68
38
37
I/O4
VCC
SI/O4 SI/O5
72
71
73
33
35
34
I/O7 I/O6
SI/O8
GND
SI/O GND
7
IDT70824G
G84-3(4)
75
70
74
32
31
36
I/O9
I/O5
I/O
8
SI/O
9
SI/O10
SI/O
6
84-Pin PGA
Top View(5)
76
77
78
28
29
30
I/O10 I/O11
V
CC
SI/O12 VCC SI/O11
79
80
26
27
I/O12
I/O13
SI/O14
SI/O
13
81
83
7
11
12
23
25
I/O14
CMD
V
CC
A
2
NC
15
NC SI/O
82
1
2
4
5
6
8
9
10
14
17
20
22
24
OE
LB
CC
A
4
A7
A10
I/O15 GND
A0
V
GND GND
84
3
15
13
16
18
19
21
UB
CE
NC R/W
A8
A
1
A
5
A3
A
6
A
9
A
11
,
A
B
C
D
E
F
G
H
J
K
L
Pin 1
Designator
3099 drw 03
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PN80-1 package body is approximately 14mm x 14mm x 1.4mm.
G84-3 package body is approximately 1.12 in x 1.12 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Pin Descriptions: Random Access Port(1)
SYMBOL
NAME
I/O
DESCRIPTION
A0-A11
Address Lines
I
I
I
Address inputs to access the 4096-word (16-Bit) memory array.
I/O0-I/O15
Inputs/Outputs
Chip Enable
Random access data inputs/outputs for 16-Bit wide data.
When CE is LOW, the random access port is enabled. When CE is HIGH, the random access port is disabled
into power-down mode and the I/O outputs are in the High-impedance state. All data is retained during CE =
VIH, unless it is altered by the sequential port CE and CMD may not be LOW at the same time.
CE
Control Register Enable
Read/Write Enable
Output Enable
I
I
When CMD is LOW, address lines A0-A2, R/W, and inputs and outputs I/O0-I/O12, are used to access the
control register, the flag register and the start and end of buffer registers. CMD and CE may not be LOW at the
same time.
CMD
R/W
If CE is LOW and CMD is HIGH, data is written into the array when R/W is LOW and read out of the array when
W
CE
CMD
W
CE
R/ is HIGH. If
is HIGH and
is LOW, R/ is used to access the buffer command registers. and
CMD may not be LOW at the same time.
I
I
When OE is LOW and R/W is HIGH, I/O0-I/O15 outputs are enabled. When OE is HIGH, the I/O outputs are in
OE
the High-impedance state.
Lower Byte, Upper Byte
Enables
When LB is LOW, I/O0-I/O7 are accessible for read and write operations. When LB is HIGH, I/O0-I/O7 are tri-
LB, UB
stated and blocked during read and write operations. UB controls access for I/O8-I/O15 in the same manner and
is asynchronous
from LB.
VCC
Power Supply
Ground
I
I
Seven +5 power supply pins. All VCC pins must be connected to the same +5V VCC supply.
GND
Ten ground pins. All ground pins must be connected to the same ground supply.
3099 tbl 01
Pin Descriptions: Sequential Access Port(1)
SYMBOL
SI/O0-15
SCLK
NAME
I/O DESCRIPTION
Inputs/Outputs
Clock
I/O Sequential data inputs/outputs for 16-bit wide data.
I
SI/O0-SI/O15,SCE, SR/W, and SLD are registered on the LOW-to-HIGH transition of SCLK. Also, the sequential
access port address pointer increments by 1 on each LOW-TO-HIGH transition of SCLK when CNTEN is LOW.
Chip Enable
I
When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transition of SCLK. When SCE
is HIGH, the sequential access port is disabled into powered-down mode on the LOW-to-HIGH transition of
SCLK, and the SI/O outputs are in the High-impedance state. All data is retained, unless altered by the random
access port.
SCE
CNTEN
is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK. This function is
Counter Enable
I
I
When
CNTEN
independent of CE.
SR/W
Read/Write Enable
When SR/W and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of SCLK. When SR/W is
HIGH, and SCE and SOE are LOW, a read cycle is initiated on the LOW-to-HIGH transition of SCLK. Termination
of a write cycle is done on the LOW-to-HIGH transition of SCLK if SR/W or SCE is HIGH.
Address Pointer Load Control
I
When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. When
SLD is LOW, data on the inputs SI/O0-SI/O11 is loaded into a data-in register on the LOW-to-HIGH transition of
SCLK. On the Cycle following SLD, the address pointer charges to the address location contained in the data-
in register. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle following SLD.
SLD
Load Start of Address
Register
I
When SSTRT1 or SSTRT2 is LOW, the startof address register #1 or #2 is loaded into the address pointer on
the LOW-to-HIGH transition of SCLK. The start addresses are stored in internal registers. SSTRT1 and SSTRT2
may not be LOW while SLD is LOW or during the cycle following SLD.
SSTRT1,
SSTRT2
End of Buffer Flag
O
EOB1,
EOB2
EOB1 or EOB2 is output low when the address pointer is incremented to match the address stored in the end
of buffer registers. The flags can be cleared by either asserting RST LOW or by writing zero into Bit 0 and/or
Bit 1 of the control register at address 101. EOB1 and EOB2 are dependent on separate internal registers, and
therefore separate match addresses.
Output Enable
Reset
I
I
SOE
SOE controls the data outputs and is independent of SCLK. When SOE is LOW, output buffers and the
sequentially addressed data is output. When SOE is HIGH, the SI/O output bus is in the High-impedance state.
SOE is asynchronous to SCLK.
When RST is LOW, all internal registers are set to their default state, the address pointer is set to zero and the
EOB1 and EOB2 flags are set HIGH. RST is asynchronous to SCLK.
RST
3099 tbl 02
NOTE:
1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output.
6.42
3
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureandSupplyVoltage
Symbol
Rating
Commercial
& Industrial
Military
Unit
Grade
GND
Vcc
(2)
Ambient Temperature
-55OC to +125OC
0OC to +70OC
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
+
5.0V 10%
Military
0V
0V
0V
Temperature
Under Bias
-55 to +125
-55 to +125
50
-65 to +135
-65 to +150
50
oC
oC
Commercial
Industrial
+
5.0V 10%
TBIAS
TSTG
IOUT
-40OC to +85OC
5.0V 10%
+
Storage
Temperature
3099 tbl 04
NOTES:
1. This is the parameter TA.
2. Industrial temperature: for specific speeds, packages and powers contact
your sales office.
DC Output
Current
mA
3099 tbl 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
RecommendedDCOperating
Conditions
Symbol
Parameter
Min.
Typ. Max. Unit
VCC
Supply Voltage
4.5
5.0
5.5
0
V
V
V
GND Ground
0
0
(2)
____
VIH
VIL
Input High Voltage
Input Low Voltage
2.2
6.0
Capacitance
(TA = +25°C, f = 1.0mhz, TQFP only)
-0.5(1)
0.8
V
____
Symbol
CIN
Parameter
Input Capacitance
Output Capacitance
Conditions(2 )
Max. Unit
3099 tbl 05
NOTES:
VIN = 3dV
9
pF
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
COUT
VOUT = 3dV
10
pF
3099 tbl 06
NOTES:
1. This parameter is determined by device characterization, but is not
production tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
70824S
70824L
Symbol
|ILI|
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
VOUT = 0V to VCC
Min.
Max.
5
Min.
Max.
Unit
µA
µA
V
___
___
1
1
___
___
___
___
|ILO|
5
VOL
IOL = +4mA
0.4
0.4
___
___
VOH
Output High Voltage
IOH = -4mA
2.4
2.4
V
3099 tbl 07
4
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,2,8)(VCC = 5.0V ± 10%)
70824X20
Com'l Only
70824X25
Com'l Only
70824X35
Com'l &
Military
70824X45
Com'l &
Military
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
CC
I
Dynamic Operating
Current
(Both Ports Active)
S
L
180
180
380
330
170
170
360
310
160
160
340
290
155
155
340
290
mA
L
R
IL
CE and CE = V ,
Outputs Open
(5)
IL
SCE = V
____
____
____
____
____
____
____
____
(3)
MIL &
IND
S
L
160
160
400
340
155
155
400
340
MAX
f = f
(7)
IH
SB1
I
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
25
25
70
50
25
25
70
50
20
20
70
50
16
16
70
50
mA
mA
mA
mA
SCE and CE = V
IH
CMD = V
(3)
MAX
f = f
____
____
____
____
____
____
____
____
MIL &
IND
S
L
20
20
85
65
16
16
85
65
SB2
I
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
115
115
260
230
105
105
250
220
95
95
240
210
90
90
240
210
IH
CE or SCE = V
Active Port Outputs Open,
(3)
MAX
f=f
____
____
____
____
____
____
____
____
MIL &
IND
S
L
95
95
290
250
90
90
290
250
SB3
I
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE and
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
(6)
CC
SCE > V - 0.2V
IN
CC
V
> V - 0.2V or
2V,
____
____
____
____
____
____
____
____
IN
V
f = 0
< 0.
MIL &
IND
S
L
1.0
0.2
30
10
1.0
0.2
30
10
(4)
SB4
I
Full Standby Current
(One Port -
CMOS Level Inputs)
One Port CE or
COM'L
S
L
110
110
240
200
100
100
230
190
90
90
220
180
85
85
220
180
(6,7)
CC
SCE > V - 0.2V
Outputs Open (Active Port)
____
____
____
____
____
____
____
____
(3)
MIL &
IND
S
L
90
90
260
215
85
85
260
215
MAX
f = f
V
IN
CC IN
> V - 0.2V or V < 0.2V
3099 tbl 08
NOTES
1. 'X' in part number indicates power rating (S or L).
2. VCC = 5V, TA = +25°C; guaranteed by device characterization but not production tested.
3. At f = fMAX, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5. SCE may transition, but is Low (SCE=VIL) when clocked in by SCLK.
6. SCE may be - 0.2V, after it is clocked in, since SCLK=VIH must be clocked in prior to powerdown.
7. If one port is enabled (either CE or SCE = LOW) then the other port is disabled (SCE or CE = HIGH, respectively). CMOS HIGH > Vcc - 0.2V and LOW < 0.2V, and
TTL HIGH = VIH and LOW = VIL.
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC < 0.2V, VHC > VCC - 0.2V)
Symbol
VDR
ICCDR
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
V
___
___
VCC for Data Retention
VCC = 2V
2.0
___
Data Retention Current
µA
CE = VHC
MIL. & IND.
COM'L.
100
4000
___
___
VIN = VHC or = VLC
100
1500
(3)
SCE = VHC(4) when SCLK = u
CMD > VHC
___
___
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
V
(3)
(2)
___
___
tR
tRC
V
3099 tbl 09
NOTES :
1. TA = +25°C, VCC = 2V; guaranteed by device characterization but not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by device characterization, but is not production tested.
4. To initiate data retention, SCE = VIH must be clocked in.
6.42
5
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
DataRetentionPowerDown/UpWaveform(RandomandSequentialPort)(1,2)
DATA RETENTION MODE
VCC
4.5V
≥
4.5V
VDR 2V
tCDR
tR
VDR
VIH
CE
VIH
SCLK
SCE
tPD
tPU
ICC
3099 drw 04
ISB
ISB
NOTES :
1. SCE is synchronized to the sequential clock input.
2. CMD > VCC - 0.2V.
5V
5V
Ω
893
893Ω
DATAOUT
DATAOUT
30pF
347Ω
5pF*
Ω
347
3099 drw 06
3099 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load (for tCLZ, tBLZ, tOLZ, tCHZ, tBHZ,
tOHZ,tWHZ, tCKHZ, and tCKLZ)
(*Including scope and jig.)
8
7
6
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
Input Rise/Fall Times
tAA/tCD/tEB
(Typical, ns)
5
4
3
2
1
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
10pF is the I/O
capacitance of
this device, and
30pF is the AC
Test Load
1.5V
Figures 1,2 and 3
3099 tbl 10
capacitance.
-1
-2
-3
20 40 60 80 100 120 140 160 180 200
,
3099 drw 07
CAPACITANCE (pF)
Figure 3. Lumped Capacitance Load Typical Derating Curve
6
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Truth Table I: Random Access Read and Write(1,2)
Inputs/Outputs
R/W
H
H
H
L
I/O0-I/O7
DATAOUT
DATAOUT
High-Z
I/O8-I/O15
MODE
CE
L
CMD
H
OE
L
LB
L
UB
L
DATAOUT Read both Bytes.
L
H
L
L
H
L
High-Z
Read lower Byte only.
L
H
L
H
L
DATAOUT Read upper Byte only.
(3)
L
H
H
L
DATAIN
DATAIN
High-Z
DATAIN
High-Z
DATAIN
High-Z
High-Z
High-Z
DATAIN
DATAOUT
Write to both Bytes.
(3)
L
H
L
H
L
H
L
Write to lower Byte only.
Write to upper Byte only.
(3)
L
H
L
H
X
H
X
H
X
X
H
H
L
H
X
H
X
L
X
X
H
High-Z
Both Bytes deselected and powered down.
Outputs disabled but not powered down.
Both Bytes deselected but not powered down.
Write I/O0-I/O11 to the Buffer Command Register.
H
High-Z
L
H
High-Z
(3)
(4)
(4)
H
H
L
H
L
L
L
DATAIN
DATAOUT
(4)
(4)
L
L
L
H
Read contents of the Buffer Command Register
via I/O0-I/O12.
3099 tbl 11
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and HIGH-Z = High-impedance.
2. RST, SCE, CNTEN, SR/W, SLD, SSTRT1, SSTRT2, SCLK, SI/O0-SI/O15, EOB1, EOB2, and SOE are unrelated to the random access port control and operation.
3. If OE = VIL during write, tWHZ must be added to the tWP or tCW write pulse width to allow the bus to float prior to being driven.
4. Byte operations to control register using UB and LB separately are also allowed.
Truth Table II: Sequential Read(1,2,3,6,8)
Inputs/Outputs
SCLK
SR/W
H
SI/O
MODE
SCE
L
CNTEN
EOB1
EOB2 SOE
L
H
L
H
L
LOW
LAST
L
L
L
L
H
[EOB1]
Counter Advanced Sequential Read with EOB1 reached.
↑
↑
↑
↑
↑
L
H
LAST LAST
LAST LOW
LAST LAST
LOW LOW
[EOB1 - 1] Non-Counter Advanced Sequential Read, without EOB1 reached
[EOB2] Counter Advanced Sequential Read with EOB2 reched.
[EOB2 - 1] Non-Counter Advanced Sequential Read without EOB2 reached
High-Z Counter Advanced Sequential Non-Read with EOB1 and EOB2 reached
L
H
L
H
L
H
3099 tbl 12
Truth Table III: Sequential Write(1,2,3,4,5,6,7,8)
Inputs/Outputs
SCLK
SR/W
L
1
2
SI/O
MODE
SCE
L
CNTEN
EOB
LAST LAST
LOW LOW
EOB
SOE
H
H
L
H
L
SI/OIN Non-Counter Advanced Sequential Write, without EOB1 or EOB2 reached.
SI/OIN Counter Advanced Sequential Write with EOB1 and EOB2 reached.
High-Z No Write or Read due to Sequential port Deselect. No counter advance.
High-Z No Write or Read due to Sequential port Deselect. Counter does advance.
↑
L
L
H
↑
H
X
LAST LAST
NEXT NEXT
X
↑
↑
H
X
X
3099 tbl 13
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and HIGH-Z = High-impedance. LOW = VOL.
2. RST, SLD, SSTRT1, SSTRT2 are continuously HIGH during a sequential write access, other than pointer access operations.
3. CE, OE, R/W, CMD, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation except for CMD which must not be used concurrently with the
sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access.
4. SOE must be HIGH (SOE=VIH) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising edge
of the clock during the cycle in which SR/W = VIL.
5. SI/OIN refers to SI/O0-SI/O15 inputs.
6. "LAST" refers to the previous value still being output, no change.
7. Termination of a write is done on the LOW-to-HIGH transition of SCLK if SR/W or SCE is HIGH.
8. When CLKEN=LOW, the address is incremented on the next rising edge before any operation takes place. See the diagrams called "Sequential Counter Enable Cycle
after Reset, Read (and write) Cycle".
6.42
7
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Truth Table: Sequential AddressPointerOperations(1,2,3,4,5)
Inputs/Outputs
SCLK
MODE
SLD
H
SSTRT1
SSTRT1
SOE
X
L
H
H
H
L
Non-Counter Advanced Sequential Write, without EOB1 or EOB2 reached.
Counter Advanced Sequential Write with EOB1 and EOB2 reached.
No Write or Read due to Sequential port Deselect. No counter advance.
↑
↑
↑
H
X
(6)
L
H
H
3099 tbl 14
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance.
2. RST is continuously HIGH. The conditions of SCE CNTEN, and SR/W are unrelated to the sequential address pointer operations.
3. CE, OE, R/W, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation, except for CMD which must not be used concurrently with the sequential
port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access.
4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table.
5. When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. The state of CNTEN is ignored and the address is not incremented
during the two cycles.
6. SOE may be LOW with SCE deselect or in the write mode using SR/W.
Address Pointer Load Control (SLD)
InSLDmode,thereisaninternaldelayofonecyclebeforetheaddress changestotheaddresslocationcontainedinthedata-inregister.SSTRT1,
pointerchangesinthecyclefollowingSLD.WhenSLDisLOW,dataon SSTRT2maynotbelowwhileSLDisLOW,orduringthecyclefollowing
theinputsSI/O0-SI/O11 isloadedintoadata-inregisterontheLOW-to- SLD.TheSSTRT1andSSTRT2requireonlyoneclockcycle,sincethese
HIGHtransitionofSCLK.OnthecyclefollowingSLD,theaddresspointer addresses are pre-loaded in the registers already.
SLDMode(1)
SLD
SCLK(1)
B
A
C
SI/O0-11
ADDRIN
DATAOUT
SSTRT(1 or 2)
3099 drw 08
NOTE:
1. At SCLK edge (A), SI/O0-SI/O11 data is loaded into a data-in register. At edge (B), contents of the data-in register are loaded into the address pointer (i.e.
address pointer changes). At SCLK edge (A), SSTRT1 and SSTRT2 must be HIGH to ensure for proper sequential address pointer loading. At SCLK edge (B),
SLD and SSTRT1,2 must be HIGH to ensure for proper sequential address pointer loading. For SSTRT1 or SSTRT2, the data to be read will be ready for edge
(B), while data will not be ready at edge (B) when SLD is used, but will be ready at edge (C).
Sequential Load of Address into Pointer/Counter(1)
15
H
14
H
13
H
12
L
11 -------------------------------------------------------------------------------------------------- 0
Address Loaded into Pointer
LSB SI/O BITS
MSB
3099 drw 09
NOTE:
1. "H" = VIH and "L" = VIL for the SI/O intput state.
8
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Reset (RST)
SettingRSTLOWresetsthecontrolstateoftheSARAM.RSTfunctions
asynchronouslyofSCLK(i.e.notregistered).Thedefaultstatesaftera
resetoperationaredisplayedintheadjacentchart.
Register
Contents
0
Address
Cleared to HIGH state
BUFFER CHAINING
EOB Flags
Buffer Flow Mode
Start Address Buffer #1
End Address Buffer #1
0
(1)
4095 (4K)
(1)
Start Address Buffer #2
Cleared (set at invalid points)
Cleared (set at invalid points)
(1)
End Address Buffer #2
Registered State
SCE = V , SR/W = V
IH
IL
3099 tbl 15
NOTE:
1. Start address and End of address for Buffer #2 and the Flow Control for
both Buffer #1 and #2, must be programmed as described in the "Buffer
Command Mode" section.
Buffer Command Mode (CMD)
alsoallowsreadingandclearingthestatusoftheEOBflags.Sevendifferent
CMD cases are available dependingonthe conditions ofA0-A2 andR/
W.AddressbitsA3-A11anddataI/ObitsI/O12-I/O15arenotusedduring
thisoperation.
Buffer Command Mode (CMD) allows the random access port to
controlthestateofthetwobuffers.AddresspinsA0-A2andI/OpinsI/O0-
I/O11areusedtoaccessthestartofbufferandtheendofbufferaddresses
andtosettheflowcontrolmodeofeachbuffer.TheBufferCommandMode
Random Access Port CMD Mode(1)
Case #
A2-A0
R/W
0 (1)
0 (1)
0 (1)
0 (1)
0 (1)
0
DESCRIPTIONS
1
2
3
4
5
6
7
8
000
Write (read) the start address of Buffer #1 through I/O0-I/O11.
001
Write (read) the end address of Buffer #1 through I/O0-I/O11.
Write (read) the start address of Buffer #2 through I/O0-I/O11.
Write (read) the end address of Buffer #2 through I/O0-I/O11.
Write (read) flow control register.
010
011
100
101
Write only - clear EOB1 and/or EOB2 flag.
Read only - flag status register.
101
1
110/111
(X)
(Reserved)
3099 tbl 16
NOTE:
1. R/W input "0(1)" indicates a write(0) or read(1) occurring with the same address input.
Cases 1 through 4: Start and End of Buffer Register Description(1,2)
15
H
14
H
13
H
12
L
11 -------------------------------------------------------------------------------------------------- 0
Address Loaded into Buffer
LSB I/O BITS
MSB
3099 drw 10
NOTES:
1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state. "L" = VIL for I/O in the input state.
2. A write into the buffer occurs when R/W = VIL and a read when R/W = VIH. EOB1/SOB1 and EOB2/SOB2 are chosen through address A0-A2 while CMD = VIL and
CE = VIH.
Case 5: Buffer Flow Modes
WithintheSARAM,theusercandesignateoneoftwobufferflowmodes
foreachbuffer.Eachbufferflowmodedefinesauniquesetofactionsfor
thesequentialportaddresspointerandEOB flags.InBUFFERCHAIN-
INGmode,aftertheaddresspointerreachestheendofthebuffer,itsets
thecorrespondingEOBflagandcontinuesfromthestartaddressofthe
otherbuffer.InSTOPmode,theaddresspointerstopsincrementingafter
itreachestheendofthebuffer.Thereisnolinearormaskmodeavailable.
6.42
9
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Flow Control Register Description(1,2)
0
15
MSB
H
H
H
H
H
H
H
H
H
H
4
3
2
1
0
LSB I/O BITS
H
Counter Release
(STOP Mode Only)
Buffer #1 flow control
Buffer #2 flow control
3099 drw 11
NOTES:
1. "H" = VOH for I/O in the output state and "Don't Cares"' for I/O in the input state.
2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs asynchronously
of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next rising edge of SCLK that is enabled by CNTEN. The pointer is
also released by RST, SLD, SSTRT1 and SSTRT2 operations.
Flow Control Bits(5)
Flow Control
Bit 1 & Bit 0
Mode
Functional Description
(Bit 3 & Bit 2)
00
01
BUFFER
EOB1 (EOB2) is asserted (Active LOW output) when the pointer matches the end address of Buffer #1 (Buffer #2).
(1,3)
CHAINING
The pointer value is changed to the start address of Buffer #2 (Buffer #1)
STOP
EOB1 (EOB2) is asserted when the pointer matches the end address of Butler #1 (Butler #2).
The address pointer will stop incrementing when it reaches the next address (EOB address + 1), if CNTEN is LOW
on the next clock's rising edge. Otherwise, the address pointer will stop incrementing on EOB. Sequential write
operations are inhibited after the address pointer is stopped. The pointer can be released by bit 4 of the flow
control register.(1, 2,4)
3099 tbl 17
NOTES:
1. EOB1 and EOB2 may be asserted (set) at the same time, if both end addresses have been loaded with the same value.
2. CMD flow control bits are unchanged, the count does not continue advancement.
3. If EOB1 and EOB2 are equal, then the pointer will jump to the start of Buffer #1.
4. If the counter has stopped at EOBx and was released by bit 4 of the flow control register, CNTEN must be LOW on the next rising edge of SCLK; otherwise the flow
control will remain in the stop mode.
5. Flow Control Bit settings of '10' and '11' are reserved.
6. Start address and End of address for Buffer #2 and the Flow Control for both Buffer #1 and #2, must be programmed as described in the "Buffer Command Mode"
section. RST conditions are not set to valid addresses.
Cases 6 and 7: Flag Status Register Bit Description(1)
0
0
15
MSB
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1
LSB I/O BITS
End of buffer flag for Buffer #1
End of buffer flag for Buffer #2
NOTE:
1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state.
3099 drw 12
Cases 6: Flag Status Register
Write Conditions(1)
Case 7: Flag Status Register Read
Conditions
Flag Status Bit 0, (Bit 1)
Functional Description
Clears Buffer Flag EOB1, (EOB2).
No change to the Buffer Flag.(2)
Flag Status Bit 0, (Bit 1)
Functional Description
0
1
0
EOB1 (EOB2) flag has not been set, the
Pointer has not reached the End of the
Buffer.
3099 tbl 18
NOTES:
1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be
cleared while the second is left alone, or both may be cleared.
2. Remains as it was prior to the CMD operation, either HIGH (1) or LOW (0).
1
EOB1 (EOB2) flag has been set, the
Pointer has reached the end of the
Buffer.
3099 tbl 19
Cases 8 and 9: (Reserved)
Illegal operations. All outputs will be HIGH on the I/O bus during a READ.
10
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Random Access Port: AC Electrical Characteristics Over
theOperatingTemperatureandSupplyVoltageRange(2,4,5)
70824X20
Com'l Only
70824X25
Com'l Only
70824X35
Com'l &
Military
70824X45
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
____
____
____
____
Read Cycle Time
20
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
tAA
Address Access Time
20
20
20
25
25
25
35
35
35
45
45
45
____
____
____
____
____
____
____
____
____
____
____
____
tACE
tBE
Chip Enable Access Time
Byte Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Chip Select Low-Z Time(1)
Byte Select Low-Z Time(1)
Output Enable Low-Z Time(1)
Chip Select High-Z Time(1)
Byte Select High-Z Time(1)
Output Select High-Z Time(1)
Chip Select Power-Up Time
Chip Select Power-Down Time
tOE
10
10
15
20
____
____
____
____
tOH
3
3
3
3
3
3
3
3
3
3
3
3
____
____
____
____
____
____
____
____
____
____
____
____
tCLZ
tBLZ
tOLZ
tCHZ
tBHZ
tOHZ
tPU
2
2
2
2
____
.____
____
____
10
10
12
12
15
15
15
15
____
____
____
____
____
____
____
____
9
11
15
15
____
____
____
____
0
0
0
0
____
____
____
____
tPD
20
25
35
45
ns
3099 tbl 20
Random Access Port: AC Electrical Characteristics
Over the Operating Temperature and Supply Voltage(2,4,5)
70824X20
Com'l Only
70824X25
Com'l Only
70824X35
Com'l &
Military
70824X45
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tCW
tAW
tAS
Write Cycle Time
20
15
15
0
25
20
20
0
35
25
25
0
45
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write
Address Valid to End-of-Write(3)
Address Set-up Time
tWP
tBP
Write Pulse Width(3)
13
15
20
20
25
25
30
30
Byte Enable Pulse Width(3)
Write Recovery Time
tWR
tWHZ
tDW
tDH
tOW
0
0
0
0
Write Enable Output High-Z Time(1)
Data Set-up Time
10
12
15
15
____
____
____
____
____
____
____
____
13
0
15
0
20
0
25
0
____
____
____
____
____
____
____
____
Data Hold Time
Output Active from End-of-Write
3
3
3
3
ns
3099 tbl 21
NOTES:
1. Transition measured at 0mV from steady state. This parameter is guaranteed with the AC Output Test Load (Figure 1) by device characterization, but is not
production tested.
2. 'X' in part number indicates power rating (S or L).
3. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to
turn off and on the data to be placed on the bus for the required tDW. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum
write pulse is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degradation to tCW timing.
4. CMD access follows standard timing listed for both read and write accesses, (CE = VIH when CMD = VIL) or (CMD = VIH when CE = VIL).
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.42
11
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Waveform of Read Cycles: Random Access Port(1,2)
tRC
ADDR
tAA
tOH
(2)
tACS
CE
tCHZ
tCLZ
LB, UB
tBHZ
tBE
tBLZ
OE
tOE
tOLZ
tOHZ
I/OOUT
Valid Data Out
3099 drw 13
NOTES:
1. R/W is HIGH for read cycle.
2. Address valid prior to or coincident with CE transition LOW; otherwise tAA is the limiting parameter.
Waveform of Read Cycles: Buffer Command Mode
tRC
ADDR
tAA
tOH
tACS
(1)
CMD
tCHZ
tBHZ
tCLZ
LB, UB
tBE
tOE
tBLZ
OE
tOHZ
tOLZ
I/OOUT
Valid Data Out
3099 drw 14
NOTE:
1. CE = VIH when CMD = VIL.
12
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Waveform of Write Cycle No.1 (R/W Controlled Timing)
RandomAccessPort(1,6)
tWC
ADDR
tAW
R/W
(3)
(2)
tWR
tWP
tAS
(8)
(5)
CE, LB, UB
tDH
tDW
I/OIN
Valid Data In
OE
tOHZ
tWHZ
(4)
Data Out
Data Out(4)
I/OOUT
tACS
tBE
tOW
3099 drw 15
Waveform of Write Cycle No.2 (CE, LB, and/or UB Controlled Timing)
RandomAccessPort(1,6,7)
tWC
ADDR
tAW
(8)
(5)
CE,
,
LB UB
tAS
(3)
tWR
(2)
tCW
tBP
(2)
R/W
tDW
tDH
I/OIN
Valid Data
3099 drw 16
NOTES:
1. R/W, CE, or LB and UB must be inactive during all address transitions.
2. A write occurs during the overlap of R/W = VIL, CE = VIL and LB = VIL and/or UB = VIL.
3. tWR is measured from the earlier of CE (and LB and/or UB) or R/W going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state and the input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to
turn off and on the data to be placed on the bus for the required tDW. If OE is HIGH during the R/W controlled write cycle, this requirement does not apply and the minimum
write pulse is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degregation to tCW timing.
7. I/OOUT is never enabled, therefore the output is in High-Z state during the entire write cycle.
8. CMD access follows the standard CE access described above. If CMD = VIL, then CE must = VIH or, when CE = VIL, CMD must = VIH.
6.42
13
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Sequential Port: AC Electrical Characteristics Over
theOperating TemperatureandSupplyVoltageRange(1,3)
70824X20
Com'l Only
70824X25
Com'l Only
70824X35
Com'l &
Military
70824X45
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tCY C
tCH
Sequential Clock Cycle Time
25
10
10
5
30
12
12
5
40
15
15
6
50
18
18
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Pulse HIGH
tCL
Clock Pulse LOW
tES
Count Enable and Address Pointer Set-up Time
Count Enable and Address Pointer Hold Time
Output Enable to Data Valid
Output Enable Low-Z Time(2)
Output Enable High-Z Time(2)
Clock to Valid Data
tEH
2
2
2
2
____
____
____
____
tSOE
tOLZ
tOHZ
tCD
8
10
15
20
____
____
____
____
2
2
2
2
____
____
____
____
9
11
25
15
35
15
45
____
____
____
____
20
Clock High-Z Time(2)
12
14
17
20
____
____
____
____
tCKHZ
tCKLZ
tEB
Clock Low-Z Time(2)
3
3
3
3
____
____
____
____
____
____
____
____
Clock to EOB
13
15
18
23
ns
3099 tbl 22
Sequential Port: AC Electrical Characteristics
Over the Operating Temperature and Supply Voltage(1,3)
70824X20
Com'l Only
70824X25
Com'l Only
70824X35
Com'l &
Military
70824X45
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tCY C
tFS
Sequential Clock Cycle Time
25
13
5
30
15
5
40
20
6
50
20
6
ns
ns
ns
ns
ns
Flow Restart Time
tWS
tWH
tDS
Chip Select and Read/Write Set-up Time
Chip Select and Read/Write Hold Time
Input Data Set-up Time
2
2
2
2
5
5
6
6
tDH
Input Data Hold Time
2
2
2
2
ns
3099 tbl 23
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. Transition measured at 0mV from steady state. This parameter is guaranteed with the AC Output Test Load (Figure 1) by device characterization, but is not
production tested.
3. Industrial temperature: for specific speeds, packages and powers contact your sales office.
14
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Sequential Port: AC Electrical Characteristics
Over the Operating Temperature and Supply Voltage(1,2)
70824X20
Com'l Only
70824X25
Com'l Only
70824X35
Com'l &
Military
70824X45
Com'l &
Military
Symbol
WRITE CYCLE
tRS PW
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
Reset Pulse Width
13
10
10
15
15
10
10
20
20
10
10
25
20
10
10
25
ns
ns
ns
tWERS
Write Enable HIGH to Reset HIGH
Reset HIGH to Write Enable LOW
Reset HIGH to Flag Valid
tRSRC
tRS FV
ns
3099 tbl 24
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Sequential Port: Write, Pointer Load Non-Incrementing Read
tCYC
tCH
tCL
SCLK
tEH
tES
(2)
(3)
CNTEN
SLD
tEH
tES
(1)
tDS
A0
tDH
HIGH IMPEDANCE
Dx
SI/OIN
tWS
tWS
tWS
tWH
tWH
tWH
tWH
SR/
W
tWS
SCE
SOE
tCSZ
tCD
tCKHZ
tSOE
tOLZ
tOHZ
D0
D0
D0
SI/OOUT
3099 drw 17
tCKLZ
NOTES:
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
6.42
15
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Sequential Port: Write, Pointer Load, Burst Read
tCYC
tCH
tCL
SCLK
tEH
tES
(3)
(2)
CNTEN
tEH
tES
(1)
SLD
tDS
tDS
A0
tDH
tDH
HIGH IMPEDANCE
D2
SI/OIN
Dx
tWS
tWS
tWH
tWH
tWH
SR/W
SCE
tWS tWH
tWS
tSD
tSOP
SOE
tOHZ
tOLZ
(2)
SI/OOUT
D0
D1
tCKLZ
3099 drw 18
NOTES:
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
Read STRT/EOB Flag Timing - Sequential Port
tCYC
tCH
tCL
SCLK
tEH
tES
(4)
(2)
CNTEN
tES
tEH
(1)
SSTRT1/2
tDS
tDH
HIGH IMPEDANCE
SI/OIN
D3
Dx
tWS
tWS
tWH
tWH
SR/
W
tWS
tWS
tWH
tWH
(3)
SCE
SOE
tCD
tSOE
tOLZ
tOHZ
(2)
(5)
SI/OOUT
D0
D1
D2
tCKLZ
EOB1/2
tEB
3099 drw19
NOTES: (Also used in Figure "Read STRT/EOB Flag Timing")
1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. SOE will control the output and should be HIGH on power-up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within that
cycle. If SCE = VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus
contention and permit a write on this cycle.
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
16
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Waveform of Write Cycles: Sequential Port
tCYC
tCH
tCL
SCLK
tEH
tEH
(4)
tES
tES
(3)
CNTEN
SLD
tES
tEH
(1)
tDS
tDS
tDS
tDH
tDH
tDH
HIGH IMPEDANCE
Dx
A0
D1
SI/OIN
D0
tWS
tWS
tWH
tWH
tWH
tWH
(4)
SR/W
tWS
tWS
SCE
tCKHZ
tCD
(5)
SOE
tOHZ
HIGH IMPEDANCE
SI/OOUT
D0
3099 drw 20
tCKLZ
Waveform of Burst Write Cycles: Sequential Port
tCYC
tCH
tCL
SCLK
tEH
tES
(3)
CNTEN
(2)
tEH
tES
(1)
SLD
tDS
tDS
A0
tDH
tDH
SI/OIN
Dx
D0
D1
D2
tWS
tWS
tWH
tWH
tWH
tWH
SR/
W
(5)
tWS
tWS
SCE
SOE
(5)
tCKLZ
tCD
HIGH IMPEDANCE
SI/OOUT
D2
3099 drw 21
NOTES:
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incrementing on cycle immediately following SLD even if CNTEN is LOW.
4. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
5. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
6.42
17
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Waveform of Write Cycles: Sequential Port (STRT/EOB Flag Timing)
tCH
tCL
SCLK
tEH
tES
(2)
(4)
CNTEN
tEH
tES
(1)
SSTRT1/2
tDS
tDH
HIGH IMPEDANCE
SI/OIN
D0
D1
D3
Dx
D2
tWS
tWS
tWH
tWH
tWH
tWH
(5)
SR/W
SCE
SOE
tWS
tWS
(3)
(6)
tCKLZ
tCD
HIGH IMPEDANCE
SI/OOUT
D3
EOB1/2
tEB
3099 drw 22
NOTES: (Also used in Figure "Read STRT/EOB Flag Timing")
1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. SOE will control the output and should be HIGH on power-up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within that
cycle. If SCE = VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus
contention and permit a write on this cycle.
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
18
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Sequential Counter Enable Cycle After Reset, Write Cycle(1,4,6)
SCLK
RST
(2)
CNTEN
D0
D1
D2
D3
D4
SI/OIN
3099 drw 23
Sequential Counter Enable Cycle After Reset, Read Cycle(1,4)
SCLK
RST
(3)
SR/W
(5)
CNTEN
D0(5)
D3
D1
D2
SI/OOUT
3099 drw 24
NOTES:
1. 'D0' represents data input for Address = 0, 'D1' represents data input for Address = 1, etc.
2. If CNTEN = VIL then 'D1' would be written into 'A1' at this point.
3. Data output is available at a tCD after the SR/W = VIH is clocked. The RST sets SR/W = LOW internally and therefore disables the output until the next clock.
4. SCE = VIL throughout all cycles.
5. If CNTEN=VIL then 'D1' would be clocked out (read) at this point.
6. SR/W = VIL.
6.42
19
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Random Access Port - Reset Timing
tRSPW
RST
tRSRC
R/W, SR/W CMD
or (UB + LB)(4)
tWERS
tRSFV
EOB(1 or 2)
Flag Valid
3099 drw 25
Random Access Port Restart Timing of Sequential Port(1)
0.5 x tCYC
tFS
SCLK
R/W
(2)
2-5ns
6-7ns
CLR(3)
Block
3099 drw 26
(Internal Signal)
NOTES:
1. The sequential port is in the STOP mode and is being restarted from the random port by the Bit 4 Counter Release (see Case 5).
2. "0" is written to Bit 4 from the random port at address [A2 - A0] = 100, when CMD = VIL and CE = VIH. The device is in the Buffer Command Mode (see Case 5).
3. CLR is an internal signal only and is shown for reference only.
4. Sequential port must also prohibit SR/W or SCE from being LOW for tWERS and tRSRC periods or SCLK must not toggle from LOW-to-HIGH until after tRSRC.
20
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
OrderingInformation
IDT 70824
X
XX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I(1)
B
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Military (–55°C to +125°C)
Compliant to MIL-PRF-38535 QML
84-pin PGA (G84-3)
80-pin TQFP (PN80-1)
G
PF
Commercial Only
20
25
35
45
Commercial Only
Speed in nanoseconds
Commercial & Military
Commercial & Military
Standard Power
Low Power
S
L
70824 64K (4K x 16) Sequential Access Random Access
Memory
3099 drw 27
NOTE:
1. Industrial temperature range is available on selected TQFP packages in standard power.
For specific speeds, packages and powers contact your sales office.
DatasheetDocumentHistory
3/8/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Page2Addedadditionalnotestopinconfigurations
Changeddrawingformat
6/4/99:
11/10/99:
4/18/00:
Replaced IDT logo
Page3Added"Outputs"inSequentialpindescriptiontable
Changed±200mVto0mVinnotes
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6.42
21
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