IDT709149S8PF [IDT]
HIGH-SPEED 36K (4K x 9-BIT) SYNCHRONOUS PIPELINED DUAL-PORT SRAM; 高速36K （ 4K ×9位）同步流水式双端口SRAM
| 型号： | IDT709149S8PF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 36K (4K x 9-BIT) SYNCHRONOUS PIPELINED DUAL-PORT SRAM |
| 文件： | 总10页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT709149S
HIGH-SPEED 36K (4K x 9-BIT)
SYNCHRONOUS PIPELINED
DUAL-PORT SRAM
Features
◆
◆
13ns cycle time, 76MHz operation in pipeline mode
Architecture based on Dual-Port SRAM cells
Allows full simultaneous access from both ports
High-speed clock-to-data output times
Commercial: 8/10/12ns (max.)
Low-power operation
Self-timed write allows for fast cycle times
TTL-compatible, singles 5V (±10%) power supply
Clock Enable feature
Guaranteed data output hold times
Industrial temperature range (40°C to +85°C) is available
for selected speeds.
◆
◆
◆
◆
◆
◆
IDT709149S
Active: 1500mW (typ.)
Standby: 75mW (typ.)
4K X 9 bits
Synchronous operation
4ns setup to clock, 1ns hold on all control, data, and
address inputs
◆
◆
Description
The IDT709149 is a high-speed 4K x 9 bit synchronous Dual-Port
SRAM.ThememoryarrayisbasedonDual-Portmemorycells toallow
simultaneous access from both ports. Registers on control, data, and
address inputs provide low set-up and hold times. The timing latitude
provided by this approach will allow systems to be designed with very
Data input, address, and control registers
Fast 8ns clock to data out
Functional Block Diagram
I/O0-8L
I/O0-8R
/PIPEDR
WRITE
WRITE
MEMORY
LOGIC
LOGIC
FT
ARRAY
0/1
0
SENSE
AMPS
SENSE
AMPS
1
DECODERDECODER
REG
en
REG
en
OEL
OER
CLKL
CLKR
CLKENL
CLKENR
Self-
Self-
timed
Write
Logic
timed
Write
Logic
R/WR
CER
WL
R/
REG
REG
CEL
A0L-A11L A0R-A11R
3494 drw 01
SEPTEMBER 1999
1
DSC-3494/4
©1999 Integrated Device Technology, Inc.
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
short cycle times. This device has been optimized for applications
having unidirectional data flow or bi-directional data flow in bursts, by Dual-Ports typically operate on only 800mW of power at maximum
utilizing input data registers. high-speed clock-to-data output times as fast as 8ns. An automatic
FabricatedusingIDTsCMOShigh-performancetechnology,these
The IDT709149 utilizes a 9-bit wide data path to allow for parity at power down feature, controlled by CE, permits the on-chip circuitry
the user's option. This feature is especially useful in data communica- of each port to enter a very low standby power mode.
tion applications where it is necessary to use a parity bit for transmis-
sion/reception error checking.
The IDT709149 is packaged in an 80-pin TQFP.
Pin Configurations(1,2,3)
Reference
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
N/C
A6L
A7L
A8L
A9L
A10L
1
2
60
N/C
59
A7R
3
58
A8R
A9R
4
57
5
56
10R
A
6
55
A11R
N/C
7
54
11L
A
IDT709149PF
PN80-1
,
8
53
52
51
50
49
48
47
46
45
44
43
42
41
N/C
OEL
VCC
VCC
OER
(4)
9
FT
R
/PIPED
10
11
12
13
14
15
16
17
18
19
20
GND
80-Pin TQFP
GND
(5)
Top View
WL
R/
WR
R/
N/C
N/C
N/C
N/C
CEL
CER
GND
I/O8R
GND
I/O8L
I/O7L
I/O6L
N/C
7R
I/O
I/O6R
N/C
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
3494 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All ground pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4, This package code is used to reference the package diagram.
5. This text does not indicate the orientaion of the actual part-marking.
6.42
2
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Maximum OperatingTemperature
and Supply Voltage(1,2)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
GND
Vcc
(2)
Ambient Temperature
0OC to +70OC
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
+
5.0V 10%
Commercial
Industrial
0V
0V
(2)
-40OC to +85OC
+
5.0V 10%
VTERM
TBIAS
Terminal Voltage
-0.5 to VCC
-55 to +125
V
Temperature
Under Bias
oC
3494 tbl 02
NOTES:
1. This is the parameter TA.
oC
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Storage
-55 to +125
50
TSTG
IOUT
NOTES:
Temperature
DC Output Current
mA
3494 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating
Conditions
Symbol
Parameter
Min.
Typ.
Max. Unit
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
VCC
Supply Voltage
4.5
5.0
5.5
0
V
V
V
GND
VIH
Ground
0
0
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
-0.5(1)
V
____
VIL
3494 tbl 03
Capacitance (TA = +25°C, f = 1.0MHz)
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
Symbol
Parameter
Conditions
Max. Unit
CIN
Input Capacitance
Output Capacitance
VIN = 3dV
8
9
pF
COUT
VOUT = 3dV
pF
3494 tbl 04
NOTES:
1. These parameters are determined by device characterization, but are not produc-
tion tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
709149S
Symbol
|ILI|
Parameter
Input Leakage Current(1)
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
Min.
Max.
Unit
µA
µA
V
___
10
10
___
___
|ILO|
Output Leakage Current
Output Low Voltage
Output High Voltage
VOUT = 0V to VCC
IOL = +4mA
VOL
0.4
___
VOH
IOH = -4mA
2.4
V
3494 tbl 05
NOTE:
1. At VCC < 2.0V, input leakages are undefined
6.342
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(4,5) (VCC = 5V ± 10%)
709149S8
Com'l Only
709149S10
Com'l Only
709149S12
Com'l Only
Symbol
Parameter
Test Condition
R = VIL,
CE
Version
COM'L
IND
Typ.
Max.
Typ.
Max.
Typ.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
ICC
Dynamic Operating
Current
(Both Ports Active)
mA
320
310
300
and
CEL
Outputs Open
(1)
____
____
____
f = fMAX
ISB1
ISB2
ISB3
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
150
150
140
mA
mA
mA
CEL and CER = VIH
(1)
f = fMAX
____
____
____
(3)
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
230
220
210
CE"A " = VIL and CE"B" = VIH
Active Port Outputs Open,
(1)
____
____
____
f=fMAX
____
____
____
____
____
____
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
CEL and
COM'L
IND
15
15
15
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(2)
____
____
____
____
____
____
____
____
____
ISB4
Full Standby Current
(One Port - All
CMOS Level Inputs)
mA
COM'L
IND
220
210
200
CE"A " < 0.2V and
CE"B " > VCC - 0.2V(3)
____
____
____
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Open,
(1)
f = fMAX
3494 tbl 06
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCLK, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC = 150mA (Typ).
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1,2 and 3
8
7
6
9pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
3494 tbl 07
5V
5
4
3
5V
∆tCD
(Typical, ns)
893
Ω
893
Ω
2
1
DATAOUT
DATAOUT
30pF
5pF*
347
Ω
347
Ω
0
,
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
,
-1
3494 drw 04
3494 drw 03
3494 drw 05
Figure 1. AC Output Test load.
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
4
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(4)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
709149S8
Com'l Only
709149S10
Com'l Only
709124S12
Com'l Only
Symbol
tCYC1
Parameter
Clock Cycle Time (Flow-Through)(3)
Clock Cycle Time (Pipelined)(3)
Clock High Time (Flow-Through)(3)
Clock Low Time (Flow-Through)(3)
Clock High Time (Pipelined)(3)
Clock Low Time (Pipelined)(3)
Min.
16
13
6
Max.
Min.
20
15
7
Max.
Min.
20
16
8
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
CYC2
t
tCH1
tCL1
6
7
8
CH2
t
6
6
6
tCL2
tCD1
tCD2
tS
6
6
6
Clock to Data Valid (Flow-Through)(3)
Clock to Data Valid (Pipelined)(3)
Registered Signal Set-up Time
Registered Signal Hold Time
12
15
20
____
____
____
____
____
____
8
10
12
____
____
____
4
1
1
4
1
1
5
1
1
____
____
____
____
____
____
____
____
____
tH
tDC
Data Output Hold After Clock High
Clock High to Output Low-Z(1,2)
Clock High to Output High-Z(1,2)
Output Enable to Output Valid
tCKLZ
tCKHZ
tOE
2
2
2
____
____
____
7
7
9
____
____
____
8
8
10
Output Enable to Output Low-Z(1,2)
Output Disable to Output High-Z(1,2)
Clock Enable, Disable Set-Up Time
Clock Enable, Disable Hold Time
Write Port Clock High to Read Data Delay
0
0
0
____
____
____
tOLZ
tOHZ
tSCK
tHCK
tCWDD
____
____
____
7
7
9
____
____
____
4
4
5
____
____
____
1
1
1
____
____
____
25
30
35
ns
3494 tbl 08
NOTES:
1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The Pipelined output parameters (tCYC2, tCD2) always apply to the Left Port. The Right Port uses the Pipelined tCYC2 and tCD2 when FT/PIPEDR = VIH and the Flow-
Through parameters (tCYC1, tCD1) when FT/PIPEDR = VIL.
4. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.542
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Flow-Through Output on Right Port
(FT/PipedR = VIL)
tCYC1
tCH1
tCL1
CLK
CLKEN
CE
tSCK
tHCK
tSCK
tS
tH
R/W
ADDRESS
DATAOUT
An
An + 1
An + 2
An + 3
(1)
tDC
tCKHZ
tCD1
Qn
Qn + 1
Qn + 1
(1)
tCKLZ
(1)
(1)
tOHZ
tOLZ
tOE
OE
3494 drw 06
Timing Waveform of Left Port Write to Flow-Through Right Port Read
(FT/PipedR = VIL)(2,3)
CLK "L"
R/W "L"
NO
ADDR "L"
DATA IN "L"
CLK "R"
MATCH
VALID
MATCH
VALID
tCCS
R/W "R"
NO
MATCH
ADDR "R"
DATA OUT "R"
NOTES:
MATCH
tCWDD
tCD1
VALID
VALID
tDC
3494 drw 07
1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CEL = CER = VIL, CLKENL = CLKENR = VIL
3. OE = VIL for the reading port, port 'R'.
6.42
6
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(Left Port; Right Port when FT/PipedR = VIH)(3)
tCYC2
tCH2
tCL2
CLK
tS
tH
tH
tH
tS
CE
R/W
tS
An
An + 1
An + 2
Qn
An + 3
ADDRESS
(1 Latency)
tDC
tCD2
tCD2
DATAOUT
Qn + 1
Qn + 2
(1)
tCKLZ
(1)
(1)
tOHZ
tOLZ
OE (2)
tOE
3494 drw 08
NOTES:
1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. CLKENL and CLKENR = VIL.
6.742
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)
tCYC2
tCH2
tCL2
CLK
CE
tS
tS
tH
tS
tH
R/W
tH
tH
An + 4
An + 3
An
tS
An +1
An + 2
An + 2
tS
Dn + 2
ADDRESS
tH
DATAIN
(1)
(1)
tCD2
tCD2
tCKLZ
(2)
tCKHZ
(3)
Qn + 3
Qn
DATAOUT
READ
NOP
WRITE
READ
3494 drw 09
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)
tCYC2
tCH2
tCL2
CLK
tS
tH
CE
tS tH
An + 2
W
R/
tS
tS
tH
tH
An + 4
An
An +1
An + 3
Dn + 3
An + 5
ADDRESS
DATAIN
tS
tH
Dn + 2
(1)
tCD2
tCD2
tCKLZ
(2)
Qn
Qn + 4
DATAOUT
(1)
tOHZ
OE
WRITE
READ
READ
3494 drw 10
NOTES:
1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
8
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Functional Description
possible realized cycle times. Clock enable inputs are provided to stall
the operation of the address and data input registers without introduc-
ing clock skew for very fast interleaved memory applications.
A HIGH on the CE input for one clock cycle will power down the
internal circuitry to reduce static power consumption.
TheIDT709149providesatruesynchronousDual-PortStaticRAM
interface. Registered inputs provide very short set-up and hold times
onaddress, data, andallcriticalcontrolinputs. Allinternalregistersare
clockedontherisingedgeoftheclock signal. Anasynchronousoutput
enable is provided to ease asynchronous bus interfacing.
When piplelined mode is enabled, two cycles are required with
CE LOW to reactivate the outputs.
The internal write pulse width is dependent only on the low to high
transitions of the clock signal to initiate a write allowing the shortest
Truth Table I: Read/Write Control(1)
Inputs
Outputs
Synchronous(3)
Asynchronous
Mode
CLK
↑
R/W
X
I/O0-8
High-Z
CE
H
OE
X
DeselectedPower Down
L
L
X
DATAIN
DATAOUT
High-Z
Selected and Write Enable
↑
L
H
L
Read Selected and Data Output Enabled Read (1 Latency)
Data I/O Disabled
↑
X
X
H
↑
3494 tbl 09
Truth Table II: Clock Enable Function Table(1)
Inputs
Register Inputs
Register Outputs(4)
ADDR DATAOUT
CLK(3)
ADDR
DATAIN
CLKEN(2)
Operating Mode
Load "1"
L
L
H
L
H
L
H
L
H
L
↑
↑
↑
X
Load "0"
Hold (do nothing)
H
H
X
X
X
X
NC
NC
NC
NC
3494 tbl 10
NOTES:
1. 'H' = HIGH voltage level steady state, 'h' = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'L' = LOW voltage level steady state 'l' = LOW voltage
level one set-up time prior to the LOW-to-HIGH clock transition, 'X' = Don't care, 'NC' = No change
2. CLKEN = VIL must be clocked in during Power-Up.
3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/W and CE are LOW, a write cycle is initiated on the LOW-
to-HIGH transition of the CLK. Termination of a write cycle is done on the next LOW-to-HIGH transistion of the CLK.
4. The register outputs are internal signals from the register inputs being clocked in or disabled by CLKEN.
6.942
IDT709149S
High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT
XXXX
A
999
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
PF
Commercial (0°C to +70°C)
80-pin TQFP (PN80-1)
Commercial Only
Speed in nanoseconds
Commercial Only
Commercial Only
8
10
12
S
Standard Power
709149 36K (4K x 9-Bit) Synchronous
Pipelined Dual-Port RAM
3494 drw 11
NOTE:
1. Industrial temperature range is available.
For specific speeds, packages and poewrs contact your sales office.
Datasheet Document History
3/8/99:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
Changed drawing format
6/3/99:
9/1/99:
Removed Preliminary
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800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
831-754-4613
DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
10
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