IDT709269S12PF9 [IDT]
Dual-Port SRAM, 16KX16, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100;
| 型号： | IDT709269S12PF9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 16KX16, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
IDT709269S/L
HIGH-SPEED 16K x 16
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features:
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial:9/12/15ns (max.)
– Industrial:12ns (max.)
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data, and
addressinputs
◆
◆
◆
Low-power operation
– Data input, address, and control registers
– IDT709269S
–
Fast 9ns clock to data out in the Pipelined output mode
Active: 950mW (typ.)
– Self-timedwriteallowsfastcycletime
Standby: 5mW (typ.)
– IDT709269L
– 15ns cycle time, 66MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
◆
Active: 950mW (typ.)
Standby: 1mW (typ.)
Flow-through or Pipelined output mode on either port via
the FT/PIPE pin
Counter enable and reset features
◆
◆
◆
◆
◆
Available in a 100-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/W
L
R/W
UBR
R
UBL
CE0L
CE1L
CE0R
CE1R
1
0
1
0
0/1
0/1
LB
R
LB
L
OER
OEL
0a 1a
1b 0b
1a 0a
0b 1b
b
0/1
0/1
FT/PIPE
L
b
a
a
FT/PIPE
R
I/O8L-I/O15L
I/O0L-I/O7L
I/O8R-I/O15R
I/O0R-I/O7R
I/O
Control
I/O
Control
A
13R
A
13L
Counter/
Address
Reg.
Counter/
Address
Reg.
MEMORY
ARRAY
A
C0LRK
R
R
A
0L
L
L
L
CLK
ADS
CNTEN
CNTRST
ADS
CNTEN
R
L
CNTRST
R
3493 drw 01
JANUARY 2002
1
DSC-3493/9
©2002IntegratedDeviceTechnology,Inc.
IDT709269S/L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM
Description:
TheIDT709269isahigh-speed16Kx16bitsynchronouspipelined
With an input data register, the IDT709269 has been optimized for
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to applications having unidirectional or bidirectional data flow in bursts.
allow simultaneous access of any address from both ports. Registers Anautomaticpowerdownfeature, controlledbyCE0andCE1, permits
on control, data, and address inputs provide minimal setup and hold the on-chip circuitry of each port to enter a very low standby power
times. The timing latitude provided by this approach allows systems mode. Fabricated using IDT’s CMOS high-performance technology,
to be designed with very short cycle times.
these devices typically operate on only 950mW of power.
Pin Configuration(1,2,3)
01/02/02
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A
A
A
A
A
9R
1
A
9L
75
74
73
10R
11R
12R
13R
2
A10L
A11L
A12L
A13L
3
4
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
5
6
NC
NC
NC
NC
LB
UB
CE0R
CE1R
CNTRST
NC
NC
NC
NC
LB
UB
7
8
9
R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
L
IDT709269PF
PN100-1
R
(4)
L
CE0L
CE1L
CNTRST
Vcc
R/W
OE
FT/PIPE
,
100-PIN TQFP
(5)
R
L
TOP VIEW
GND
R/W
OE
FT/PIPE
R
L
R
L
L
R
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3493 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
6.42
IDT709269S/L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM
Pin Names
Left Port
Right Port
CE0R, CE1R
R/W
OE
Names
Chip Enables
CE0L, CE1L
R/W
OE
L
R
Read/Write Enable
Output Enable
Address
L
R
A
0L - A13L
I/O0L - I/O15L
CLK
UB
LB
ADS
CNTEN
CNTRST
FT/PIPE
A
0R - A13R
I/O0R - I/O15R
CLK
UB
LB
ADS
CNTEN
CNTRST
FT/PIPE
Data Input/Output
Clock
L
R
Upper Byte Select
Lower Byte Select
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power
L
R
L
R
L
R
L
R
L
R
L
R
VCC
GND
Ground
3493 tbl 01
Truth Table I—Read/Write and Enable Control(1,2,3)
Upper Byte
I/O8-15
Lower Byte
I/O0-7
CLK
↑
CE
1
Mode
OE
X
X
X
X
X
X
L
CE
0
UB
X
X
H
L
LB
X
X
H
H
L
R/W
H
X
L
L
L
L
L
L
L
L
X
L
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Deselected—Power Down
Deselected—Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
X
X
L
↑
H
H
H
H
H
H
H
H
↑
DIN
↑
H
L
L
High-Z
DIN
↑
L
L
DIN
DIN
↑
L
H
L
H
H
H
X
DOUT
High-Z
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
↑
L
H
L
High-Z
DOUT
↑
L
L
DOUT
DOUT
↑
H
X
L
L
High-Z
High-Z
Outputs Disabled
3493 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
6.342
IDT709269S/L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM
TRUTHTABLEII—AddressCounterControl(1,2)
Previous
Address
Addr
Used
(3)
Address
CLK
↑
I/O
MODE
ADS CNTEN
CNTRST
(4)
X
An
An
X
X
X
0
An
X
X
X
H
L
D
I/O(0)
I/O (n) External Address Used
I/O(p) External Address Blocked—Counter disabled (Ap reused)
DI/O(p+1) Counter Enabled—Internal Address generation
Counter Reset to Address 0
(4)
↑
L
H
H
H
H
H
D
Ap
Ap
Ap
D
↑
(5)
Ap + 1
L
↑
3493 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
Recommended Operating
Recommended DC Operating
Conditions
TemperatureandSupplyVoltage
Symbol
Parameter
Supply Voltage
GND Ground
Min.
Typ. Max. Unit
Grade
Ambient
GND
Vcc
Temperature(1)
VCC
4.5
5.0
5.5
0
V
V
V
Commercial
0OC to +70OC
0V
0V
5.0V
5.0V
+
+
10%
0
0
Industrial
-40OC to +85OC
10%
____
V
IH
Input High Voltage
Input Low Voltage
2.2
6.0(1)
0.8
3493 tbl 04
____
NOTES:
VIL
-0.5(2)
V
1. This is the parameter TA. This is the "instant on" case temperature.
3493 tbl 05
NOTES:
1. VTERM must not exceed VCC + 10%.
2. VIL > -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings(1)
Capacitance (TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
9
pF
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
(3)
OUT
C
V
10
pF
3493 tbl 07
NOTES:
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
T
BIAS
1. These parameters are determined by device characterization, but are not produc-
tion tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
Storage
Temperature
TSTG
DC Output
Current
mA
IOUT
3493 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operationofthe device atthese oranyotherconditions above those indicatedinthe
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
4
6.42
IDT709269S/L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
709269S/L
Symbol
|ILI
|ILO
Parameter
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
Min.
Max.
10
Unit
µA
µA
V
(1)
___
___
___
|
Input Leakage Current
|
Output Leakage Current
Output Low Voltage
Output High Voltage
10
CE
OL = +4mA
OH = -4mA
0
= VIH or CE
1
= VIL, VOUT = 0V to VCC
VOL
I
0.4
___
VOH
I
2.4
V
3493 tbl 08
NOTE:
1. At VCC < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(6) (VCC = 5V ± 10%)
709269X9
709269X12
709269X15
Com'l Only
Com'l Only
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
S
L
210
210
390
350
200
200
345
305
190
190
325
285
mA
CEL
and CER= VIL
Outputs Disabled
(1)
f = fMAX
____
____
____
____
____
____
____
____
IND
S
L
200
200
380
340
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
50
50
135
115
50
50
110
90
50
50
110
90
mA
mA
CE
L
= CER = VIH
(1)
f = fMAX
____
____
____
____
____
____
____
____
S
L
50
50
125
105
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
140
140
270
240
130
130
230
200
120
120
220
190
CE"A" = VIL and
(3)
CE"B" = VIH
Active Port Outputs
Disabled,
____
____
____
____
____
____
____
____
S
L
130
130
245
215
(3)
f=fMAX
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
CE > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(2)
R
and
COM'L
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
mA
mA
L
V
V
____
____
____
____
____
____
____
____
S
L
1.0
0.2
15
5
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
IND
S
L
130
130
245
225
120
120
205
185
110
110
195
175
CE"A" < 0.2V and
(5)
CE"B" > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, Active Port
Outputs Disabled, f = fMAX
V
V
____
____
____
____
____
____
____
____
S
L
120
120
220
200
(1)
3493 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VCC = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part number indicates power rating (S or L).
6.542
IDT709269S/L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
3ns
1.5V
1.5V
Figures 1,2 and 3
3493 tbl 10
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
30pF
347Ω
5pF*
347Ω
,
3493 drw 03
3493 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
Figure 1. AC Output Test load.
8
7
6
5
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
tCD
tCD
(Typical, ns)
1
,
4
3
2
1
2
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
,
-1
3493 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6
6.42
IDT709269S/L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VCC = 5V ± 10%, TA = 0°C to +70°C)
709269X9
Com'l Only
709269X12
Com'l
709269X15
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
30
20
12
12
8
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
CYC1
CYC2
CH1
CL1
CH2
CL2
Clock Cycle Time (Flow-Through)
25
15
12
12
6
35
25
12
12
10
(2)
t
Clock Cycle Time (Pipelined)
t
Clock High Time (Flow-Through)(2)
Clock Low Time (Flow-Through)(2)
t
(2)
t
Clock High Time (Pipelined)
t
Clock Low Time (Pipelined)(2)
Clock Rise Time
6
8
10
____
____
____
tR
3
3
3
____
____
____
tF
Clock Fall Time
3
3
3
____
____
____
t
SA
HA
SC
HC
SB
HB
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRST
HRST
OE
OLZ
OHZ
CD1
CD2
DC
CKHZ
CKLZ
Address Setup Time
Address Hold Time
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
t
t
t
t
t
t
R/W Hold Time
t
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
t
t
t
ADS Hold Time
t
CNTEN Setup Time
CNTEN Hold Time
t
____
____
____
____
____
____
t
CNTRST Setup Time
CNTRST Hold Time
Output Enable to Data Valid
t
1
1
1
____
____
____
t
12
12
15
(1)
____
____
____
t
Output Enable to Output Low-Z
2
2
2
(1)
t
Output Enable to Output High-Z
1
7
1
7
1
7
(2)
____
____
____
t
Clock to Data Valid (Flow-Through)
20
25
30
(2)
____
____
____
t
Clock to Data Valid (Pipelined)
9
12
15
____
____
____
t
Data Output Hold After Clock High
2
2
2
2
2
2
2
2
2
(1)
t
Clock High to Output High-Z
9
9
9
(1)
____
____
____
t
Clock High to Output Low-Z
Port-to-Port Delay
____
____
____
____
____
____
t
CWDD
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
40
15
40
15
50
20
ns
tCCS
ns
3493 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPEX.
4. 'X' in part number indicates power rating (S or L).
6.742
IDT709269S/L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM
Timing Waveform of Read Cycle for
Flow-through Output on Either Port (FT/PIPEX = VIL)(3)
tCYC1
tCH1
tCL1
CLK
CE
0
tSC
tHC
tSC
tHC
(4)
CE1
tSB
tHB
UB, LB
R/W
tHB
tSB
tHW
tSW
tSA
tHA
(5)
ADDRESS
An
An + 1
An + 2
An + 3
(1)
tDC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2
DATAOUT
(1)
(1)
tDC
tCKLZ
(1)
tOHZ
tOLZ
OE(2)
t
OE
3493 drw 06
Timing Waveform of Read Cycle for Pipelined Operation on Either Port
(FT/PIPEX = VIH)(3)
t
CYC2
tCH2
t
CL2
CLK
CE
0
t
SC
tHC
t
SC
SB
t
HC
HB
(4)
CE1
t
SB
tHB
t
t
(6)
UB, LB
R/W
tHW
tSW
tSA
tHA
(5)
ADDRESS
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
Qn + 2 (6)
DATAOUT
Qn + 1
(1)
tCKLZ
(1)
(1)
t
OHZ
tOLZ
OE(2)
tOE
3493 drw 07
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-impedance state).
8
6.42
IDT709269S/L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM
Timing Waveform of a Multi-device Pipelined Read(1,2)
t
CYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A
6
A
5
A
4
A
3
A
2
A
0
A1
tSC
tHC
t
SC
t
HC
DC
(3)
CKHZ
tCD2
tCD2
t
t
CD2
Q0
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
(3)
(3)
t
t
CKLZ
t
DC
tCKHZ
tSA
tHA
A6
A5
A4
A3
A2
A
0
A1
tSC
t
HC
CE0(B2)
tSC
tHC
(3)
CKHZ
tCD2
t
tCD2
DATAOUT(B2)
Q4
Q2
(3)
(3)
tCKLZ
tCKLZ
3493 drw 08
Timing Waveform of Left Port Write to Flow-through Right Port Read(4,5)
CLK
L
L
L
t
SW
tHW
R/W
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
ADDRESS
t
t
DATAIN L
(6)
tCCS
CLK
R/W
R
R
R
tCD1
t
HW
t
SW
t
HA
tSA
NO
MATCH
ADDRESS
MATCH
(6)
t
CD1
tCWDD
DATAOUT R
VALID
VALID
tDC
t
DC
3493 drw 09
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one 709269 for this waveform, and are set up for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2) R/W, CNTEN, and CNTRST = VIH.
,
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
6.942
IDT709269S/L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
t
SC
tHC
CE1
tSB
tHB
UB, LB
R/W
t
SW tHW
tSW tHW
ADDRESS(4)
An + 3
An + 4
An
An +1
An + 2
An + 2
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
(1)
tCD2
(1)
t
CD2
(2)
t
CKHZ
tCKLZ
Qn + 3
Qn
DATAOUT
NOP(5)
READ
WRITE
READ
3493 drw 10
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
t
CYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
t
SW tHW
(4)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
(1)
CKLZ
tCD2
t
CD2
t
(2)
Qn
Qn + 4
DATAOUT
(1)
t
OHZ
OE
READ
WRITE
READ
3493 drw 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
10
6.42
IDT709269S/L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM
Timing Waveform of Flow-through Read-to-Write-to-Read (OE = VIL)(3)
t
CYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
t
SW tHW
(4)
An + 4
An
An + 3
An +1
An + 2
Qn + 1
An + 2
ADDRESS
tSA
tHA
t
SD tHD
DATAIN
Dn + 2
tCD1
tCD1
tCD1
t
CD1
(2)
Qn + 3
Qn
READ
DATAOUT
(1)
(1)
tCKLZ
t
DC
tDC
t
CKHZ
NOP(5)
READ
WRITE
3493 drw 12
TimingWaveformof Flow-throughRead-to-Write-to-Read(OEControlled)(3)
tCYC1
tCH1
tCL1
CLK
CE
0
1
t
SC
tHC
CE
t
SB
tHB
UB, LB
R/W
tSW tHW
t
SW tHW
(4)
An + 5
An
tHA
An +1
An + 2
An + 3
Dn + 3
An + 4
ADDRESS
tSA
t
SD tHD
DATAIN
Dn + 2
tOE
tDC
tCD1
t
CD1
tCD1
(2)
Qn + 4
Qn
DATAOUT
(1)
CKLZ
(1)
t
tOHZ
tDC
OE
READ
WRITE
READ
3493 drw 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
61.412
IDT709269S/L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
t
SAD tHAD
ADS
t
SAD tHAD
CNTEN
tSCN tHCN
tCD2
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 3
Qn + 1
Qn
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
3493 drw 14
Timing Waveform of Flow-through Read with Address Counter Advance(1)
t
CYC1
tCH1
tCL1
CLK
t
SA
tHA
An
ADDRESS
tSAD tHAD
ADS
t
SAD
tHAD
tSCN
tHCN
CNTEN
tCD1
Qn + 3(2)
Qx(2)
Qn
Qn + 4
Qn + 1
Qn + 2
DATAOUT
tDC
READ
READ
READ WITH COUNTER
COUNTER
HOLD
WITH
EXTERNAL
ADDRESS
COUNTER
3493 drw 15
NOTES:
1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output
remains constant for subsequent clocks.
12
6.42
IDT709269S/L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An + 4
An(7)
An + 2
An + 1
An + 3
t
SAD tHAD
ADS
CNTEN
t
SD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
3493 drw 16
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
t
CYC2
t
CH2
tCL2
CLK
t
SA
tHA
(4)
An + 2
An
An + 1
ADDRESS
INTERNAL(3)
ADDRESS
Ax(6)
0
An + 1
1
An
tSW tHW
R/W
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tSRST
tHRST
CNTRST
tSD
tHD
D0
DATAIN
(5)
Qn
Q1
Q0
DATAOUT
COUNTER (6)
RESET
WRITE
READ
ADDRESS 0
READ
READ
READ
ADDRESS 1
ADDRESS 0
ADDRESS n ADDRESS n+1
3493 drw 17
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
CE0, UB, LB = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR 0 will be accessed. Extra cycles are shown
here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written
to during this cycle.
61.432
IDT709269S/L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM
Depth and Width Expansion
FunctionalDescription
The IDT709269 features dual chip enables (refer to Truth Table I)
in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The 709269 can also be used in applications requiring expanded
width, as indicated in Figure 4. Since the banks are allocated at the
discretion of the user, the external controller can be set up to drive the
input signals for the various devices as required to allow for 32-bit
or wider applications.
TheIDT709269providesatruesynchronousDual-PortStaticRAM
interface. Registered inputs provide minimal set-up and hold times on
address,data,andallcriticalcontrolinputs.Allinternalregistersareclocked
ontherisingedgeoftheclock signal,however,theself-timedinternalwrite
pulseisindependentoftheLOWtoHIGHtransitionoftheclocksignal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory appli-
cations.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce static power consumption.
Multiple chip enables allow easier banking of multiple IDT709269's for
depth expansion configurations. When the Pipelined output mode is
enabled, two cycles are required with CE0 LOW and CE1 HIGH to re-
activate the outputs.
A14
IDT709269
IDT709269
CE0
CE0
CE1
CE1
VCC
VCC
Control Inputs
Control Inputs
IDT709269
IDT709269
CE1
CE1
,
CE
0
CE0
CNTRST
CLK
Control Inputs
Control Inputs
ADS
CNTEN
R/W
3493 drw 18
OE
LB, UB
Figure 4. Depth and Width Expansion with IDT709269
14
6.42
IDT709269S/L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM
Ordering Information
IDT XXXXX
A
99
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
100-pin TQFP (PN100-1)
Commercial Only
9
12
15
Commercial & Industrial
Commercial Only
Speed in nanoseconds
Standard Power
Low Power
S
L
709269 256K (16K x 16-Bit) Synchronous Dual-Port RAM
3493 drw 19
NOTES:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
Preliminary Datasheet:
"PRELIMINARY' datasheets contain descriptions for products that are in early release.
Datasheet Document History
1/12/99:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
Page 14 AddedDepth&WidthExpansionnote
Changeddrawingformat
6/7/99:
Page 4 Deleted note 6 for Table II
Replaced IDT logo
4/17/00:
AddedFT/PIPEtoleftport.
Changed±200mVto0mVinnotes
5/24/00:
Page 4 ChangedinformationinTruthTableII
Increasedstoragetemperatureparameter
ClarifiedTAparameter
Page 5 DCElectricalparameters–changedwordingfrom"open"to"disabled"
AddedIndustrialTemperatureRangesandremovedrelatednotes
Continued on page 16
61.452
IDT709269S/L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM
DatasheetDocumentHistory(cont'd)
01/02/02:
Page 2 Added date revision to pin configurations
Page 5& 7 Removedindustrialtempfor15ns speedfromDC&ACElectricalCharacteristics
Page 15 Removedindustrialtempfrom15nsinorderinginformation
Addedindustrialtempfootnote
Page 1 & 16 Replaced TM logo with ® logo
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
16
6.42
相关型号：
IDT709269S12PFGI
Dual-Port SRAM, 16KX16, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
IDT
IDT709269S15PF8
Dual-Port SRAM, 16KX16, 30ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
IDT
IDT709269S15PF9
Dual-Port SRAM, 16KX16, 30ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
IDT
IDT709269S15PFG
Dual-Port SRAM, 16KX16, 30ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
IDT
IDT709269S15PFG8
Dual-Port SRAM, 16KX16, 30ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
IDT
©2020 ICPDF网 联系我们和版权申明