IDT70927S30PF9_技术文档

HIGH-SPEED 32K x 16

SYNCHRONOUS

PRELIMINARY

IDT70927S/L

DUAL-PORT STATIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

Commercial: 20/25/30ns

Low-power operation

Full synchronous operation on both ports

4ns setup to clock and 1ns hold on all control, data,

and address inputs

Data input, address, and control registers

Fast 20ns clock to data out

◆

IDT70927S

Self-timed write allows fast cycle time

25ns cycle time, 40MHz operation

Active: 950mW (typ.)

Standby: 5mW (typ.)

IDT70927L

Active: 950mW (typ.)

Standby: 1mW (typ.)

Flow-Through output mode

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

◆

Separate upper-byte and lower-byte controls for

multiplexed bus and bus matching compatibility

TTL- compatible, single 5V (±10%) power supply

Industrial temperature range (40°C to +85°C) is available

for selected speeds

◆

Available in 108-pin Pin Grid Array (PGA) and 100 pin Thin

Quad Flatpack (TQFP) packages

Functional Block Diagram

R/W_R

UB_R

R/W_L

UB_L

CE_0R

CE0L

CE1R

CE1L

LBR

OER

LBL

OEL

I/O8R-I/O15R

I/O8L-I/O15L

I/O_0L-I/O_7L

I/O

Control

I/O

Control

I/O0R-I/O7R

A_14R

A14L

Counter/

Address

Reg.

Counter/

MEMORY

ARRAY

A0R

A0L

Address

CLKR

Reg.

CLK_L

ADSR

ADSL

CNTENL

CNTRSTL

CNTENR

CNTRSTR

3201 drw 01

JUNE 1999

1

DSC-3201/7

IDT70927S/L

Preliminary

High-Speed 32K x 16 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Description

The IDT70927 is a high-speed 32K x 16 bit synchronous Dual-Port

RAM. The memory array utilizes Dual-Port memory cells to allow

simultaneous access of any address from both ports. Registers on

control, data, and address inputs provide minimal setup and hold

times. The timing latitude provided by this approach allows systems

to be designed with very short cycle times.

With an input data register, the IDT70927 has been optimized for

applications having unidirectional or bidirectional data flow in bursts.

An automatic power down feature, controlled byCE0and CE1, permits

the on-chip circuitry of each port to enter a very low standby power

mode. Fabricated using IDTs CMOS high-performance technology,

these devices typically operate on only 950mW of power.

Pin Configurations^(1,2,3)

Index

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

1

A9R

75

A9L

A10L

A11L

A12L

A13L

A

10R

2

74

73

72

A11R

A12R

A13R

A14R

NC

LBR

UBR

CE0R

CE1R

CNTRST

GND

3

4

5

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

6

A

14L

7

NC

LBL

UBL

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

IDT70927PF

PN100-1

(4)

CE0L

CE1L

CNTRSTL

Vcc

,

100-Pin TQFP

R

(5)

Top View

R/

WR

R/WL

OEL

OER

GND

I/O15L

I/O14L

I/O13L

I/O12L

I/O11L

I/O10L

56

55

I/O

15R

I/O14R

I/O13R

I/O12R

I/O11R

I/O10R

54

53

52

51

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

3201drw 02

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 14mm x 14mm x 1.4mm

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

2

6.42

IDT70927S/L

Preliminary

High-Speed 32K x 16 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Configurations (con't.)^(1,2)

81

A10R

80

A11R

77

A14R

74

72

69

CNT

RSTR

68

65

63

60

57

54

GND

NC

GND

NC

I/O13R I/O10R NC

UBR

12

11

10

09

08

84

A7R

83

A8R

78

A13R

76

73

LBR

70

67

64

61

59

56

53

NC

CE1R R/WR GND I/O14R I/O12R I/O9R

NC

87

A4R

86

A5R

82

A9R

79

A12R

75

71

66

OER

62

58

55

51

50

CE0R

NC

I/O15R I/O11R

NC

I/O8R I/O7R

90

A1R

88

A3R

85

A6R

52

49

47

NC

Vcc

I/O5R

92

91

A0R

89

A2R

48

46

45

CNT

ENR

95

I/O6R I/O4R I/O3R

94

93

44

I/O2R I/O1R I/O0R

39 40 41

I/01L

35

I/O4L I/O2L GND

43

42

GND

CLKR

07

06

ADSR

IDT70927PF

G108-1

(4)

96

97

98

CNT

ENL

108-Pin PGA

Top View

ADSL

CLKL

I/O0L GND

(5)

99

100

102

37

38

A0L

A1L

A3L

05

04

03

101

103

106

31

34

36

A2L

A4L

A7L

Vcc

I/O5L I/O3L

104

105

1

4

7

9

8

12

17

21

25

28

32

33

A5L

A6L

A10L

A13L

NC

CE1L GND I/O14L I/O10L

NC

I/O7L I/O6L

107

2

5

10

UBL

13

CNT

RST

16

OEL

19

22

24

29

30

I/O8L

A8L

A11L

A14L

GND I/O13L I/O11L NC

02

01

L

108

3

6

11

CE0L

14

15

18

20

23

26

27

A9L

A12L

NC

Vcc R/WL

NC I/O15L I/O12L I/O9L

NC

LBL

,

A

B

C

D

E

F

G

H

J

K

L

M

3201 drw 03

Index

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 1.21in x 1.21in x 0.16in

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

Pin Names

Left Port

Right Port

Names

Chip Enables

Read/Write Enable

Output Enable

Address

CE^0L1L

, CE

CE0R

1R

, CE

W^L

W^R

R/

OE^L

OER

0L

14L

0R

14R

- A

A

- A

A

0L

15L

0R

15R

I/O - I/O

Data Input/Output

Clock

L

R

CLK

UB^L

UBR

Upper Byte Select

Lower Byte Select

Address Strobe

Counter Enable

Counter Reset

Power

LB^L

LBR

ADS^L

ADSR

CNTEN^L

CNTRST^L

CNTENR

CNTRSTR

CC

V

GND

Ground

3201 tbl 01

6.342

IDT70927S/L

Preliminary

High-Speed 32K x 16 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Truth Table IRead/Write and Enable Control^(1,2,3)

Upper ^Byte

Lower B^yte

CLK

↑

0

CE¹

X

I/O^8-15

I/O^0-7

Mode

DeselectedPower Down

OE

X

L

CE

H

X

L

UB

X

H

L

LB

X

H

L

R/W

X

High-Z

D^IN

High-Z

D^IN

L

X

DeselectedPower Down

Both Bytes Deselected

Write to Upper Byte Only

Write to Lower Byte Only

Write to Both Bytes

↑

H

X

↑

L

H

L

↑

L

H

L

High-Z

D^IN

↑

L

H

L

D^IN

↑

L

H

L

H

L

H

X

D^OUT

High-Z

D^OUT

High-Z

D^OUT

High-Z

Read Upper Byte Only

Read Lower Byte Only

Read Both Bytes

↑

L

H

L

↑

L

H

L

↑

H

X

L

H

L

Outputs Disabled

3201 tbl 02

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, CNTRST = X.

3. OE is an asynchronous input signal.

TRUTH TABLE IIADDRESS COUNTER CONTROL^(1,2)

Address

CLK

↑

I/O

Mode

Counter Reset to Address 0

ADS

H

CNTEN

CNTRST

X

An

X

H

L

D^I/O(0)

D^I/O(n)

D^I/O(n+1)

L⁽³⁾

H

External Address Utilized

↑

An

H

External Address BlockedCounter Disabled

Counter EnableInternal Address Generation

↑

X

H

L⁽⁴⁾

↑

3201 tbl 03

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. CE⁰, LB, UB, and OE = VIL; CE1 and R/W = VIH.

3. ADS is independent of all other signals including CE⁰, CE1, UB and LB.

4. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.

4

6.42

IDT70927S/L

Preliminary

High-Speed 32K x 16 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Recommended Operating

Recommended DC Operating

TemperatureandSupplyVoltage^(1,2)Conditions

Symbol

Parameter

Min.

4.5

Typ. Max. Unit

Grade

Ambient

GND

Vcc

Temperature

V^CC

Supply Voltage

5.0

5.5

0

V

Commercial

0^OC to +70^OC

0V

5.0V + 10%

GND

V^IH

Ground

0

Industrial

-40^OC to +85^OC

6.0⁽¹⁾

0.8

____

Input High Voltage

Input Low Voltage

2.2

3201 tbl 04

-0.5^{(2 )}

V

____

NOTES:

V^IL

1. This is the parameter TA.

2. Industrial temperature: for specific speeds, packages and powers contact your

sales office.

3201 tbl 05

NOTES:

1. VTERM must not exceed Vcc + 10%.

2. VIL > -1.5V for pulse width less than 10ns.

Absolute Maximum Ratings⁽¹⁾

CAPACITANCE⁽¹⁾

(TA = +25°C, f = 1.0MHz) TQFP Only

Symbol

Rating

Commercial

& Industrial

Unit

Symbol

Parameter

Input Capacitance

Output Capacitance

Conditions⁽²⁾

Max. Unit

(2)

V^{TE RM}

Terminal Voltage

with Respect

to GND

-0.5 to +7.0

V

C^IN

V^IN= 3dV

9

pF

(3)

C^OUT

V^OUT= 3dV

10

pF

3201 tbl 07

Temperature

Under Bias

-55 to +125

50

^oC

T^BIAS

T^STG

I^OUT

NOTES:

1. These parameters are determined by device characterization, but are not produc-

tion tested.

Storage

Temperature

2. 3dV references the interpolated capacitance when the input and output switch from

0V to 3V or from 3V to 0V.

DC Output

Current

mA

3. COUT also references CI/O.

32 01 tb l 06

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.

DC Electrical Characteristics Over the Operating

Temperature Supply Voltage Range (VCC = 5.0V ± 10%)

70927S/L

Symbol

|I^LI|

Parameter

Input Leakage Current⁽¹⁾

Test Conditions

V^CC= 5.5V, V^IN= 0V to V^CC

Min.

Max.

10

Unit

µA

V

___

|I^LO|

Output Leakage Current

Output Low Voltage

Output High Voltage

0

IH

1

IL OUT

CC

10

CE = V or CE = V , V = 0V to V

V^OL

I^OL= +4mA

I^OH= -4mA

0.4

___

V^OH

2.4

V

3201 tbl 08

NOTE:

1. At Vcc < 2.0V input leakages are undefined.

6.542

IDT70927S/L

Preliminary

High-Speed 32K x 16 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range^(6,7)(VCC = 5V ± 10%)

70927X20

70927X25

70927X30

Com'l Only

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽⁴⁾

Max.

Typ.⁽⁴⁾

Max.

Typ.⁽⁴⁾

Max.

Unit

I^CC

Dynamic Operating

Current

(Both Ports Active)

S

L

210

390

350

200

345

305

190

325

285

mA

CE^Land CE^R= V^IL

Outputs Open

(1)

f = f^MAX

____

IND

S

L

SB1

I

Standby Current

(Both Ports - TTL

Level Inputs)

COM'L

IND

S

L

50

135

115

50

110

90

50

110

90

mA

CE^L= CE^R= V^IH

(1)

f = f^MAX

____

S

L

I^SB2

I^SB3

I^SB4

Standby Current

(One Port - TTL

Level Inputs)

COM'L

IND

S

L

140

270

240

130

230

200

120

220

190

CE^{"A "}= V^ILand

(3)

CE^{"B "}= V^IH

Active Port Outputs

____

S

L

(1)

Open, f=f^MAX

Full Standby Current

(Both Ports -

CMOS Level Inputs)

Both Ports CE^Rand

CE^L> V^CC- 0.2V

V^IN> V^CC- 0.2V or

V^IN< 0.2V, f = 0⁽²⁾

COM'L

IND

S

L

1.0

0.2

15

5

1.0

0.2

15

5

1.0

0.2

15

5

____

S

L

Full Standby Current

(One Port -

CMOS Level Inputs)

CE^{"A "}< 0.2V and

COM'L

S

L

130

245

225

120

205

185

110

195

175

CE^{"B "}> V^CC- 0.2V⁽⁵⁾

V^IN> V^CC- 0.2V or

V^IN< 0.2V, Active Port

____

IND

S

L

(1)

Outputs Open, f = f^MAX

3201 tbl 09

NOTES:

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of

GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).

5. CE^X= VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V

CE^X> VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V

"X" represents "L" for left port or "R" for right port.

6. 'X' in part numbers indicate power rating (S or L).

7. Industrial temperature: for specific speeds, packages and powers contact your sales office.

6

6.42

IDT70927S/L

Preliminary

High-Speed 32K x 16 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Test Conditions

Input Pulse Levels

GND to 3.0V

3ns Max.

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

1.5V

Figures 1,2 and 3

3201 tbl 10

5V

893Ω

DATAOUT

DATA_OUT

30pF

347Ω

5pF*

347Ω

3201 drw 04

3201 drw 05

Figure 2. Output Test Load

Figure 1. AC Output Test load.

(For tCKLZ, tCKHZ, tOLZ, and tOHZ).

*Including scope and jig.

8

7

6

5

- 10pF is the I/O capacitance

of this device, and 30pF is the

AC Test Load Capacitance

∆ tCD1

(Typical, ns)

4

3

2

1

0

,

20 40 60 80 100 120 140 160 180 200

Capacitance (pF)

-1

3201 drw 06

Figure 3. Typical Output Derating (Lumped Capacitive Load).

6.742

IDT70927S/L

Preliminary

High-Speed 32K x 16 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating Temperature Range

(Read and Write Cycle Timing)^(2,3,4)(VCC = 5V ± 10%, TA = 0°C to +70°C)

70927X20

70927X25

70927X30

Com'l Only

Symbol

t^CYC1

Parameter

Clock Cycle Time (Flow-Through)⁽²⁾

Min.

Max.

Min.

Max.

Min.

Max.

Unit

ns

____

25

12

30

12

35

12

t^CH1

t^CL1

t^R

Clock High Time (Flow-Through)⁽²⁾

Clock Low Time (Flow-Through)⁽²⁾

Clock Rise Time

12

____

3

____

t^F

Clock Fall Time

3

____

t^SA

Address Setup Time

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

1

4

____

t^HA

Address Hold Time

t^SC

Chip Enable Setup Time

Chip Enable Hold Time

Byte Enable Setup Time

Byte Enable Hold Time

R/W Setup Time

t^HC

t^SB

t^HB

t^SW

t^HW

t^SD

R/W Hold Time

Input Data Setup Time

Input Data Hold Time

t^HD

t^SAD

t^HAD

t^SCN

t^HCN

t^SRST

t^HRST

t^OE

ADS Setup Time

ADS Hold Time

CNTEN Setup Time

CNTEN Hold Time

CNTRST Setup Time

1

CNTRST Hold Time

____

Output Enable to Data Valid

Output Enable to Output Low-Z⁽¹⁾

Output Enable to Output High-Z⁽¹⁾

Clock to Data Valid (Flow-Through)

Data Output Hold After Clock High

Clock High to Output High-Z ⁽¹⁾

Clock High to Output Low-Z⁽¹⁾

12

15

____

t^OLZ

t^OHZ

t^CD1

t^DC

2

1

7

1

7

1

7

____

20

25

30

____

2

t^CKHZ

t^CKLZ

Port-to-Port Delay

t^CWDDWrite Port Clock High to Read Data Delay

t^CCSClock-to-Clock Setup Time

9

____

35

15

40

15

50

20

ns

3201 tbl 11

NOTES:

1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

This parameter is guaranteed by device characterization, but is not production tested.

2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE).

3. 'X' in part number indicates power rating (S or L).

4. Industrial temperature: for specific speeds, packages and powers contact your sales office.

8

6.42

IDT70927S/L

Preliminary

High-Speed 32K x 16 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

TIMING WAVEFORM OF READ CYCLE FOR FLOW-THROUGH OUTPUT⁽³⁾

tCYC1

tCH1

tCL1

CLK

CE0

tSC

(4)

tHC

tHB

tSC

tSB

tHC

tHB

CE1

UB, LB

R/W

tSB

tHW

tHA

tSW

tSA

(5)

ADDRESS

An

An + 1

An + 2

An + 3

(1)

tDC

tCD1

tCKHZ

Qn

Qn + 1

Qn + 2

DATAOUT

(1)

tDC

tCKLZ

(1)

tOHZ

tOLZ

tOE

(2)

OE

3201 drw 07

TIMING WAVEFORM OF A BANK SELECT FLOW-THROUGH READ^(6,7)

tCYC1

tCH1

tCL1

CLK

tSA tHA

A6

A5

A4

A3

A2

A0

A1

ADDRESS(B1)

tSC tHC

CE0(B1)

tSC tHC

(1)

tCD1

tCKHZ

tCD1

(1)

tCD1

(1)

Q0

A1

Q3

Q5

A6

Q1

A2

DATAOUT(B1)

ADDRESS(B2)

(1)

tDC

tCKLZ

tDC

tCKHZ

tSA tHA

A0

A5

A4

A3

tSC tHC

CE0(B2)

tSC tHC

(1)

tCD1

(1)

tCKHZ

tCD1

(1)

tCKHZ

Q4

DATAOUT(B2)

Q2

tCKLZ

3201 drw 08

NOTES:

1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

3. ADS = VIL, CNTEN and CNTRST = VIH.

4. The output is disabled (High-impedance state) by CE⁰= VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to

Truth Table 1.

5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

6. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70927 for this waveform,

and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.

7. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.

6.942

IDT70927S/L

Preliminary

High-Speed 32K x 16 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Left Port Write to Flow-Through Right Port Read^(1,2)

CLK L

tSW tHW

R/W L

tSA tHA

NO

ADDRESS L

DATAIN L

CLK R

MATCH

tSD tHD

VALID

(3)

tCCS

tCD1

R/

W

R

tHW

tHA

tSW

tSA

NO

MATCH

ADDRESS R

DATAOUT R

MATCH

(3)

tCD1

tCWDD

VALID

tDC

3201 drw 09

NOTES:

1. CE⁰, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.

2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.

3. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.

If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.

10

6.42

IDT70927S/L

Preliminary

High-Speed 32K x 16 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)⁽³⁾

tCYC1

tCH1

tCL1

CLK

CE0

CE1

tSC tHC

tSB

tHB

UB, LB

R/W

tSW tHW

(4)

An + 4

An

An + 3

An +1

An + 2

tSD tHD

Dn + 2

ADDRESS

tSA tHA

DATAIN

tCD1

(2)

Qn + 3

Qn

READ

Qn + 1

DATAOUT

(1)

tCKLZ

tDC

tCKHZ

NOP⁽⁵⁾

READ

WRITE

3201 drw 10

TimingWaveformofFlow-ThroughRead-to-Write-to-Read(OEControlled)⁽³⁾

tCYC1

tCH1

tCL1

CLK

CE0

tSC tHC

CE1

tSB

tHB

UB, LB

tSW tHW

R/W

tSW tHW

ADDRESS⁽⁴⁾

An + 5

An

An +1

An + 2

An + 3

Dn + 3

An + 4

tSA tHA

tSD tHD

DATAIN

Dn + 2

tOE

tCD1

tDC

tCD1

(2)

Qn + 4

tDC

Qn

DATAOUT

(1)

tCKLZ

(1)

tOHZ

OE

READ

WRITE

READ

3201 drw 11

NOTES:

1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

3. CE⁰, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".

4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.

5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

61.412

IDT70927S/L

Preliminary

High-Speed 32K x 16 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

TimingWaveformof Flow-ThroughReadwithAddressCounterAdvance⁽¹⁾

tCYC1

tCH1

tCL1

CLK

tSA tHA

An

ADDRESS

tSAD tHAD

ADS

tSAD tHAD

tSCN tHCN

CNTEN

tCD1

Qn + 3⁽⁴⁾

Qx⁽⁴⁾

Qn

Qn + 4

Qn + 1

Qn + 2

DATA_OUT

tDC

READ

WITH

COUNTER

3201 drw 12

READ

EXTERNAL

ADDRESS

READ WITH COUNTER

COUNTER

HOLD

Timing Waveform of Write with Address Counter Advance⁽²⁾

tCYC1

t_CH1

t_CL1

CLK

tSA tHA

An

ADDRESS

INTERNAL⁽³⁾

ADDRESS

An⁽⁵⁾

An + 4

An + 2

An + 1

An + 3

tSAD tHAD

ADS

CNTEN

tSD tHD

Dn

Dn + 4

Dn + 1

Dn + 3

Dn + 1

Dn + 2

DATAIN

WRITE

EXTERNAL

ADDRESS

WRITE

WITH COUNTER

WRITE

COUNTER HOLD

WRITE WITH COUNTER

3201 drw 13

NOTES:

1. CE⁰, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.

2. CE⁰, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.

3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.

4. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then

the data output remains constant for subsequent clocks.

5. CNTEN = VIL advances Internal Address from An to An +1. The transition shown indicates the time required for the counter to advance. The

An +1Address is written to during this cycle.

12

6.42

IDT70927S/L

Preliminary

High-Speed 32K x 16 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Counter Reset⁽¹⁾

t_CYC1

t_CH1

t_CL1

CLK

t_SAt_HA

(3)

An +

An

An + 1

ADDRESS

INTERNAL⁽²⁾

ADDRESS

Ax⁽⁵⁾

An + 1

0

1

An

t_SWt_HW

R/

W

ADS

CNTEN

t

SRST t_HRST

CNTRST

DATA_IN

t_SD

t_HD

D₀

(4)

An + 1

An

Q₁

Q₀

DATA_OUT

COUNTER⁽⁵⁾

RESET

WRITE

ADDRESS 0

READ

ADDRESS 0

READ

ADDRESS 1

READ

ADDRESS n

READ

ADDRESS n+1

3201 drw 14

NOTES:

CE⁰, UB, LB = VIL; CE1 = VIH.

1.

2. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.

4. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

5. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Extra ADDR0 will be accessed. Extra cycles are shown

here simply for clarification.

61.432

IDT70927S/L

Preliminary

High-Speed 32K x 16 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

FUNCTIONAL DESCRIPTION

Depth and Width Expansion

The IDT70927 provides a true synchronous Dual-Port Static RAM

interface. Registered inputs provide minimal set-up and hold times on

address, data, and all critical control inputs. All internal registers are

clocked on the rising edge of the clock signal, however, the self-timed

internal write pulse is independent of the LOW to HIGH transition of

the clock signal.

An asynchronous output enable is provided to ease asynchronous

bus interfacing. Counter enable inputs are also provided to stall the

operation of the address counters for fast interleaved memory appli-

cations.

The IDT70927 features dual chip enables (refer to Truth Table I)

in order to facilitate rapid and simple depth expansion with no

requirements for external logic. Figure 4 illustrates how to control the

various chip enables in order to expand two devices in depth.

The 70927 can also be used in applications requiring expanded

width, as indicated in Figure 4. Since the banks are allocated at the

discretion of the user, the external controller can be set up to drive the

input signals for the various devices as required to allow for 32-bit or

wider applications.

A HIGH on CE⁰or a LOW on CE1 for one clock cycle will power

down the internal circuitry to reduce static power consumption.

Multiple chip enables allow easier banking of multiple IDT70927's for

depth expansion configurations.

A¹⁵

IDT70927

CE⁰

CE¹

V^CC

Control Inputs

IDT70927

CE¹

1

CE

CE⁰

CNTRST

CLK

Control Inputs

ADS

CNTEN

R/W

3201 drw 15

OE

Figure 4. Depth and Width Expansion with IDT70927

14

6.42

IDT70927S/L

Preliminary

High-Speed 32K x 16 Synchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Ordering Information

IDT XXXXX

A

99

A

Device

Type

Power Speed

Package

Process/

Temperature

Range

Blank

I⁽¹⁾

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

PF

G

100-pin TQFP (PN100-1)

108-pin PGA (G108-1)

20

25

30

Commercial Only

Speed in nanoseconds

S

L

Standard Power

Low Power

70927 512K (32K x 16-Bit) Synchronous Dual-Port RAM

3201 drw 16

NOTE:

1. Industrial temperature range is available.

For specific speeds, packages and powers contact your sales office.

Preliminary Datasheet:

"PRELIMINARY' datasheets contain descriptions for products that are in early release.

Datasheet Document History

1/12/99:

Initiated datasheet document history

Converted to new format

Cosmetic and typographical corrections

Added additional notes to pin configurations

Page 14 Added Depth and Width Expansion note

Changed drawing format

6/3/99:

Page 4 Deleted note 5 for Table II

CORPORATE HEADQUARTERS

2975 Stender Way

Santa Clara, CA 95054

for SALES:

for Tech Support:

831-754-4613

DualPortHelp@idt.com

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

61.452


型号：	IDT70927S30PF9
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Dual-Port SRAM, 32KX16, 30ns, PQFP100, TQFP-100 静态存储器
文件：	总15页 (文件大小：192K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT70927S30PF9 [IDT]

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