IDT70P3519S166BCG8 [IDT]
SRAM;
| 型号： | IDT70P3519S166BCG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | SRAM 静态存储器 |
| 文件： | 总28页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 1.8V
256/128K x 36
SYNCHRONOUS
PRELIMINARY
IDT70P3519/99
DUAL-PORT STATIC RAM
WITH 3.3V/2.5V/1.8V INTERFACE
Features:
◆
Counter enable and repeat features
◆
True Dual-Port memory cells which allow simultaneous
◆
◆
Interrupt and Collision Detection Flags
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
1.8V (±100mV) power supply for core
LVTTL compatible,1.8V to 3.3V power supply for I/Os and
control signals on each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz
Available in a 256-pin Ball Grid Array (BGA), a 208-pin
Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball
GridArray(fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Due to limited pin count JTAG is not supported on the 208-
pin PQFP package
access of the same memory location
Low Power
High-speed data access
◆
◆
◆
◆
◆
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)
– Industrial: 3.6ns (166MHz)
Selectable Pipelined or Flow-Through output mode
◆
◆
Dual chip enables allow for depth expansion without
◆
◆
additional logic
◆
Full synchronous operation on both ports
– 5ns cycle time, 200MHzoperation(14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timedwriteallowsfastcycletime
◆
◆
◆
Green parts available, see ordering information
FunctionalBlockDiagram
BE3R
BE3L
BE2L
BE1L
BE0L
BE2R
BE1R
BE0R
FT/PIPE
L
0a 1a
a
0b 1b
b
0c 1c
c
0d 1d
d
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
a
FT/PIPE
R
1/0
1/0
R/WL
R/W
R
CE0L
CE0R
1
1
CE1R
CE1L
0
0
B
B B B
B
B
B
B
1/0
1/0
W W W W W W W W
0
L
1
L
2
L
3
L
3
R
2
R
1
R
0
R
OE
R
OE
L
Dout0-8_L
Dout0-8_R
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout9-17_R
Dout18-26_R
Dout27-35_R
,
1d 0d 1c 0c
1b 0b 1a 0a
0a 1a 0b 1b
0c 1c 0d 1d
d c b a
0/1
0/1
FT/PIPE
L
FT/PIPER
a bc d
256/128K x 36
MEMORY
ARRAY
I/O0L - I/O35 L
I/O0R - I/O35R
Din_L
Din_R
,
CLK
R
CLK
L
(1)
17R
(1)
0L
A
A
17L
A
Counter/
Address
Reg.
Counter/
Address
Reg.
A
0R
REPEAT
ADS
CNTEN
ADDR_R
ADDR_L
REPEAT
L
R
R
ADS
L
R
CNTEN
L
TDI
TCK
T MS
T RST
INTERRUPT
CE0
CE1
CE
0
R
L
JTAG
COLLISION
DETECTION
LOGIC
R
CE1
TDO
L
R/
W
L
R/W
R
COL L
INTL
COLR
INTR
(2)
(2)
ZZR
ZZ
ZZL
CONTROL
LOGIC
7144 drw 01
NOTES:
1. Address A17 is a NC for the IDT70P3599.
+. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and the
JULY 2008
sleep mode pins themselves (ZZx) are not affected during sleep mode.
1
DSC 7144/1
©2008IntegratedDeviceTechnology,Inc.
IDT70P3519/99
Preliminary
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Description:
TheIDT70P3519/99isahigh-speed256/128Kx36bitsynchronous or bidirectional data flow in bursts. An automatic power down feature,
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to controlledbyCE0andCE1, permits the on-chipcircuitryofeachportto
allowsimultaneousaccessofanyaddressfrombothports.Registerson enter a very low standby power mode.
control,data,andaddressinputsprovideminimalsetupandholdtimes.
The70P3519/99 cansupportanoperatingvoltageof 3.3V, 2.5Vor
The timing latitude provided by this approach allows systems to be 1.8V on one or both ports. The power supply for the core of the device
designed with very short cycle times. With an input data register, the (VDD) is 1.8V.
IDT70P3519/99hasbeenoptimizedforapplicationshavingunidirectional
6.42
JULY 7, 2008
2
FEBRUARY 15, 2008
IDT70P3519/99
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Pin Configuration (2,3,4)
70P3519/99BC
BC-256(5)
256-Pin BGA
Top View(6)
02/12/08
A1
A2
A3
A6
A7
A8
A9
A11
A12
A13
A14
A4
A5
A10
A15
A16
(1)
NC
TDI
NC
A
11L
A
8L
9L
7L
BE2L CE1L
CNTEN
L
L
A
5L
A
2L
A
0L
A
17L
A
14L
OE
L
NC
NC
B1
B2
B3
B6
B7
B9
CE0L
B11
B12
B13
B4
B5
B8
B10
B14
B15
B16
I/O18L NC TDO
A
12L
A
REPEAT
A4L
A
1L
NC
A
15L
BE3L
R/W
L
VDD I/O17L NC
C1
C5
C6
C2
C3
C4
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
I/O18R
A
13L
A
10L
I/O19L
V
SS
A
BE1L BE0L CLK
L
ADS
L
A6L
A
3L
I/O16L
A
16L
NC I/O17R
D1
D2
D6
D9
D11
D3
D5
D7
D8
D10
D12
D13
D14
D15
D16
D4
I/O20R I/O19R
VDDQL
VDDQL
VDDQR
VDDQL
I/O20L
V
PIPE/FTL
DDQL
V
DDQR
VDDQR
VDDQR
VDD I/O15R I/O15L I/O16R
E6
E5
E7
E8
E9
E10
E11
E12
E13
E1
E2
E3
E4
E14
E16
E15
V
DD
V
DD
INT
L
V
SS
SS
SS
V
SS
SS
SS
V
SS
V
DD
V
DD
V
DDQR
I/O13L
I/O21R I/O21L I/O22L
V
DDQL
I/O14R
I/O14L
F7
F1 F2 F3
F5
F6
F9
F10
F14
F15
F16
F11
F13
F4
F8
F12
COL
L
VDD
NC
V
VSS
I/O23L I/O22R I/O23R
G1
VSS
V
DDQR I/O12R I/O13R I/O12L
V
V
DD
VDDQL
G5
H5
G2
G4
G6
G8
G9
G3
G7
G10
G12
G13 G14 G15 G16
G11
I/O24R
V
SS
I/O24L
V
DDQR
VSS
V
V
I/O25L
I/O10L I/O11L I/O11R
H16
VSS
VSS
VSS
V
DDQL
VSS
H11
H12
H13
H7
H8
H9
H10
H14
H15
H3
H4
H6
H1
H2
VSS
V
SS
VDDQL
I/O10R
VSS
VSS
VSS
V
SS
I/O9R IO9L
VSS
VSS
I/O26R
V
DDQR
I/O26L I/O25R
J1
J2
J3
J4
J5
J6
J7
J8
J9
J13
J10
J11
J12
J14
J15
J16
I/O27L
I/O28R I/O27R
V
DDQL ZZ
R
V
SS
V
SS
V
SS
SS
V
SS
V
DDQR
I/O8R
V
SS
V
SS
ZZ
L
I/O7R I/O8L
K6
K8
K10
K12
K13
K5
K7
K9
K11
K2
K4
K15
K16
K1
K3
K14
VSS
V
VSS
V
SS
V
DDQR
I/O6R
I/O29L
V
DDQL
V
SS
V
SS
V
SS
V
SS
I/O6L I/O7L
I/O29R
I/O28L
L7
L8
L11
L12
L13
L3
L4
L5
L6
L9
L10
L15
L16
L1
L2
L14
COLR
V
SS
VSS
V
DD
V
DDQL
I/O30R
VDDQR
VDD
NC
V
SS
V
SS
I/O4R I/O5R
I/O30L I/O31R
I/O5L
M5
M6
M7
M8
M9
M10
M11
M12
M13
M1 M2
M3
M4
M16
M14
M15
VDD
V
DD INT
R
V
SS
V
SS
VSS
VDD
V
DD
V
DDQL
I/O3R I/O3L
I/O32R I/O32L I/O31L
V
DDQR
I/O4L
N8
N12
N16
N13
N4
N5
N6
N7
N9
N10
N11
N15
N1
N2
N3
N14
V
DDQL
V
DDQL
V
DD
I/O2R
R VDDQR
P5
V
DDQR
V
DDQL
V
DDQR
V
DDQR
V
DDQL
PIPE/FT
I/O1R
I/O33L I/O34R I/O33R
I/O2L
P1
P2
P3
P4
P7
P8
P9
P10
P11
P12
P14
P15
P16
P6
P13
A
16R
I/O35R I/O34L TMS
A
13R
A
7R BE1R BE0R CLK
R
ADS
R
A
6R
4R
5R
I/O0L I/O0R I/O1L
A
10R
A
3R
R5
R6
R7
R8 R9 R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R15
,
A
15R
A
12R
A
9R
BE3R CE0R R/W
R
REPEAT
R
NC
I/O35L NC TRST NC
A
A1R
NC
NC
T2
T3
T4
17R
T1
T5
T8
T9
T15
T16
T6
T7
T10
T11
T12
T13
T14
(1)
A
TCK
NC
NC
A
14R
BE2R CE1R
NC
NC
A11R
A
8R
OER
CNTEN
R
A
A
2R
A
0R
NOTES:
1. Pin is a NC for IDT70P3599.
7144 drw 02d
2. All VDD pins must be connected to 1.8V power supply.
3. All VSS pins must be connected to ground supply.
,
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
3
JULY 7, 2008
IDT70P3519/99
Preliminary
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration (2,3,4,7) (con't.)
02/12/08
I/O16L
156
1
2
3
4
5
6
I/O19L
I/O19R
I/O20L
I/O20R
I/O16R
155
I/O15L
154
I/O15R
153
VSS
VDDQL
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VDDQL
VSS
I/O14L
I/O14R
I/O13L
I/O13R
7
8
9
I/O21L
I/O21R
I/O22L
I/O22R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
VSS
VDDQR
VDDQR
VSS
I/O12L
I/O12R
I/O11L
I/O11R
I/O23L
I/O23R
I/O24L
I/O24R
VSS
VDDQL
VDDQL
VSS
I/O10L
I/O10R
I/O9L
I/O25L
I/O25R
I/O26L
I/O26R
I/O9R
V
V
V
V
V
V
SS
VDDQR
DDQR
DD
70P3519/99DR
ZZ
R
VDD
(5)
DD
VDD
DR-208
SS
V
V
SS
SS
SS
ZZ
L
VDDQL
VDDQL
208-Pin PQFP
VSS
I/O8R
I/O8L
I/O7R
I/O7L
I/O27R
I/O27L
I/O28R
I/O28L
(6)
Top View
VSS
VDDQR
VDDQR
VSS
I/O6R
I/O6L
I/O5R
I/O5L
I/O29R
I/O29L
I/O30R
I/O30L
VSS
VDDQL
VDDQL
VSS
I/O4R
I/O4L
I/O3R
I/O3L
I/O31R
I/O31L
I/O32R
I/O32L
VSS
VDDQR
VDDQR
VSS
I/O2R
I/O2L
I/O1R
I/O1L
I/O33R
I/O33L
I/O34R
I/O34L
,
7144 drw 02a
NOTES:
1. Pin is a NC for IDT70P3599.
2. All VDD pins must be connected to 1.8V power supply.
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 28mm x 28mm x 3.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
7. Due to limited pin count, JTAG is not supported in the DR-208 package.
6.42
JULY 7, 2008
4
FEBRUARY 15, 2008
IDT70P3519/99
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Pin Configuration (2,3,4) (con't.)
02/12/08
A1
A2
A3
A6
A7
A8
A9
BE1L
A11
A12
A13
A14
A17
A4
A10
A15
A16
A5
I/O19L I/O18L
V
SS
A
12L
A
8L
CLK
L
CNTEN
L
A
4L
A
0L
V
SS
TDO
A
16L
13L
14L
VDD
NC I/O17L
COL
L
B1
B2
B3
B6
B7
B9
CE0L
B11
B12
B13
B17
B4
B5
B8
B10
B14
B15
B16
(1)
I/O20R
V
SS I/O18R
A17L
A
A
9L
ADS
L
A
5L
A
1L
I/O15R
TDI
BE2L
VSS
NC
V
DDQR I/O16L
C1
C6
C2
C3
C4
C5
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
C17
V
DDQL
A
I/O19R
V
DDQR PL/FT
L
INT
L
A
10L BE3L CE1L
V
SS R/W
L
A
6L
A
2L
I/O15L
V
DD I/O16R
VSS
D1
D2
D6
D9
D11
REPEATL
D3
D5
D7
D8
D10
D12
D13
D14 D15
D16
D17
D4
I/O22L
V
SS
A
11L
V
DD
I/O21L
A
15L
A
7L BE0L
OE
L
A
3L
VDD I/O17R
V
DDQL I/O14L I/O14R
I/O20L
E1
E2
E3
E4
E14
E16
E17
E15
I/O23L I/O22R
V
DDQR I/O21R
I/O12L
V
SS I/O13L
I/O13R
F1
F2
F3
F14
F15
F16
F17
F4
V
DDQL I/O23R I/O24L
VSS I/O12R I/O11L VDDQR
V
SS
G1
G2
G4
G14
G15
G16
G3
G17
I/O26L
V
SS
I/O24R
I/O9L
V
DDQL I/O10L
I/O25L
I/O11R
H3
H4
H1
H2
H16
H17
H14
H15
70P3519/99BF
BF-208(5)
V
DDQR I/O25R
V
DD I/O26R
V
SS I/O10R
V
DD I/O9R
J1
J2
J3
J4
J14
J15
J16
J17
V
DDQL
V
DD
SS
V
SS
ZZ
R
ZZ
L
V
DD
V
SS
VDDQR
208-Pin fpBGA
Top View(6)
K2
K4
K15
K16
K1
K3
K14
K17
V
V
SS
VDDQL I/O8R
I/O7R
I/O28R
I/O27R
V
SS
L3
L4
L15
L16
L17
L1
L2
L14
V
DDQR I/O27L
I/O7L
V
SS I/O8L
I/O29R I/O28L
I/O6R
M1
M2
M3
M4
M16
M17
M14
M15
V
DDQL I/O29L I/O30R
V
SS
I/O5R
V
DDQR
VSS
I/O6L
N16
N17
N4
N15
N1
N2
N3
N14
I/O4R I/O5L
DDQL
I/O30L
V
I/O31L
V
SS I/O31R
I/O3R
P12
P1
P2
P3
P4
P5
P7
P8
P9
P10
P11
P14
P15
P16
P17
P6
P13
A
16R
I/O32R I/O32L
V
DDQR I/O35R TRST
A
12R
A
8R BE1R
VDD CLK
R
I/O2L I/O3L
V
SS I/O4L
CNTEN
R
A
4R
R5
R6
R7
R8
R9
R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R17
R15
(1)
A
17R
A
13R
A
9R
BE2R CE0R
V
SS ADS
R
R
I/O1R
V
SS I/O33L I/O34R TCK
A
5R
A
1R
NC
V
DDQR
V
DDQL
T2
T3
T1
T4
T5
T8
T9
T15
T16
T17
T6
T7
T10
T11
T12
T13
T14
SS
I/O34L
VDDQL
I/O33R
TMS INT
R
BE3R CE1R
I/O0R
V
SS I/O2R
A
14R
A
10R
V
SS R/W
A
6R
A
2R
V
U1
U2
U3
U4
U5
U6
U7
U17
U8
BE0R
U9
U10
U12
U13
U14
DD
U16
U15
V
SS I/O35L PL/FT
R
COL
R
A
15R
A
11R
A
7R
I/O1L
V
DD
OE
R
A
3R
A
0R
V
I/O0L
NC
7144 drw 02c
NOTES:
1. Pin is a NC for IDT70P3599.
2. All VDD pins must be connected to 1.8V power supply.
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
5
JULY 7, 2008
IDT70P3519/99
Preliminary
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
Names
Chip Enables (Input)(6)
CE0L
R/W
OE
,
CE1L
CE0R
R/W
OE
,
CE1R
L
R
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
L
R
(5)
(5)
A
0L - A17L
A
0R - A17R
I/O0R - I/O35R
CLK
I/O0L - I/O35L
CLK
Data Input/Output
L
R
Clock (Input)
PL/FT
ADS
CNTEN
REPEAT
BE0L - BE3L
DDQL
L
PL/FT
ADS
CNTEN
REPEAT
BE0R - BE3R
DDQR
R
Pipeline/Flow-Through (Input)
Address Strobe Enable (Input)
Counter Enable (Input)
L
R
L
R
(2)
Counter Repeat
L
R
Byte Enables (9-bit bytes) (Input)(6)
Power (I/O Bus) (3.3V, 2.5V or 1.8V)(1) (Input)
Sleep Mode pin(3) (Input)
Power (1.8V)(1) (Input)
V
V
ZZL
ZZR
V
DD
SS
(4)
NOTES:
V
Ground (0V) (Input)
1. VDD and VDDQX must be set to appropriate operating levels prior to applying inputs
on the I/Os and controls for that port.
TDI
Test Data Input
2. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
3. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and the sleep mode pins themselves
(ZZx) are not affected during sleep mode.
4. Due to limited pin count, JTAG is not supported in the DR-208 package.
5. Address A17x is a NC for the IDT70P3599.
6. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
(4)
TDO
Test Data Output
(4)
TCK
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)
Interrupt Flag (Output)
TMS(4)
TRST(4)
INT
R
INTL
COL
R
Collision Alert (Output)
COL
L
7144 tbl 01
6.42
JULY 7, 2008
6
FEBRUARY 15, 2008
IDT70P3519/99
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
(1,2,3,4)
Truth Table I—Read/Write and Enable Control
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
CLK
CE
1
R/W
X
X
X
L
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
MODE
OE
X
X
X
X
X
X
X
X
X
X
L
CE
0
BE
3
BE
2
BE
1
BE0
↑
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
L
X
X
H
H
H
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z Deselected–Power Down
High-Z Deselected–Power Down
High-Z All Bytes Deselected
↑
↑
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
↑
DIN
Write to Byte 0 Only
↑
H
H
H
L
L
DIN
High-Z Write to Byte 1 Only
High-Z Write to Byte 2 Only
High-Z Write to Byte 3 Only
↑
H
H
L
L
DIN
High-Z
High-Z
↑
H
H
L
L
D
IN
High-Z
High-Z
↑
H
L
L
High-Z
DIN
DIN
Write to Lower 2 Bytes Only
↑
H
L
H
L
L
DIN
DIN
High-Z
High-Z Write to Upper 2 bytes Only
↑
L
L
L
DIN
DIN
DIN
D
IN
Write to All Bytes
Read Byte 0 Only
↑
H
H
H
L
H
H
L
H
L
L
H
H
H
H
H
H
H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
L
↑
H
H
H
L
DOUT
High-Z Read Byte 1 Only
High-Z Read Byte 2 Only
High-Z Read Byte 3 Only
L
↑
H
H
L
DOUT
High-Z
High-Z
L
↑
H
H
L
D
OUT
High-Z
High-Z
L
↑
H
L
High-Z
DOUT
D
OUT
Read Lower 2 Bytes Only
High-Z Read Upper 2 Bytes Only
Read All Bytes
L
↑
H
L
H
L
DOUT
DOUT
High-Z
L
↑
L
L
DOUT
DOUT
DOUT
DOUT
H
X
↑
X
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z Outputs Disabled
High-Z Sleep Mode
X
7144 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = X.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
(1,2)
Truth Table II—Address Counter Control
Previous
Internal
Address
Internal
Address
Used
MODE
(3)
ADS CNTEN REPEAT(6)
Address
CLK
↑
I/O
I/O (n) External Address Used
I/O(n+1) Counter Enabled—Internal Address generation
I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
DI/O(n) Counter Set to last valid ADS load
(4)
An
X
X
An
An
L
H
H
X
X
H
H
D
(5)
An + 1
An + 1
An
↑
L
H
X
D
X
An + 1
X
↑
H
D
(4)
X
↑
L
7144 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
6.42
7
JULY 7, 2008
IDT70P3519/99
Preliminary
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
RecommendedOperating
(1)
Temperature and Supply Voltage
Ambient
Grade
Commercial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
VDD
1.8V
1.8V
+
+
100mV
Industrial
0V
100mV
7144 tbl 04
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
RecommendedDCOperating
Conditions with VDDQ at 1.8V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Min.
Typ.
Max.
1.9
1.9
0
Unit
V
V
DD
DDQ
SS
IH
1.7
1.8
V
1.7
1.8
V
V
0
0
V
(2)
____
V
Input High Voltage
0.7 VDDQ
VDDQ + 100mV
V
_
Input High Voltage
JTAG
(2)
____
VIH
0.7 VDDQL
V
DDQL + 100mV
V
(3)
Input High Voltage -
ZZ, PIPE/FT
(2)
____
____
____
V
IH
V
DDQ - 0.2V
V
DDQ + 100mV
V
V
V
VIL
Input Low Voltage
-0.3(1)
0.3 VDDQ
0.2
Input Low Voltage -
ZZ, PIPE/FT
VIL
-0.3(1)
7144 tbl 05c
NOTES:
1. VIL (min.) = -0.75V for pulse width less than tCYC/2, or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 0.75V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. JTAG is driven by the left port VDDQL.
RecommendedDCOperating
Conditions with VDDQ at 2.5V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Min.
1.7
2.4
0
Typ.
1.8
Max.
1.9
2.6
0
Unit
V
V
DD
DDQ
SS
IH
V
2.5
V
V
0
V
(2)
____
V
Input High Volltage
Input High Voltage _
1.7
V
DDQ + 100mV
V
(2)
____
VIH
1.7
VDDQL + 100mV
V
(3)
JTAG
Input High Voltage -
ZZ, PIPE/FT
(2)
____
____
____
V
IH
V
DDQ - 0.2V
V
DDQ + 100mV
V
V
V
VIL
Input Low Voltage
-0.3(1)
0.7
0.2
Input Low Voltage -
ZZ, PIPE/FT
VIL
-0.3(1)
7144 tbl 05a
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. JTAG is driven by the left port VDDQL.
6.42
JULY 7, 2008
8
FEBRUARY 15, 2008
IDT70P3519/99
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
RecommendedDCOperating
Conditions with VDDQ at 3.3V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Min.
1.7
3.15
0
Typ.
1.8
Max.
1.9
3.45
0
Unit
V
V
DD
DDQ
SS
IH
V
3.3
V
V
0
V
(2)
____
V
Input High Voltage
2.0
VDDQ + 150mV
V
_
Input High Voltage
JTAG
(2)
____
VIH
2.0
V
DDQL + 150mV
V
(3)
Input High Voltage -
ZZ, PIPE/FT
(2)
____
____
____
V
IH
V
DDQ - 0.2V
V
DDQ + 150mV
V
V
V
VIL
Input Low Voltage
-0.3(1)
0.8
0.2
Input Low Voltage -
ZZ, PIPE/FT
VIL
-0.3(1)
7144 tbl 05b
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. JTAG is driven by the left port VDDQL.
Absolute Maximum Ratings (1)
Symbol
Rating
Commercial
& Industrial
Unit
V
V
TERM
VDD Terminal Voltage
- 0.5 to + 2.5
- 0.3 to + 4.2
(VDD
)
with Respect to GND
(2)
TERM
V
VDDQ Terminal Voltage
V
(VDDQ
)
with Respect to GND
(4)
(2)
TERM
V
Input and I/O Terminal
- 0.3 to min. {VDDQ + 0.3, 4.2}
V
(INPUTS and I/O's)
Voltage with Respect to GND
(3)
T
BIAS
STG
JN
Temperature Under Bias
Storage Temperature
Junction Temperature
-55 to +125
oC
oC
T
-65 to +150
T
+150
50
oC
I
OUT(For VDDQ = 3.3V) DC Output Current
OUT(For VDDQ = 2.5V) DC Output Current
OUT(For VDDQ = 1.8V) DC Output Current
mA
mA
I
40
I
35
mA
7144 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its
nominal operating value. Power sequencing is not necessary; however, the voltage
on any Input or I/O pin cannot exceed VDDQ during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
4. VTERM (Inputs and I/O's) -0.3 to min {VDDQ + 0.3, 4.2} means that the range is -0.3V to
either VDDQ +0.3V or 4.2V whichever is less.
6.42
9
JULY 7, 2008
IDT70P3519/99
Preliminary
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
8
pF
(3)
OUT
C
V
10.5
pF
7144 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 1.8V ± 100mV)
70P3519/99S
Symbol
|ILI
|ILI
|ILO
Parameter
Input Leakage Current
Test Conditions
DDQ = Max., VIN = 0V to VDDQ
DDQL = Max. IN = 0V to VDDQL
= VIH or CE
OL = +4mA, VDDQ = Min.
OH = -4mA, VDDQ = Min.
OL = +2mA, VDDQ = Min.
OH = -2mA, VDDQ = Min.
OL = +2mA, VDDQ = Min.
OH = -2mA, VDDQ = Min.
Min.
Max.
10
Unit
µA
µA
µA
V
___
___
___
___
|
V
(1)
|
JTAG & ZZ Input Leakage Current
V
,
V
30
(2)
|
Output Leakage Current
10
CE
0
1 = VIL, VOUT = 0V to VDDQ
V
OL (3.3V) Output Low Voltage
OH (3.3V) Output High Voltage
OL (2.5V) Output Low Voltage
OH (2.5V) Output High Voltage
OL (1.8V) Output Low Voltage
OH (1.8V) Output High Voltage
I
0.4
___
V
I
2.4
V
___
V
I
0.4
V
___
V
I
2.0
V
___
V
I
0.4
V
___
V
I
V
DDQ -0.40
V
7144 tbl 08
NOTES:
1. Applicable only for TMS, TDI and TRST inputs.
2. Outputs tested in tri-state mode.
6.42
10
JULY 7, 2008
FEBRUARY 15, 2008
IDT70P3519/99
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
DC Electrical Characteristics Over the Operating
(3)
Temperature and Supply Voltage Range
(VDD = 1.8V ± 100mV)
70P3519/99
S200
70P3519/99
S166
Com'l Only(8)
Com'l
& Ind(7)
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max. Unit
IDD
Dynamic Operating
Current (Both
Ports Active)
CE
L
and CER= VIL,
S
S
S
S
S
S
S
S
S
S
S
S
226
304
190
258
mA
mA
mA
mA
mA
Outputs Disabled,
___
___
(1)
IND
190
102
102
148
148
15
283
147
172
205
229
45
f = fMAX
I
SB1(6)
Standby Current
(Both Ports - TTL
Level Inputs)
CEL
= CE
R
= VIH
COM'L
IND
120
171
(1)
f = fMAX
___
___
SB2(6)
Standby Current
(One Port - TTL
Level Inputs)
(5)
I
CE"A" = VIL and CE"B" = VIH
COM'L
IND
176
240
Active Port Outputs Disabled,
___
___
(1)
f=fMAX
ISB3
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports CE
CE > VDDQ - 0.2V, VIN > VDDQ - 0.2V
or VIN < 0.2V, f = 0(2)
L and
COM'L
IND
15
45
R
___
___
15
60
SB4(6)
Full Standby Current
(One Port - CMOS
Level Inputs)
(5)
I
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V
IN > VDDQ - 0.2V or VIN < 0.2V
Active Port, Outputs Disabled, f = fMAX
COM'L
IND
176
240
148
148
15
205
229
45
V
___
___
(1)
Izz
Sleep Mode Current
(Both Ports - TTL
Level Inputs)
ZZL = ZZR = VIH
f=fMAX
COM'L
IND
15
45
(1)
mA
___
___
15
60
7144 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS".
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 1.8V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 15mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V
CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH.
7. 166MHz I-Temp is not available in the BF-208 package.
8. 200Mhz is not available in the BF-208 and DR-208 packages.
6.42
11
JULY 7, 2008
IDT70P3519/99
Preliminary
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V/1.8V)
Input Pulse Levels (Address & Controls)
Input Pulse Levels (I/Os)
Input Rise/Fall Times
GND to 3.0V/GND to 2.4V/GND to 1.7V
GND to 3.0V/GND to 2.4V/GND to 1.7V
2ns
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V/1.25V/0.85V
1.5V/1.25V/0.85V
Figure 1
7144 tbl 10
50Ω
50Ω
,
DATAOUT
1.5V/1.25V/0.85V
10pF
(Tester)
7144 drw 03
Figure 1. AC Output Test load.
∆
tCD
(Typical, ns)
7144 drw 04
∆
Capacitance (pF) from AC Test Load
6.42
12
JULY 7, 2008
FEBRUARY 15, 2008
IDT70P3519/99
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing) (2,3) (VDD = 1.8V ± 100mV, TA = 0°C to +70°C)
70P3519/99
S200
70P3519/99
S166
Com'l Only(5)
Com'l
& Ind(4)
Symbol
Parameter
Min.
15
Max.
Min.
Max.
Unit
ns
t
CYC1
CYC2
CH1
CL1
CH2
CL2
SA
HA
SC
HC
SB
HB
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRPT
HRPT
OE
Clock Cycle Time (Flow-Through)(1)
Clock Cycle Time (Pipelined)(1)
Clock High Time (Flow-Through)(1)
Clock Low Time (Flow-Through)(1)
Clock High Time (Pipelined)(2)
20
6
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
5
ns
t
6
8
ns
t
6
8
ns
t
2
2.4
2.4
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
ns
(1)
t
Clock Low Time (Pipelined)
2
ns
t
Address Setup Time
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
ns
t
Address Hold Time
ns
t
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
ns
t
ns
t
ns
t
ns
t
ns
t
R/W Hold Time
ns
t
Input Data Setup Time
Input Data Hold Time
ns
t
ns
t
ns
ADS Setup Time
t
ns
ADS Hold Time
t
ns
CNTEN Setup Time
t
ns
CNTEN Hold Time
t
ns
REPEAT Setup Time
t
0.5
0.5
ns
REPEAT Hold Time
____
____
t
Output Enable to Data Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Clock to Data Valid (Flow-Through)(1)
Clock to Data Valid (Pipelined)(1)
Data Output Hold After Clock High
Clock High to Output High-Z
Clock High to Output Low-Z
Interrupt Flag Set Time
Interrupt Flag Reset Time
Collision Flag Set Time
Collision Flag Reset Time
Sleep Mode Set Cycles
Sleep Mode Recovery Cycles
4.4
4.4
ns
(6)
____
____
t
OLZ
1
1
ns
(6)
OHZ
t
1
3.4
10
1
3.6
12
ns
____
____
t
CD1
CD2
DC
ns
____
____
t
3.4
3.6
ns
____
____
t
1
1
1
1
ns
(6)
CKHZ
t
3.4
3.6
ns
(6)
CKLZ
____
____
t
1
1
ns
____
____
t
INS
INR
COLS
COLR
ZZSC
ZZRC
7
7
7
7
ns
____
____
____
____
____
____
t
ns
t
3.4
3.6
ns
t
3.4
3.6
ns
____
____
t
2
3
2
3
cycles
cycles
____
____
t
Port-to-Port Delay
Clock-to-Clock Offset
____
____
tCO
4
5
ns
Please refer to Collision Detection Timing Table
on Page 22
tOFS
Clock-to-Clock Offset for Collision Detection
7144 tbl 11
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when PL/FTX = VDD (1.8V). Flow-through parameters (tCYC1, tCD1) apply
when PL/FT = Vss (0V) for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), PL/FT and OPT. PL/FT and OPT should be
treated as DC signals, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V/1.8V).
4. 166MHz I-Temp is not available in the BF-208 package.
5. 200Mhz is not available in the BF-208 and DR-208 packages.
6. Guaranteed by design (not production tested).
6.42
13
JULY 7, 2008
IDT70P3519/99
Preliminary
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(1,2)
tCYC2
tCH2
tCL2
CLK
CE
0
t
SC
tHC
t
SC
SB
t
HC
HB
(3)
CE
1
n
t
SB
tHB
t
t
(5)
BE
R/W
t
HW
HA
t
SW
SA
t
t
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
Qn + 1
Qn + 2(5)
(1)
tCKLZ
t
OHZ
tOLZ
OE(1)
,
tOE
7144 drw 05
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(1,2,6)
t
CYC1
t
CH1
t
CL1
CLK
CE
0
t
SC
tHC
t
SC
SB
tHC
(3)
CE
1
t
tHB
tHB
BEn
tSB
R/W
t
SW
SA
t
HW
t
t
HA
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
An + 3
tDC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2(5)
t
CKLZ
tDC
tOHZ
t
OLZ
OE(1)
,
tOE
7144 drw 06
NOTES:
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
6.42
14
JULY 7, 2008
FEBRUARY 15, 2008
IDT70P3519/99
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
(1,2)
Timing Waveform of a Multi-Device Pipelined Read
tCYC2
t
CH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A6
A5
A4
A
3
A
2
A
0
A1
tSC tHC
t
SC
tHC
tCD2
tCD2
tCKHZ
tCD2
Q
0
Q
3
Q1
DATAOUT(B1)
ADDRESS(B2)
tDC
tCKLZ
tDC
tCKHZ
tSA
tHA
A6
A5
A4
A
3
A2
A
0
A1
tSC
tHC
CE0(B2)
tSC
tHC
tCD2
tCKHZ
tCD2
,
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
7144 drw 07
(1,2)
Timing Waveform of a Multi-Device Flow-Through Read
tCYC1
tCH1
tCL1
CLK
tSA
tH
A
A6
A5
A4
A3
A2
A0
A1
ADDRESS(B1)
t
SC
t
HC
CE0(B1)
t
SC
tHC
(1)
tCD1
tCD1
t
CKHZ
tCD1
tCD1
D
0
D
3
D5
D
1
DATAOUT(B1)
ADDRESS(B2)
(1)
(1)
(1)
tDC
tCKLZ
tCKLZ
tDC
t
CKHZ
tSA
tHA
A6
A
5
A4
A3
A2
A
0
A1
t
SC
tHC
CE0(B2)
t
SC
t
HC
(1)
(1)
tCD1
t
CKHZ
tCD1
t
CKHZ
D4
DATAOUT(B2)
D2
(1)
(1)
,
t
CKLZ
tCKLZ
7144 drw 08
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70P3519/99 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. BEn, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.
6.42
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JULY 7, 2008
IDT70P3519/99
Preliminary
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
(1,2,4)
Timing Waveform of Left Port Write to Pipelined Right Port Read
CLK"A"
tSW
tHW
R/W"A
"
tSA
tHA
NO
MATC
H
ADDRESS"A"
DATAIN"A"
MATC
H
t
SD
tHD
VALID
(3)
CO
t
CLK"B"
t
CD2
R/W"B"
tSW
tHW
tSA
t
HA
NO
ADDRESS"B"
DATAOUT"B"
MATC
H
MATCH
VALID
,
t
DC
7144 drw 09
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
(1,2,4)
Timing Waveform with Port-to-Port Flow-Through Read
CLK "A"
t
SW
tHW
R/W "A"
ADDRESS "A"
DATAIN "A"
CLK "B"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(3)
tCO
t
CD1
R/W "B"
tHW
tSW
t
HA
t
SA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
tCD1
VALID
VALID
,
tDC
t
DC
7144 drw 10
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be tCO + tCD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42
16
JULY 7, 2008
FEBRUARY 15, 2008
IDT70P3519/99
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Timing Waveform of Pipelined Read-to-Write-to-Read
(OE = VIL)(2)
t
CYC2
tCH2
tCL2
CLK
CE
CE
BE
0
1
n
t
SC
tHC
t
SB
tHB
tSW tHW
R/W
tSW tHW
(3)
An + 3
An + 4
An
An +1
An + 2
An + 2
ADDRESS
tSA
tHA
tSD
tHD
DATAIN
Dn + 2
tCD2
t
CD2
(1)
t
CKHZ
(4)
tCKLZ
Qn + 3
Qn
DATAOUT
READ
NOP
WRITE
READ
,
7144 drw 11
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled) (2)
t
CYC2
tCH2
tCL2
CLK
CE
0
tSC
tHC
CE1
tSB
tHB
BE
n
tSW tHW
R/W
t
SW tHW
(3)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
t
CD2
tCD2
t
CKLZ
(1)
Qn
Qn + 4
DATAOUT
(4)
tOHZ
OE
READ
WRITE
READ
,
NOTES:
7144 drw 12
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
17
JULY 7, 2008
IDT70P3519/99
Preliminary
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read ( OE = VIL)(2)
t
CYC1
tCH1
tCL1
CLK
CE
0
1
t
SC
tHC
CE
t
SB
tHB
BEn
t
SW tHW
R/
W
t
SW tHW
(3)
An + 4
An
An + 3
An +1
An + 2
An + 2
ADDRESS
t
SA
tHA
t
SD
t
HD
DATAIN
Dn + 2
t
CD1
t
CD1
t
CD1
tCD1
(1)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
t
DC
tDC
tCKLZ
t
CKHZ
NOP(5)
,
READ
WRITE
7144 drw 13
TimingWaveformof Flow-ThroughRead-to-Write-to-Read(OE Controlled)(2)
t
CYC1
t
CH1
tCL1
CLK
CE0
t
SC
tHC
CE1
t
SB
tHB
BEn
t
SW tHW
t
SW tHW
R/
W
ADDRESS(3)
DATAIN
An + 5
An
An + 4
An +1
An + 2
An + 3
Dn + 3
t
SA
tHA
t
SD tHD
Dn + 2
t
OE
t
DC
t
CD1
t
CD1
t
CD1
(1)
Qn + 4
Qn
DATAOUT
t
CKLZ
t
DC
t
OHZ
OE
,
READ
WRITE
READ
7144 drw 14
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
18
JULY 7, 2008
FEBRUARY 15, 2008
IDT70P3519/99
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
(1)
Timing Waveform of Pipelined Read with Address Counter Advance
tCYC2
tCH2
tCL2
CLK
t
SA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
CNTEN
t
SCN tHCN
tCD2
,
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 3
Qn + 1
Qn
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
7144 drw 15
TimingWaveformof Flow-ThroughReadwithAddressCounterAdvance (1)
t
CYC1
t
CH1
tCL1
CLK
t
SA
tHA
An
ADDRESS
t
SAD tHAD
t
SAD
t
HAD
ADS
t
SCN
t
HCN
CNTEN
t
CD1
,
Qn + 3(2)
Qx(2)
Qn + 4
Qn + 1
Qn + 2
Qn
DATAOUT
t
DC
READ
WITH
COUNTER
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
7144 drw 16
NOTES:
1. CE0, OE, BEn = VIL; CE1, R/W, and REPEAT = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.42
19
JULY 7, 2008
IDT70P3519/99
Preliminary
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(1)
(Flow-through or Pipelined Inputs)
t
CYC2
tCH2
tCL2
CLK
t
SA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 1
An + 3
An + 4
An + 2
t
SAD tHAD
ADS
t
SCN
t
HC
N
CNTEN
t
SD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
,
7144 drw 17
(2,6)
Timing Waveform of Counter Repeat
t
CYC2
CLK
t
SA tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An+2
An+1
An+2
An+2
An
An
An+1
An+2
t
SAD tHAD
ADS
tSW tHW
R/
W
t
SCN tHCN
CNTEN
(4)
REPEAT
SRPT tHRPT
t
,
t
SD
t
HD
D3
D2
D
0
D1
DATAIN
tCD1
An
An+1
An+2
An+2
HOLD
DATAOUT
,
ADVANCE
COUNTER
WRITE TO
An+2
ADVANCE
COUNTER
WRITE TO
An+1
HOLD
REPEAT
READ LAST
ADS
ADDRESS
An
ADVANCE
COUNTER
READ
WRITE TO
ADS
ADDRESS
An
ADVANCE
COUNTER
READ
COUNTER
WRITE TO
An+2
COUNTER
READ
An+1
An+2
An+2
7144 drw 18
NOTES:
1. CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.
CE0, BEn = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.
5. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
6.42
20
JULY 7, 2008
FEBRUARY 15, 2008
IDT70P3519/99
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Waveform of Interrupt Timing (2)
CLK
L
tSW
tHW
R/W
L
t
SA
3FFFF
SC
t
HA
ADDRESSL(3)
CEL(1)
t
t
HC
t
INS
INT
R
t
INR
CLK
R
tSC
tHC
CER(1)
R/WR
t
SW
SA
3FFFF
t
HW
t
HA
t
ADDRESSR(3)
7144 drw 19
NOTES:
1. CE0 = VIL and CE1 = VIH
2. All timing is the same for Left and Right ports.
3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Truth Table III — Interrupt Flag (1)
Left Port
Right Port
(2)
(2)
(3,4)
(2)
(2)
(3,4)
CLK
L
R/W
L
CE
L
A
17L-A0L
CLK
R
R/W
R
CE
R
A
17R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
INT
X
L
INTR
↑
↑
↑
↑
L
X
X
H
L
3FFFF
X
↑
↑
↑
↑
X
H
L
X
L
L
X
X
L
R
X
X
L
X
3FFFF
3FFFE
X
H
X
X
R
X
L
L
3FFFE
H
X
L
7144 tbl 12
NOTES:
1. INTL and INTR must be initialized at power-up by Resetting the flags.
2. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
3. A17X is a NC for IDT70T3599, therefore Interrupt Addresses are 1FFFF and 1FFFE.
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
21
JULY 7, 2008
IDT70P3519/99
Preliminary
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Collision Timing(1,2)
BothPorts Writing with Left Port Clock Leading
CLK
L
tOFS
tSA tHA
ADDRESS(4)
L
A
3
A
2
A1
A0
tCOLR
tCOLS
COL
L
(3)
tOFS
CLK
R
tSA
tHA
(4)
ADDRESS
R
A3
A
2
A0
A1
tCOLR
tCOLS
COL
R
7144 drw 20
NOTES:
1. CE0 = VIL, CE1 = VIH.
2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3. Leading Port Output flag might output 3tCYC2 + tCOLS after Address match.
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Collision Detection Timing(3,4)
tOFS (ns)
Cycle Time
NOTES:
1. Region 1
Region 1 (ns) (1)
Region 2 (ns) (2)
Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.
2. Region 2
Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.
while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.
3. All the production units are tested to midpoint of each region.
5ns
6ns
0 - 2.8
2.81 - 4.6
0 - 3.8
0 - 5.3
3.81 - 5.6
5.31 - 7.1
7.5ns
4. These ranges are based on characterization of a typical device.
7144 tbl 13
Truth Table IV — Collision Detection Flag
Left Port
Right Port
(1)
(1)
(2)
(1)
(1)
(2)
CLK
L
R/W
L
CE
L
A
17L-A0L
CLK
R
R/W
R
CE
R
A
17R-A0R
Function
COL
H
L
COL
R
Both ports reading. Not a valid collision.
No flag output on either port.
↑
↑
↑
H
H
L
L
L
L
L
L
MATCH
MATCH
MATCH
MATCH
↑
↑
↑
↑
H
L
MATCH
MATCH
MATCH
MATCH
H
Left port reading, Right port writing.
Valid collision, flag output on Left port.
L
L
H
L
L
L
L
H
Right port reading, Left port writing.
Valid collision, flag output on Right port.
H
L
Both ports writing. Valid collision. Flag
output on both ports.
↑
L
L
7144 tbl 14
NOTES:
1. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
22
JULY 7, 2008
FEBRUARY 15, 2008
IDT70P3519/99
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Timing Waveform - Entering Sleep Mode (1,2)
R/W
(3)
Timing Waveform - Exiting Sleep Mode (1,2)
An
An+1
(5)
R/W
OE
(5)
Dn
Dn+1
DATAOUT
(4)
NOTES:
1. CE1 = VIH.
2. All timing is same for Left and Right ports.
3. CE0 has to be deactivated (CE0 = VIH) three cycles prior to asserting ZZ (ZZx = VIH) and held for two cycles after asserting ZZ (ZZx = VIH).
4. CE0 has to be deactivated (CE0 = VIH) one cycle prior to de-asserting ZZ (ZZx = VIL) and held for three cycles after de-asserting ZZ (ZZx = VIL).
5. The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.
6.42
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JULY 7, 2008
IDT70P3519/99
Preliminary
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
alertflagasappropriate.Intheeventthatauserinitiatesaburstaccess
onbothportswiththesamestartingaddressonbothportsandoneorboth
portswritingduringeachaccess(i.e.,imposesalongstringofcollisions
on contiguous clock cycles), the alert flag will be asserted and cleared
everyothercycle.PleaserefertotheCollisionDetectiontimingwaveform
on Page 21.
FunctionalDescription
The IDT70P3519/99 provides a true synchronous Dual-Port Static
RAM interface.Registeredinputsprovideminimalset-upandholdtimes
onaddress,data,andallcriticalcontrolinputs.Allinternalregistersare
clocked on the rising edge of the clock signal, however, the self-timed
internalwritepulsewidthisindependentofthecycletime.
Collision detection on the IDT70P3519/99 represents a significant
advanceinfunctionalityovercurrentsyncmulti-ports,whichhavenosuch
capability. InadditiontothisfunctionalitytheIDT70P3519/99sustainsthe
keyfeaturesofbandwidthandflexibility. Thecollisiondetectionfunction
isveryusefulinthecaseofburstingdata,orastringofaccessesmadeto
sequentialaddresses,inthatitindicatesaproblemwithintheburst,giving
theusertheoptionofeitherrepeatingtheburstorcontinuingtowatchthe
alert flag to see whether the number of collisions increases above an
acceptablethresholdvalue.Offeringthisfunctiononchipalsoallowsusers
to reduce their need for arbitration circuits, typically done in CPLD’s or
FPGA’s.Thisreducesboardspaceanddesigncomplexity,andgivesthe
usermoreflexibilityindevelopingasolution.
An asynchronous output enable is provided to ease asyn-
chronousbusinterfacing.Counterenableinputsarealsoprovidedtostall
the operation of the address counters for fast interleaved
memoryapplications.
AHIGHonCE0oraLOWonCE1foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70P3519/99 for depth
expansionconfigurations. Twocycles arerequiredwithCE0 LOWand
CE1HIGHtore-activatetheoutputs.
Interrupts
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)isassignedtoeachport. Theleftportinterrupt
flag (INTL) is asserted when the right port writes to memory location
3FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
addresslocation3FFFEwhenCEL= VIL andR/WL=VIH.Likewise,the
right port interrupt flag (INTR) is asserted when the left
port writes to memory location 3FFFF (HEX) and to clear the interrupt
flag(INTR),therightportmustreadthememorylocation3FFFF(1FFFF
or1FFFEforIDT70P3599).Themessage(36bits)at3FFFEor3FFFF
(1FFFF or 1FFFE for IDT70P3599) is user-defined since it is an
addressableSRAMlocation.Iftheinterruptfunctionisnotused,address
locations3FFFEand3FFFF(1FFFFor1FFFEforIDT70P3599)arenot
usedasmailboxes,butaspartoftherandomaccessmemory.Referto
TruthTable III forthe interruptoperation.
SleepMode
TheIDT70P3519/99isequippedwithanoptionalsleeporlowpower
modeonbothports.Thesleepmodepinonbothportsisasynchronous
andactivehigh.Duringnormaloperation,theZZpinispulledlow.When
ZZispulledhigh,theportwillentersleepmodewhereitwillmeetlowest
possible power conditions. The sleep mode timing diagram shows the
modes ofoperation:NormalOperation,NoRead/WriteAllowedandSleep
Mode.
Fornormaloperationallinputsmustmeetsetupandholdtimesprior
tosleepand afterrecoveringfromsleep.Clocksmustalsomeetcyclehigh
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx=VIH)andthreecyclesafterde-assertingZZ(ZZx=VIL),thedevice
mustbedisabledviathechipenablepins.Ifawriteorreadoperationoccurs
duringtheseperiods,thememoryarraymaybecorrupted.Validityofdata
outfromtheRAMcannotbeguaranteedimmediatelyafterZZisasserted
(priortobeinginsleep).Whenexitingsleepmode,thedevicemustbein
Read mode (R/Wx = VIH)when chip enable is asserted, and the chip
enablemustbevalidforonefullcyclebeforeareadwillresultintheoutput
ofvaliddata.
DuringsleepmodetheRAMautomaticallydeselectsitself.TheRAM
disconnectsitsinternalclockbuffer.Theexternalclockmaycontinuetorun
withoutimpactingtheRAMssleepcurrent(IZZ).Alloutputswillremainin
high-Zstatewhileinsleepmode.Allinputsareallowedtotoggle.TheRAM
will not be selected and will not perform any reads or writes.
CollisionDetection
Collision is defined as an overlap in access between the two ports
resulting in the potential for either reading or writing incorrect data to a
specificaddress. Forthespecificcases:(a)Bothportsreading-nodata
iscorrupted,lost,orincorrectlyoutput,sonocollisionflagisoutputoneither
port.(b)Oneportwriting,theotherportreading-theendresultofthewrite
willstillbevalid. However,thereadingportmightcapturedatathatisin
astateoftransitionandhencethereadingport’scollisionflagisoutput.(c)
Bothportswriting-thereisariskthatthetwoportswillinterferewitheach
other,andthedatastoredinmemorywillnotbeavalidwritefromeither
port(itmayessentiallybearandomcombinationofthetwo). Therefore,
thecollisionflagisoutputonbothports. PleaserefertoTruthTableIVfor
alloftheabovecases.
Thealertflag (COLx)isassertedonthe2ndor3rdrisingclockedge
oftheaffectedportfollowingthecollision,andremainslowforonecycle.
PleaserefertoCollisionDetectionTimingtableonPage21.Duringthat
nextcycle,theinternalarbitrationisengagedinresettingthealertflag(this
avoidsaspecificrequirementonthepartoftheusertoresetthealertflag).
Iftwocollisionsoccuronsubsequentclockcycles,thesecondcollisionmay
notgeneratetheappropriatealertflag.Athirdcollisionwillgeneratethe
6.42
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JULY 7, 2008
FEBRUARY 15, 2008
IDT70P3519/99
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Depth andWidth Expansion
The IDT70P3519/99 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70P3519/99 can also be used in applications requiring
expandedwidth,asindicatedinFigure4.Throughcombiningthecontrol
signals, the devices can be grouped as necessary to accommodate
applicationsneeding72-bitsorwider.
A
18/A17
IDT70P3519/99
IDT70P3519/99
CE0
CE0
CE1
CE1
V
DD
VDD
Control Inputs
Control Inputs
IDT70P3519/99
IDT70P3519/99
CE1
CE1
CE0
CE0
BE,
R/W,
Control Inputs
Control Inputs
OE,
7144 drw 23
CLK,
ADS,
REPEAT,
CNTEN
Figure 4. Depth and Width Expansion with IDT70P3519/99
,
NOTE:
1. A18 is for IDT70P3519, A17 is for IDT70P3599.
6.42
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JULY 7, 2008
IDT70P3519/99
Preliminary
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
JTAGTimingSpecifications
t
JR
JCYC
t
t
JF
t
JCL
tJCH
TCK
Device Inputs(1)
TDI/TMS
/
t
JDC
t
JS
tJH
Device Outputs(2)
TDO
/
tJRSR
tJCD
TRST
,
7144 drw 24
t
JRST
Figure 5. Standard JTAG Timing
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4)
70P3519/99
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
____
____
t
ns
t
40
ns
(1)
____
t
3
ns
(1)
____
t
3
ns
____
____
t
50
ns
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
____
t
25
ns
____
t
0
ns
____
____
t
15
15
ns
t
JTAG Hold
ns
7144 tbl 15
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
6.42
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JULY 7, 2008
FEBRUARY 15, 2008
IDT70P3519/99
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
0x0
Reserved for version number
0x380(1)
0x33
1
IDT Device ID (27:12)
Defines IDT part number
IDT JEDEC ID (11:1)
Allows unique identification of device vendor as IDT
Indicates the presence of an ID register
ID Register Indicator Bit (Bit 0)
7144 tbl 16
NOTE:
1. Device ID for IDT70P3599 is 0x383.
ScanRegisterSizes
Register Name
Bit Size
Instruction (IR)
4
1
Bypass (BYR)
Identification (IDR)
32
Boundary Scan (BSR)
Note (3)
7144 tbl 17
SystemInterfaceParameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
IDCODE
1111
Places the bypass register (BYR) between TDI and TDO.
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state except COLx & INTx outputs.
HIGHZ
CLAMP
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
0011
0001
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.
RESERVED
PRIVATE
0101, 0111, 1000, 1001,
1010, 1011, 1100
Several combinations are reserved. Do not use codes other than those
identified above.
0110,1110,1101
For internal use only.
7144 tbl 18
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
6.42
27
JULY 7, 2008
IDT70P3519/99
Preliminary
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
XXXXX
A
999
A
A
A
IDT
Device
Type
Power Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
G(3)
Green
BC
DR
BF
256-pin BGA (BC-256)
208-pin PQFP (DR-208)
208-pin fpBGA (BF-208)
Commercial Only(2)
200
166
Speed in Megahertz
Commercial & Industrial(1)
Standard Power
S
70P3519
70P3599
9Mbit (256K x 36) 2.5V Synchronous Dual-Port RAM
4Mbit (128K x 36) 2.5V Synchronous Dual-Port RAM
NOTES:
7144 drw 25
1. 166MHz I-Temp is only available in the BC-256 package.
2. 200Mhz is only available in the BC-256 package.
3. Green parts available. For specific speeds, packages and powers contact your local sales office.
IDT Clock Solution for IDT70P3519/99 Dual-Port
Dual-Port I/O Specifications
Clock Specifications
Input Duty
Cycle
IDT
PLL
Clock Device
IDT
Non-PLL
Clock Device
IDT Dual-Port
Part Number
Input
Capacitance
Maximum
Frequency Tolerance
Jitter
Voltage
I/O
Requirement
5T2010
5T9010
5T905, 5T9050
5T907, 5T9070
70P3519/99
2.5
LVTTL
3.5-6pF
40%
200
75ps
7144 tbl 19
PreliminaryDatasheet: Definition
"PRELIMINARY'datasheetscontaindescriptionsforproductsthatareinearlyrelease.
DatasheetDocumentHistory:
07/07/08:
InitialDatasheet
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DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
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JULY 7, 2008
FEBRUARY 15, 2008
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