IDT70T3539MS133BCI8 [IDT]
Dual-Port SRAM, 512KX36, 15ns, CMOS, PBGA256, BGA-256;
| 型号： | IDT70T3539MS133BCI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 512KX36, 15ns, CMOS, PBGA256, BGA-256 静态存储器 |
| 文件： | 总26页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 2.5V
512K x 36
SYNCHRONOUS
IDT70T3539M
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆
– Data input, address, byte enable and control registers
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 6ns cycle time, 166MHzoperation(12Gbps bandwidth)
– Fast 3.6ns clock to data out
– Self-timedwriteallowsfastcycletime
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
Includes JTAG functionality
Industrial temperature range (-40°C to +85°C) is
available at 133MHz
◆
Available in a 256-pin Ball Grid Array (BGA)
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
FunctionalBlockDiagram
BE3R
BE3L
BE2L
BE1L
BE0L
BE2R
BE1R
BE0R
FT/PIPE
L
0a 1a
a
0b 1b
b
0c 1c
c
0d 1d
d
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
a
FT/PIPER
1/0
1/0
R/WL
R/WR
CE0L
CE0R
1
1
CE1R
CE1L
0
0
B
B B B
B
B B B
1/0
1/0
W W W W W W W W
0
L
1
L
2
L
3
L
3
R
2
1
R
0
R
R
OE
R
OE
L
Dout0-8_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
Dout9-17_L
Dout18-26_L
Dout27-35_L
,
1d 0d 1c 0c
1b 0b 1a 0a
0a 1a 0b 1b
0c 1c 0d 1d
d c b a
0/1
0/1
FT/PIPE
R
FT/PIPE
L
a bc d
512K x 36
MEMORY
ARRAY
I/O0L - I/O35L
I/O0R - I/O35R
Din_L
Din_R
,
CLK
R
CLK
L
A
18R
A
18L
Counter/
Address
Reg.
Counter/
Address
Reg.
A
0L
REPEAT
ADS
CNTEN
A
0R
REPEAT
ADS
CNTEN
ADDR_R
ADDR_L
L
R
R
L
R
L
TDI
TCK
TMS
TRST
INTERRUPT
CE
CE1
0
R
CE
0
L
JTAG
COLLISION
DETECTION
LOGIC
R
CE1
TDO
L
R/
W
L
R/W
R
COL
L
COL
R
INT
L
INT
R
(1)
(1)
ZZR
ZZ
CONTROL
LOGIC
ZZ
L
5678 drw 01
NOTE:
1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx and
the sleep mode pins themselves (ZZx) are not affected during sleep mode.
JULY 2008
1
DSC 5678/6
©2008IntegratedDeviceTechnology,Inc.
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Description:
TheIDT70T3539Misahigh-speed512Kx36bitsynchronousDual- inbursts.Anautomaticpowerdownfeature,controlledbyCE0andCE1,
Port RAM. The memory array utilizes Dual-Port memory cells to allow permitstheon-chipcircuitryofeachporttoenteraverylowstandbypower
simultaneousaccessofanyaddressfrombothports.Registersoncontrol, mode.
data,andaddressinputsprovideminimalsetupandholdtimes.Thetiming
The 70T3539M can support an operating voltage of either 3.3V or
latitudeprovidedbythisapproachallowssystemstobedesignedwithvery 2.5Vononeorbothports,controllablebytheOPTpins.Thepowersupply
shortcycletimes.Withaninputdataregister,theIDT70T3539Mhasbeen for the core of the device (VDD) is at 2.5V.
optimizedforapplicationshavingunidirectionalorbidirectionaldataflow
6.42
2
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration (1,2,3,4)
70T3539M BC
BC-256(5)
256-Pin BGA
Top View(6)
10/07/03
A1
A2
A3
A6
A7
A8
A9
A11
A12
A13
A14
A4
A5
A10
A15
A16
NC
TDI
NC
A
11L
A
8L
9L
7L
BE2L CE1L
CNTEN
L
L
A
5L
A
2L
A
0L
A
17L
18L
A
14L
OE
L
NC
NC
B1
B2
B3
B6
B7
B9
CE0L
B11
B12
B13
B4
B5
B8
B10
B14
B15
B16
I/O18L NC TDO
A
12L
A
REPEAT
A4L
A
1L
A
A
15L
BE3L
R/W
L
VDD I/O17L NC
C1
C5
C6
C2
C3
C4
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
I/O18R
A
13L
A
10L
I/O19L
V
SS
A
BE1L BE0L CLK
L
ADS
L
A6L
A
3L
I/O16L
A16L
OPT
L
I/O17R
D1
D2
D6
D9
D11
D3
D5
D7
D8
D10
D12
D13
D14
D15
D16
D4
I/O20R I/O19R
VDDQL
VDDQL
VDDQR
VDDQL
I/O20L
V
PIPE/FTL
DDQL
V
DDQR
VDDQR
VDDQR
VDD I/O15R I/O15L I/O16R
E6
E5
E7
E8
E9
E10
E11
E12
E13
E1
E2
E3
E4
E14
E16
E15
V
DD
V
DD
INT
L
V
SS
SS
SS
V
SS
SS
SS
V
SS
V
DD
V
DD
V
DDQR
I/O13L
I/O21R I/O21L I/O22L
V
DDQL
I/O14R
I/O14L
F7
F1 F2 F3
F5
F6
F9
F10
F14
F15
F16
F11
F13
F4
F8
F12
COL
L
VDD
NC
V
VSS
I/O23L I/O22R I/O23R
G1
VSS
V
DDQR I/O12R I/O13R I/O12L
V
V
DD
VDDQL
G5
H5
G2
G4
G6
G8
G9
G3
G7
G10
G12
G13 G14 G15 G16
G11
I/O24R
V
SS
I/O24L
V
DDQR
VSS
V
V
I/O25L
I/O10L I/O11L I/O11R
H16
VSS
VSS
VSS
V
DDQL
VSS
H11
H12
H13
H7
H8
H9
H10
H14
H15
H3
H4
H6
H1
H2
VSS
V
SS
VDDQL
I/O10R
VSS
VSS
VSS
V
SS
I/O9R IO9L
VSS
VSS
I/O26R
V
DDQR
I/O26L I/O25R
J1
J2
J3
J4
J5
J6
J7
J8
J9
J13
J10
J11
J12
J14
J15
J16
I/O27L
I/O28R I/O27R
V
DDQL ZZ
R
V
SS
V
SS
V
SS
SS
V
SS
V
DDQR
I/O8R
V
SS
V
SS
ZZ
L
I/O7R I/O8L
K6
K8
K10
K12
K13
K5
K7
K9
K11
K2
K4
K15
K16
K1
K3
K14
VSS
V
VSS
V
SS
V
DDQR
I/O6R
I/O29L
V
DDQL
V
SS
V
SS
V
SS
V
SS
I/O6L I/O7L
I/O29R
I/O28L
L7
L8
L11
L12
L13
L3
L4
L5
L6
L9
L10
L15
L16
L1
L2
L14
COLR
V
SS
VSS
V
DD
V
DDQL
I/O30R
VDDQR
VDD
NC
V
SS
V
SS
I/O4R I/O5R
I/O30L I/O31R
I/O5L
M5
M6
M7
M8
M9
M10
M11
M12
M13
M1 M2
M3
M4
M16
M14
M15
VDD
V
DD INT
R
V
SS
V
SS
VSS
VDD
V
DD
V
DDQL
I/O3R I/O3L
I/O32R I/O32L I/O31L
V
DDQR
I/O4L
N8
N12
N16
N13
N4
N5
N6
N7
N9
N10
N11
N15
N1
N2
N3
N14
VDDQL
VDDQL
VDD
I/O2R
P IP E /FT
R
V
DDQR
VDDQR
VDDQL
V
DDQR
V
DDQR
VDDQL
I/O1R
I/O33L I/O34R I/O33R
I/O2L
P1
P2
P3
P4
P5
P7
P8
P9
P10
P11
P12
P14
P15
P16
P6
P13
A
16R
I/O35R I/O34L TMS
A
13R
A
7R BE1R BE0R CLK
R
ADS
R
A
6R
4R
5R
I/O0L I/O0R I/O1L
A
10R
A
3R
R5
R6
R7
R8 R9 R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R15
,
A
15R
A
12R
A
9R
BE3R CE0R R/W
R
REPEAT
R
NC
I/O35L NC TRST
A
18R
A
A1R OPTR
NC
T2
T3
T4
T1
T5
T8
T9
T15
T16
T6
T7
T10
T11
T12
T13
T14
A
17R
TCK
NC
NC
A
14R
BE2R CE1R
NC
NC
A11R
A
8R
OER
CNTEN
R
A
A
2R
A
0R
5678 drw 02d
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
,
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
3
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
CE1R
Names
(5)
Chip Enables (Input)
CE0L
R/W
OE
,
CE1L
CE0R
R/W
OE
,
L
R
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
L
R
A0L - A18L
A0R - A18R
I/O0L - I/O35L
CLK
PL/FT
ADS
CNTEN
REPEAT
BE0L - BE3L
I/O0R - I/O35R
CLK
Data Input/Output
L
R
Clock (Input)
L
PL/FT
ADS
CNTEN
REPEAT
BE0R - BE3R
R
Pipeline/Flow-Through (Input)
Address Strobe Enable (Input)
Counter Enable (Input)
Counter Repeat(3)
L
R
L
R
L
R
(5)
Byte Enables (9-bit bytes) (Input)
Power (I/O Bus) (3.3V or 2.5V)(1) (Input)
Option for selecting VDDQX(1,2) (Input)
Sleep Mode pin(4) (Input)
Power (2.5V)(1) (Input)
VDDQL
VDDQR
OPT
ZZ
L
OPTR
L
ZZR
V
DD
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
V
SS
Ground (0V) (Input)
TDI
TDO
TCK
TMS
TRST
Test Data Input
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)
Interrupt Flag (Output)
3. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
INT
R
INTL
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundry scan not be operated during sleep mode.
COL
R
COL
L
Collision Alert (Output)
5678 tbl 01
5. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
6.42
4
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
(1,2,3,4)
Truth Table I—Read/Write and Enable Control
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
CLK
CE
1
R/W
X
X
X
L
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
MODE
OE
X
X
X
X
X
X
X
X
X
X
L
CE
0
BE
3
BE
2
BE
1
BE0
↑
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
L
X
X
H
H
H
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z Deselected–Power Down
High-Z Deselected–Power Down
High-Z All Bytes Deselected
↑
↑
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
↑
DIN
Write to Byte 0 Only
↑
H
H
H
L
L
DIN
High-Z Write to Byte 1 Only
High-Z Write to Byte 2 Only
High-Z Write to Byte 3 Only
↑
H
H
L
L
DIN
High-Z
High-Z
↑
H
H
L
L
D
IN
High-Z
High-Z
↑
H
L
L
High-Z
DIN
DIN
Write to Lower 2 Bytes Only
↑
H
L
H
L
L
DIN
DIN
High-Z
High-Z Write to Upper 2 bytes Only
↑
L
L
L
DIN
DIN
DIN
D
IN
Write to All Bytes
Read Byte 0 Only
↑
H
H
H
L
H
H
L
H
L
L
H
H
H
H
H
H
H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
↑
L
H
H
H
L
DOUT
High-Z Read Byte 1 Only
High-Z Read Byte 2 Only
High-Z Read Byte 3 Only
↑
L
H
H
L
DOUT
High-Z
High-Z
↑
L
H
H
L
D
OUT
High-Z
High-Z
↑
L
H
L
High-Z
DOUT
D
OUT
Read Lower 2 Bytes Only
High-Z Read Upper 2 Bytes Only
Read All Bytes
↑
L
H
L
H
L
DOUT
DOUT
High-Z
↑
L
L
L
DOUT
DOUT
DOUT
DOUT
↑
H
X
X
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z Outputs Disabled
High-Z Sleep Mode
X
5678 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = VIH.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
(1,2)
Truth Table II—Address Counter Control
Previous
Internal
Address
Internal
Address
Used
MODE
(3)
ADS CNTEN REPEAT(6)
Address
CLK
↑
I/O
I/O (n) External Address Used
I/O(n+1) Counter Enabled—Internal Address generation
I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
DI/O(n) Counter Set to last valid ADS load
(4)
An
X
X
An
An
L
H
H
X
X
H
H
D
(5)
↑
An + 1
An + 1
An
L
H
X
D
↑
X
An + 1
X
H
D
(4)
↑
X
L
5678 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
6.42
5
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
RecommendedOperating
Temperature and Supply Voltage
(1)
Ambient
Grade
Temperature
0OC to +70OC
-40OC to +85OC
GND
VDD
Commercial
0V
2.5V
2.5V
+
+
100mV
100mV
Industrial
0V
5678 tbl 04
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
RecommendedDCOperating
Conditions with VDDQ at 2.5V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min.
2.4
2.4
0
Typ.
2.5
2.5
0
Max.
Unit
V
V
DD
DDQ
SS
2.6
2.6
0
V
V
V
V
Input High Volltage
(Address, Control &
Data I/O Inputs)(3)
(2)
____
V
DDQ + 100mV
1.7
1.7
V
V
V
IH
Input High Voltage _
JTAG
(2)
____
VIH
VDD + 100mV
Input High Voltage -
ZZ, OPT, PIPE/FT
(2)
____
____
____
V
IH
IL
IL
V
DD - 0.2V
V
DD + 100mV
V
V
V
Input Low Voltage
-0.3(1)
0.7
0.2
Input Low Voltage -
ZZ, OPT, PIPE/FT
V
-0.3(1)
V
5678 tbl 05a
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT
pinforthatportmustbesettoVss(0V),andVDDQX forthatportmustbesuppliedas indicated
above.
RecommendedDCOperating
Conditions with VDDQ at 3.3V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min.
2.4
3.15
0
Typ.
2.5
3.3
0
Max.
2.6
3.45
0
Unit
V
V
DD
DDQ
SS
V
V
V
V
Input High Voltage
(Address, Control
(3)
&Data I/O Inputs)
(2)
____
2.0
1.7
V
DDQ + 150mV
V
V
V
IH
_
Input High Voltage
JTAG
(2)
____
VIH
VDD + 100mV
Input High Voltage -
ZZ, OPT, PIPE/FT
(2)
____
____
____
V
IH
IL
IL
V
DD - 0.2V
V
DD + 100mV
V
V
V
Input Low Voltage
-0.3(1)
0.8
0.2
Input Low Voltage -
ZZ, OPT, PIPE/FT
V
-0.3(1)
V
5678 tbl 05b
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin
for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied as indicated
above.
6.42
6
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings (1)
Symbol
Rating
Commercial
& Industrial
Unit
V
V
TERM
VDD Terminal Voltage
-0.5 to 3.6
(VDD
)
with Respect to GND
(2)
TERM
V
V
DDQ Terminal Voltage
-0.3 to VDDQ + 0.3
-0.3 to VDDQ + 0.3
V
(VDDQ
)
with Respect to GND
(2)
TERM
V
Input and I/O Terminal
V
(INPUTS and I/O's)
Voltage with Respect to GND
(3)
T
BIAS
STG
JN
Temperature Under Bias
Storage Temperature
Junction Temperature
-55 to +125
-65 to +150
+150
oC
oC
T
T
oC
IOUT(For VDDQ = 3.3V) DC Output Current
50
mA
IOUT(For VDDQ = 2.5V) DC Output Current
40
mA
5678 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its
nominal operating value. Power sequencing is not necessary; however, the voltage on
any Input or I/O pin cannot exceed VDDQ during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max. Unit
CIN
VIN = 3dV
15
pF
(3)
OUT
C
VOUT = 3dV
10.5
pF
5678 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T3539MS
Symbol
|ILI
|ILI
|ILO
Parameter
Test Conditions
DDQ = Max., VIN = 0V to VDDQ
DD = Max. IN = 0V to VDD
CE = VIH or CE = VIL, VOUT = 0V to VDDQ
OL = +4mA, VDDQ = Min.
OH = -4mA, VDDQ = Min.
OL = +2mA, VDDQ = Min.
OH = -2mA, VDDQ = Min.
Min.
Max.
10
Unit
µA
µA
µA
V
(1)
___
___
___
___
|
Input Leakage Current
V
(1,2)
|
JTAG & ZZ Input Leakage Current
V
,
V
±30
10
(1,3)
|
Output Leakage Current
0
1
V
OL (3.3V) Output Low Voltage(1)
OH (3.3V) Output High Voltage(1)
OL (2.5V) Output Low Voltage(1)
OH (2.5V) Output High Voltage(1)
I
0.4
___
V
I
2.4
V
___
V
I
0.4
V
___
V
I
2.0
V
5678 tbl 08
NOTES:
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
6.42
7
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
(3)
Temperature and Supply Voltage Range
(VDD = 2.5V ± 100mV)
70T3539MS166 70T3539MS133
Com'l Only
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
640
Max.
900
Typ.(4)
Max. Unit
IDD
Dynamic Operating
Current (Both
Ports Active)
CE
L
and CER= VIL,
S
S
S
S
S
S
S
S
S
S
S
S
520
520
280
280
400
400
12
740
mA
900
Outputs Disabled,
___
___
(1)
IND
f = fMAX
I
SB1(6)
Standby Current
(Both Ports - TTL
Level Inputs)
CE
f = fMAX
L
= CE
R
= VIH
COM'L
IND
350
460
380
mA
470
(1)
___
___
SB2(6)
Standby Current
(One Port - TTL
Level Inputs)
(5)
I
CE"A" = VIL and CE"B" = VIH
COM'L
IND
500
650
500
mA
620
Active Port Outputs Disabled,
___
___
(1)
f=fMAX
ISB3
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports CE
CE > VDDQ - 0.2V, VIN > VDDQ - 0.2V
or VIN < 0.2V, f = 0
L and
COM'L
IND
12
20
20
R
mA
25
___
___
(2)
12
SB4(6)
Full Standby Current
(One Port - CMOS
Level Inputs)
(5)
I
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V
IN > VDDQ - 0.2V or VIN < 0.2V
Active Port, Outputs Disabled, f = fMAX
COM'L
IND
500
650
400
400
12
500
mA
620
V
___
___
(1)
Izz
Sleep Mode Current
(Both Ports - TTL
Level Inputs)
ZZL = ZZR = VIH
f=fMAX
COM'L
IND
12
20
20
(1)
mA
25
___
___
12
5678 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS".
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 2.5V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 30mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V
CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH.
6.42
8
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels (Address & Controls)
Input Pulse Levels (I/Os)
Input Rise/Fall Times
GND to 3.0V/GND to 2.4V
GND to 3.0V/GND to 2.4V
2ns
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V/1.25V
1.5V/1.25V
Figure 1
5678 tbl 10
50Ω
50Ω
,
DATAOUT
1.5V/1.25
10pF
(Tester)
5678 drw 03
Figure 1. AC Output Test load.
∆
tCD
(Typical, ns)
5678 drw 04
∆
Capacitance (pF) from AC Test Load
6.42
9
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing) (2,3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C)
70T3539MS166
Com'l Only
70T3539MS133
Com'l
& Ind
Symbol
Parameter
Min.
20
Max.
Min.
25
Max.
Unit
ns
t
CYC1
CYC2
CH1
CL1
CH2
CL2
SA
HA
SC
HC
SB
HB
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRPT
HRPT
OE
Clock Cycle Time (Flow-Through)(1)
Clock Cycle Time (Pipelined)(1)
Clock High Time (Flow-Through)(1)
Clock Low Time (Flow-Through)(1)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(1)
Address Setup Time
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
6
7.5
10
ns
t
8
ns
t
8
10
ns
t
2.4
2.4
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
3
ns
t
3
ns
t
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
ns
t
Address Hold Time
ns
t
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
ns
t
ns
t
ns
t
ns
t
ns
t
R/W Hold Time
ns
t
Input Data Setup Time
ns
t
Input Data Hold Time
ns
t
ns
ADS Setup Time
t
ns
ADS Hold Time
t
ns
CNTEN Setup Time
t
ns
CNTEN Hold Time
t
ns
REPEAT Setup Time
t
0.5
0.5
ns
REPEAT Hold Time
____
____
t
Output Enable to Data Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Clock to Data Valid (Flow-Through)(1)
Clock to Data Valid (Pipelined)(1)
Data Output Hold After Clock High
Clock High to Output High-Z
Clock High to Output Low-Z
Interrupt Flag Set Time
4.4
4.6
ns
(6)
____
____
t
OLZ
1
1
ns
(6)
OHZ
t
1
3.6
12
1
4.2
15
ns
____
____
t
CD1
CD2
DC
ns
____
____
t
3.6
4.2
ns
____
____
t
1
1
1
1
ns
(6)
CKHZ
t
3.6
4.2
ns
(6)
CKLZ
____
____
t
1
1
ns
____
____
t
INS
INR
COLS
COLR
ZZSC
ZZRC
7
7
7
7
ns
____
____
____
____
____
____
t
Interrupt Flag Reset Time
Collision Flag Set Time
Collision Flag Reset Time
Sleep Mode Set Cycles
Sleep Mode Recovery Cycles
ns
t
3.6
4.2
ns
t
3.6
4.2
ns
____
____
t
2
3
2
3
cycles
cycles
____
____
t
Port-to-Port Delay
Clock-to-Clock Offset
Clock-to-Clock Offset for Collision Detection
____
____
t
CO
5
6
ns
tOFS
Please refer to Collision Detection Timing Table on Page 19
5678 tbl 11
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1)
apply when FT/PIPE = Vss (0V) for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE and OPT. FT/PIPE and OPT should be
treated as DC signals, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port.
4. Guaranteed by design (not production tested).
6.42
10
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(1,2)
tCYC2
tCH2
tCL2
CLK
CE
0
t
SC
tHC
t
SC
SB
t
HC
HB
(3)
CE
1
n
t
SB
tHB
t
t
(5)
BE
R/W
t
HW
HA
t
SW
SA
t
t
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
Qn + 1
Qn + 2(5)
(1)
tCKLZ
t
OHZ
tOLZ
OE(1)
,
tOE
5678 drw 05
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(1,2,6)
t
CYC1
t
CH1
t
CL1
CLK
CE
0
t
SC
tHC
t
SC
SB
tHC
(3)
CE
1
t
tHB
tHB
BEn
tSB
R/W
t
SW
SA
t
HW
t
t
HA
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
An + 3
tDC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2(5)
t
CKLZ
tDC
tOHZ
t
OLZ
OE(1)
,
tOE
5678 drw 06
NOTES:
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
6.42
11
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Multi-Device Pipelined Read(1,2)
tCYC2
t
CH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A6
A5
A4
A
3
A
2
A
0
A1
tSC tHC
t
SC
tHC
tCD2
tCD2
tCKHZ
tCD2
Q
0
Q
3
Q1
DATAOUT(B1)
ADDRESS(B2)
tDC
tCKLZ
tDC
tCKHZ
tSA
tHA
A6
A5
A4
A
3
A2
A
0
A1
tSC
tHC
CE0(B2)
tSC
tHC
tCD2
tCKHZ
tCD2
,
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
5678 drw 07
Timing Waveform of a Multi-Device Flow-Through Read(1,2)
t
CYC1
tCH1
tCL1
CLK
tSA
tH
A
A6
A5
A4
A3
A2
A0
A1
ADDRESS(B1)
t
SC
t
HC
CE0(B1)
tSC
tHC
(1)
tCD1
tCD1
tCKHZ
tCD1
tCD1
D
0
D
3
D5
D
1
DATAOUT(B1)
ADDRESS(B2)
(1)
(1)
(1)
tDC
tCKLZ
tCKLZ
t
DC
tCKHZ
tSA
tHA
A6
A
5
A4
A3
A2
A
0
A1
tSC
tHC
CE0(B2)
t
SC
t
HC
(1)
(1)
tCD1
tCKHZ
tCD1
tCKHZ
D4
DATAOUT(B2)
D2
(1)
(1)
,
tCKLZ
tCKLZ
5678 drw 08
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70T3539M for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. BEn, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.
6.42
12
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4)
CLK"A"
tSW
tHW
R/W"A
"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
ADDRESS"A"
DATAIN"A"
t
t
(3)
CO
t
CLK"B"
t
CD2
R/W"B"
tSW
tHW
tSA
t
HA
NO
ADDRESS"B"
DATAOUT"B"
MATCH
MATCH
VALID
,
t
DC
5678 drw 09
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)
CLK "A"
t
SW
tHW
R/W "A"
ADDRESS "A"
DATAIN "A"
CLK "B"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(3)
tCO
t
CD1
R/W "B"
tHW
tSW
t
HA
t
SA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
tCD1
VALID
VALID
,
tDC
t
DC
5678 drw 10
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be tCO + tCD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42
13
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(2)
t
CYC2
tCH2
tCL2
CLK
CE
CE
BE
0
1
n
t
SC
tHC
t
SB
tHB
tSW tHW
R/W
tSW tHW
(3)
An + 3
An + 4
An
An +1
An + 2
An + 2
ADDRESS
tSA
tHA
tSD
tHD
DATAIN
Dn + 2
tCD2
t
CD2
(1)
t
CKHZ
(4)
tCKLZ
Qn + 3
Qn
DATAOUT
READ
NOP
WRITE
READ
,
5678 drw 11
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(2)
t
CYC2
tCH2
tCL2
CLK
CE
0
tSC
tHC
CE1
tSB
tHB
BE
n
tSW tHW
R/W
t
SW tHW
(3)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
t
CD2
tCD2
t
CKLZ
(1)
Qn
Qn + 4
DATAOUT
(4)
tOHZ
OE
READ
WRITE
READ
,
NOTES:
5678 drw 12
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
14
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2)
t
CYC1
t
CH1
tCL1
CLK
CE
0
1
t
SC
tHC
CE
t
SB
tHB
BEn
t
SW tHW
R/
W
t
SW tHW
(3)
An + 4
An
An + 3
An +1
An + 2
An + 2
ADDRESS
t
SA
tHA
t
SD tHD
DATAIN
Dn + 2
t
CD1
t
CD1
tCD1
tCD1
(1)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
t
DC
t
DC
tCKLZ
t
CKHZ
NOP(5)
,
READ
WRITE
5678 drw 13
TimingWaveformof Flow-ThroughRead-to-Write-to-Read(OE Controlled)(2)
t
CYC1
t
CH1
tCL1
CLK
CE
0
1
t
SC
tHC
CE
t
SB
tHB
BEn
t
SW tHW
t
SW tHW
R/
W
(3)
An + 5
An
An + 4
An +1
An + 2
An + 3
Dn + 3
ADDRESS
DATAIN
t
SA
tHA
t
SD tHD
Dn + 2
t
OE
t
DC
t
CD1
t
CD1
t
CD1
(1)
Qn + 4
Qn
DATAOUT
t
CKLZ
t
DC
t
OHZ
OE
,
READ
WRITE
READ
5678 drw 14
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
15
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
t
SA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
CNTEN
t
SCN tHCN
tCD2
,
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 3
Qn + 1
Qn
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
5678 drw 15
TimingWaveformof Flow-ThroughReadwithAddressCounterAdvance(1)
t
CYC1
t
CH1
tCL1
CLK
t
SA
tHA
An
ADDRESS
t
SAD tHAD
t
SAD
t
HAD
ADS
t
SCN
t
HCN
CNTEN
t
CD1
,
Qn + 3(2)
Qx(2)
Qn + 4
Qn + 1
Qn + 2
Qn
DATAOUT
t
DC
READ
WITH
COUNTER
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
5678 drw 16
NOTES:
1. CE0, OE, BEn = VIL; CE1, R/W, and REPEAT = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.42
16
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)(1)
t
CYC2
tCH2
tCL2
CLK
t
SA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 1
An + 3
An + 4
An + 2
t
SAD tHAD
ADS
t
SCN
t
HC
N
CNTEN
t
SD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
,
5678 drw 17
Timing Waveform of Counter Repeat(2,6)
t
CYC2
CLK
t
SA tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An+2
An+1
An+2
An+2
An
An
An+1
An+2
t
SAD tHAD
ADS
tSW tHW
R/
W
t
SCN tHCN
CNTEN
(4)
REPEAT
SRPT tHRPT
t
,
t
SD
t
HD
D3
D2
D
0
D1
DATAIN
tCD1
An
An+1
An+2
An+2
HOLD
DATAOUT
,
ADVANCE
COUNTER
WRITE TO
An+2
ADVANCE
COUNTER
WRITE TO
An+1
HOLD
REPEAT
READ LAST
ADS
ADDRESS
An
ADVANCE
COUNTER
READ
WRITE TO
ADS
ADDRESS
An
ADVANCE
COUNTER
READ
COUNTER
WRITE TO
An+2
COUNTER
READ
An+1
An+2
An+2
5678 drw 18
NOTES:
1. CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.
CE0, BEn = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.
5. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
6.42
17
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(2)
CLK
L
tSW
tHW
R/W
L
t
SA
7FFFF
SC
t
HA
ADDRESSL(3)
CEL(1)
t
t
HC
t
INS
INT
R
t
INR
CLKR
t
SC
tHC
CER(1)
R/WR
t
SW
SA
7FFFF
t
HW
t
HA
t
ADDRESSR(3)
5678 drw 19
NOTES:
1. CE0 = VIL and CE1 = VIH
2. All timing is the same for Left and Right ports.
3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Truth Table III — Interrupt Flag(1)
Left Port
Right Port
(2)
(2)
(2)
(2)
CLK
L
R/W
L
CE
L
A
18L-A0L
CLK
R
R/W
R
CE
R
A
18R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
INT
X
L
INTR
↑
↑
↑
↑
↑
↑
↑
↑
L
X
X
H
L
7FFFF
X
X
H
L
X
L
L
X
X
L
R
X
X
L
X
7FFFF
7FFFE
X
H
X
X
R
X
L
L
7FFFE
H
X
L
5678 tbl 12
NOTES:
1. INTL and INTR must be initialized at power-up by Resetting the flags.
2. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
18
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Collision Timing(1,2)
CLK
L
tOFS
tSA tHA
ADDRESS(4)
L
A
3
A
2
A1
A0
tCOLR
tCOLS
COL
L
(3)
tOFS
CLK
R
tSA
tHA
(4)
ADDRESS
R
A3
A
2
A0
A1
tCOLR
tCOLS
COL
R
5678 drw 20
NOTES:
1. CE0 = VIL, CE1 = VIH.
2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3. Leading Port Output flag might output 3tCYC2 + tCOLS after Address match.
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Collision Detection Timing(3,4)
tOFS (ns)
Cycle Time
NOTES:
1. Region 1
Region 1 (ns) (1)
Region 2 (ns) (2)
Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.
2. Region 2
Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.
while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.
3. All the production units are tested to midpoint of each region.
5ns
6ns
0 - 2.8
2.81 - 4.6
0 - 3.8
0 - 5.3
3.81 - 5.6
5.31 - 7.1
4. These ranges are based on characterization of a typical device.
7.5ns
5678 tbl 13
Truth Table IV — Collision Detection Flag
Left Port
Right Port
(1)
(1)
(2)
(1)
(1)
(2)
CLK
L
R/W
L
CE
L
A
18L-A0L
CLK
R
R/W
R
CE
R
A
18R-A0R
Function
COL
L
COL
H
R
Both ports reading. Not a valid collision.
No flag output on either port.
↑
↑
↑
↑
↑
↑
↑
H
L
L
L
L
MATCH
MATCH
MATCH
MATCH
H
H
L
MATCH
MATCH
MATCH
MATCH
Left port reading, Right port writing.
Valid collision, flag output on Left port.
H
L
L
L
L
H
L
L
L
L
H
Right port reading, Left port writing.
Valid collision, flag output on Right port.
H
L
Both ports writing. Valid collision. Flag
output on both ports.
↑
L
L
5678 tbl 14
NOTES:
1. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
19
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform - Entering Sleep Mode (1,2)
R/W
(3)
Timing Waveform - Exiting Sleep Mode (1,2)
An
An+1
(5)
R/W
OE
(5)
Dn
Dn+1
DATAOUT
(4)
NOTES:
1. CE1 = VIH.
2. All timing is same for Left and Right ports.
3. CE0 has to be deactivated (CE0 = VIH) three cycles prior to asserting ZZ (ZZx = VIH) and held for two cycles after asserting ZZ (ZZx = VIH).
4. CE0 has to be deactivated (CE0 = VIH) one cycle prior to de-asserting ZZ (ZZx = VIL) and held for three cycles after de-asserting ZZ (ZZx = VIL).
5. The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.
6.42
20
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
same startingaddress onbothports andone orbothports writing
duringeachaccess(i.e.,imposesalongstringofcollisionson
contiguousclockcycles),thealertflagwillbeassertedandcleared
everyothercycle.PleaserefertotheCollisionDetectiontiming
waveform on Page 19.
FunctionalDescription
The IDT70T3539M provides a true synchronous Dual-Port Static
RAM interface.Registeredinputsprovideminimalset-upandholdtimes
onaddress,data,andallcriticalcontrolinputs.Allinternalregistersare
clocked on the rising edge of the clock signal, however, the self-timed
internalwritepulsewidthisindependentofthecycletime.
Collisiondetectiononthe IDT70T3539Mrepresents a significant
advanceinfunctionalityovercurrentsyncmulti-ports,whichhaveno
suchcapability. InadditiontothisfunctionalitytheIDT70T3539M
sustainsthekeyfeaturesofbandwidthandflexibility. Thecollision
detectionfunctionisveryusefulinthecaseofburstingdata,orastring
ofaccessesmadetosequentialaddresses,inthatitindicatesa
problemwithintheburst,givingtheusertheoptionofeitherrepeating
theburstorcontinuingtowatchthealertflagtoseewhetherthe
numberofcollisionsincreasesaboveanacceptablethresholdvalue.
Offeringthisfunctiononchipalsoallowsuserstoreducetheirneedfor
arbitrationcircuits,typicallydoneinCPLD’sorFPGA’s.Thisreduces
boardspaceanddesigncomplexity, andgives theusermoreflexibility
indevelopingasolution.
An asynchronous output enable is provided to ease asyn-
chronousbusinterfacing.Counterenableinputsarealsoprovidedtostall
the operation of the address counters for fast interleaved
memoryapplications.
AHIGHonCE0oraLOWonCE1foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70T3539Ms for depth
expansionconfigurations. Twocycles arerequiredwith CE0 LOWand
CE1HIGHtore-activatetheoutputs.
Interrupts
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)isassignedtoeachport. Theleftportinterrupt
flag (INTL) is asserted when the right port writes to memory location
7FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
addresslocation7FFFEwhenCEL= VIL andR/WL=VIH.Likewise,the
right port interrupt flag (INTR) is asserted when the left
port writes to memory location 7FFFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 7FFFF. The
message (36 bits) at 7FFFE or 7FFFF is user-defined since it is an
addressableSRAMlocation.Iftheinterruptfunctionisnotused,address
locations 7FFFE and 7FFFF are not used as mail boxes, but as part of
the random access memory. Refer to Truth Table III for the interrupt
operation.
SleepMode
TTheIDT70T3539Misequippedwithanoptionalsleeporlowpower
modeonbothports.Thesleepmodepinonbothportsisasynchronous
andactivehigh.Duringnormaloperation,theZZpinispulledlow.When
ZZispulledhigh,theportwillentersleepmodewhereitwillmeetlowest
possible power conditions. The sleep mode timing diagram shows the
modes ofoperation:NormalOperation,NoRead/WriteAllowedandSleep
Mode.
Fornormaloperationallinputsmustmeetsetupandholdtimesprior
tosleepand afterrecoveringfromsleep.Clocksmustalsomeetcyclehigh
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx=VIH)andthreecyclesafterde-assertingZZ(ZZx=VIL),thedevice
mustbedisabledviathechipenablepins.Ifawriteorreadoperationoccurs
duringtheseperiods,thememoryarraymaybecorrupted.Validityofdata
outfromtheRAMcannotbeguaranteedimmediatelyafterZZisasserted
(priortobeinginsleep).Whenexitingsleepmode,thedevicemustbein
Read mode (R/Wx = VIH)when chip enable is asserted, and the chip
enablemustbevalidforonefullcyclebeforeareadwillresultintheoutput
ofvaliddata.
DuringsleepmodetheRAMautomaticallydeselectsitself.TheRAM
disconnectsitsinternalclockbuffer.Theexternalclockmaycontinuetorun
withoutimpactingtheRAMssleepcurrent(IZZ).Alloutputswillremainin
high-Zstatewhileinsleepmode.Allinputsareallowedtotoggle.TheRAM
will not be selected and will not perform any reads or writes.
CollisionDetection
Collision is defined as an overlap in access between the two ports
resultinginthepotentialforeitherreadingorwritingincorrectdatatoa
specificaddress. Forthe specificcases:(a)Bothports reading-no
dataiscorrupted,lost,orincorrectlyoutput,sonocollisionflagisoutput
on either port. (b) One port writing, the other port reading - the end
resultofthe write willstillbe valid. However, the readingportmight
capturedatathatisinastateoftransitionandhencethereadingport’s
collisionflagis output.(c)Bothports writing-thereis ariskthatthetwo
ports willinterferewitheachother,andthedatastoredinmemorywill
notbe a validwrite fromeitherport(itmayessentiallybe a random
combinationofthetwo). Therefore,thecollisionflagisoutputonboth
ports. Please refer to Truth Table IV for all of the above cases.
The alert flag (COLX) is asserted on the 2nd or 3rd rising clock
edgeoftheaffectedportfollowingthecollision,andremainslowfor
onecycle.PleaserefertoCollisionDetectionTimingTableonPage
19.Duringthatnextcycle,theinternalarbitrationis engagedin
resettingthealertflag(thisavoidsaspecificrequirementonthepartof
theusertoresetthealertflag). Iftwocollisionsoccuronsubsequent
clockcycles,thesecondcollisionmaynotgeneratetheappropriate
alertflag.Athirdcollisionwillgeneratethealertflagasappropriate.In
theeventthatauserinitiatesaburstaccessonbothportswiththe
6.42
21
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Depth andWidth Expansion
The IDT70T3539M can also be used in applications requiring
expandedwidth,asindicatedinFigure4.Throughcombiningthecontrol
signals, the devices can be grouped as necessary to accommodate
applicationsneeding72-bitsorwider.
The IDT70T3539M features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
A
19
IDT70T3539M
Control Inputs
IDT70T3539M
Control Inputs
CE
0
1
CE
0
1
CE
CE
V
DD
V
DD
CE
1
0
IDT70T3539M CE
CE
1
0
IDT70T3539M
Control Inputs
CE
BE,
R/W,
OE,
CLK,
Control Inputs
ADS,
REPEAT,
CNTEN
5678 drw 22
Figure 4. Depth and Width Expansion with IDT70T3539M
JTAG Functionality and Configuration
TheIDT70T3539Miscomposedoftwoindependentmemoryarrays,
andthus cannotbe treatedas a single JTAGdevice inthe scanchain.
The two arrays (A and B) each have identical characteristics and
commandsbutmustbetreatedasseparateentitiesinJTAGoperations.
Please refer to Figure 5.
RegisterSizes, andSystemInterface Parametertables. Specifically,
commands for Array B must precede those for Array A in any JTAG
operationssenttotheIDT70T3539M. PleasereferenceApplicationNote
AN-411,"JTAGTestingofMultichipModules"forspecificinstructionson
performingJTAGtestingontheIDT70T3539M. AN-411isavailableat
www.idt.com.
.
JTAGsignalingmustbeprovidedseriallytoeacharrayandutilizethe
informationprovidedintheIdentificationRegisterDefinitions,Scan
IDT70T3539M
TDO
TDI
TDOA
TDIB
Array A
Array B
TCK
TMS
TRST
5678drw 23
Figure 5. JTAG Configuration for IDT70T3539M
6.42
22
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
JTAGTimingSpecifications
t
JCYC
t
JR
t
JF
t
JCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
t
JDC
tJS
tJH
Device Outputs(2)/
TDO
t
JRSR
t
JCD
TRST
,
5678 drw 24
t
JRST
Figure 6. Standard JTAG Timing
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4)
70T3539M
Max.
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Units
ns
____
____
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
t
ns
t
40
ns
(1)
____
t
3
ns
(1)
____
t
3
ns
____
____
t
50
ns
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
____
t
25
ns
____
t
0
ns
____
____
t
15
15
ns
t
JTAG Hold
ns
5678 tbl 15
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
6.42
23
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Value
Value
Array A
Instruction Field Array B
Instruction Field Array A
Description
Reserved for Version number
Array B
Revision Number (31:28)
0x0
Revision Number (63:60)
IDT Device ID (59:44)
0x0
IDT Device ID (27:12)
0x333
0x33
1
0x333
0x33
1
Defines IDT Part number
IDT JEDEC ID (11:1)
IDT JEDEC ID (43:33)
Allows unique identification of device vendor as IDT
Indicates the presence of an ID Register
ID Register Indicator Bit (Bit 0)
ID Register Indicator Bit (Bit 32)
5678 tbl 16
ScanRegisterSizes
Bit Size
Array A
Bit Size
Array B
Bit Size
70T3539M
Register Name
Instruction (IR)
4
1
4
1
8
2
Bypass (BYR)
Identification (IDR)
Boundary Scan (BSR)
32
32
64
Note (3)
Note (3)
Note (3)
5678 tbl 17
SystemInterfaceParameters
Instruction
Code
Description
EXTEST
00000000
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
IDCODE
11111111
Places the bypass register (BYR) between TDI and TDO.
00100010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
01000100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers except INTx and COLx to a High-Z state.
HIGHZ
CLAMP
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
00110011
00010001
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.
RESERVED
01010101, 01110111,
10001000, 10011001,
10101010, 10111011,
11001100
Several combinations are reserved. Do not use codes other than those
identified above.
PRIVATE
01100110,11101110,
11011101
For internal use only.
5678 tbl 18
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
6.42
24
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
XXXXX
A
999
A
A
IDT
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BC
256-pin BGA (BC-256)
Commercial Only
Commercial & Industrial
166
133
Speed in Megahertz
Standard Power
S
18Mbit (512K x 36) 2.5V Synchronous Dual-Port RAM
70T3539M
5678 drw 25
IDT Clock Solution for IDT70T3539M Dual-Port
Dual-Port I/O Specitications
Clock Specifications
Input Duty
IDT
PLL
Clock Device
IDT
Non-PLL
Clock Device
IDT Dual-Port
Part Number
Input
Capacitance
Maximum
Frequency Tolerance
Jitter
Voltage
3.3/2.5
I/O
Cycle
Requirement
5T9010
5T905, 5T9050
5T907, 5T9070
70T3539M
LVTTL
15pF
40%
166
75ps
5T2010
5678 tbl 19
6.42
25
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory:
10/08/03:
10/20/03:
InitialDatasheet
Page1 Added"IncludesJTAGfunctionality"tofeatures
Page 25 Added IDT Clock Solution Table
12/04/03:
Page10 AddedtOFS symbolandparametertoACElectricalCharacteristicstable
Page19 UpdatedCollisionTimingwaveform
Page19 AddedCollisionDetectionTimingtableandfootnotes
Page22 AddedJTAGConfigurationandJTAGFunctionalitydescriptions
Page 8 Changed ISB3 and IZZ in the DC Electrical Characteristics table
Page 20 & 21 Clarified Sleep Mode Text and Waveform
02/02/04:
04/08/04:
Page22 AddedanApplicationNote,AN-411, referencetotheJTAGFunctionalityandConfigurationtext
Page 4 Addedanothersentence tofootnote 4torecommendthatboundaryscannotbe operatedduringsleepmode
Removed"Preliminary"status
05/28/04:
07/25/08:
Page 8 Correctedatypointhe footnotes ofthe DCChars table
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
26
相关型号：
IDT70T3539MS166BC
HIGH-SPEED 2.5V 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
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IDT70T3539MS166BCI
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IDT70T3539MS999BC
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IDT70T3539MS999BCI
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IDT70T3589S-133BC
HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
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IDT70T3589S-133BCI
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IDT70T3589S-133BF
HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
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HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
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IDT70T3589S-133DR
HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
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