IDT70T3719_18_技术文档

HIGH-SPEED 2.5V

256/128K x 72

SYNCHRONOUS

IDT70T3719/99M

DUAL-PORTSTATICRAM

WITH 3.3V OR 2.5V INTERFACE

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features:

True Dual-Port memory cells which allow simultaneous

◆

– 1.7ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 166MHz

– Data input, address, byte enable and control registers

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V ( 100mV) power supply for core

LVTTL compatible, selectable 3.3V ( 150mV) or 2.5V

( 100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 133MHz

Available in a 324-pin Green Ball Grid Array (BGA)

Includes JTAG Functionality

Green parts available, see ordering information

access of the same memory location

High-speed data access

◆

– Commercial: 3.6ns (166MHz)/

4.2ns (133MHz)(max.)

◆

– Industrial: 4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

◆

additional logic

Interrupt and Collision Detection Flags

Full synchronous operation on both ports

– 6ns cycle time, 166MHz operation (23.9Gbps bandwidth)

– Fast 3.6ns clock to data out

◆

– Self-timedwriteallowsfastcycletime

Functional Block Diagram

BE7L

BE7R

BE0L

BE0R

FT/PIPE

L

0a 1a

a

0h 1h

h

1h 0h

h

1a 0a

a

FT/PIPER

1/0

R/WL

R/WR

CE0L

CE0R

1

CE1R

CE1L

0

B

W

0

B

W

7

B

W

7

B

W

0

1/0

L

R

OE

R

OE

L

D

OUT0-8_L

OUT9-17_L

D

OUT0-8_R

OUT9-17_R

OUT18-26_L

OUT27-35_L

OUT36-44_L

OUT45-53_L

OUT54-62_L

OUT63-72_L

OUT18-26_R

OUT27-35_R

OUT36-44_R

OUT45-53_R

OUT54-62_R

OUT63-72_R

,

1h 0h

1a 0a

0a 1a

0h 1h

0/1

FT/PIPER

FT/PIPE

L

a

h

a

256/128K x 72

MEMORY

ARRAY

Byte 0

I/O0L - I/O71L

Byte 7

Byte 0

I/O0R - I/O71R

D

IN_L

D

IN_R

,

CLK

L

CLKR

(1)

17L

(1)

17R

A

0L

REPEAT

ADS

Counter/

Address

Reg.

Counter/

Address

Reg.

R

0

ADDR_R

ADDR_L

L

REPEAT

ADS

CNTEN

R

L

R

CNTEN

L

INTERRUPT

CE

0

L

CE0R

TDI

TDO

TCK

TMS

T RST

COLLISION

DETECTION

LOGIC

CE

1

L

CE1R

JTAG

R/W

L

R/W

R

L

COL

INT

R

COL

INT

L

R

ZZ

CONTROL

LOGIC

(2)

ZZR

ZZ

L

5687 drw 01

NOTES:

1. Address A17 is a NC for the IDT70T3799.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx

FEBRUARY 2018

and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

1

DSC 5687/4

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Description:

TheIDT70T3719/99Misahigh-speed256K/128Kx72bitsynchro- tionalorbidirectionaldataflowinbursts.Anautomaticpowerdownfeature,

nousDual-PortRAM.ThememoryarrayutilizesDual-Portmemorycells controlled by CE0 and CE1, permits the on-chip circuitry of each port to

toallowsimultaneousaccessofanyaddressfrombothports.Registerson enter a very low standby power mode.

control,data,andaddressinputsprovideminimalsetupandholdtimes.

The 70T3719/99M can support an operating voltage of either 3.3V

The timing latitude provided by this approach allows systems to be or 2.5V on one or both ports, controllable by the OPT pins. The power

designed with very short cycle times. With an input data register, the supply for the core of the device (VDD) is at 2.5V.

IDT70T3719/99Mhasbeenoptimizedforapplicationshavingunidirec-

6.42

2

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Pin Configuration ^(2,3,4,5)

70T3719/99M

BBG-324⁽⁶⁾

324-Pin BGA

Top View⁽⁷⁾

06/27/05

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

B

I/O^39R

I/O38R

I/O37R

I/O36R

A

15L

A

12L

A

8L

CE1L

A

6L

A

1L

0L

3L

I/O32R

I/O33R

I/O34R

I/O35R

A

B

COL

L

BE7L

BE6L

BE0L

BE4L

BE2L

BE5L

CE0L

BE3L

ADSL

I/O^39L

I/O38L

I/O41R

I/O37L

I/O42R

I/O36L

I/O43R

TDO

A

17L⁽¹⁾

13L

A

10L

REPEAT

L

A

I/O32L

I/O31R

I/O33L

I/O30R

I/O34L

I/O29R

I/O35L

I/O28R

BE1L

OEL

C

D

E

F

I/O^40R

I/O^40L

I/O^47R

I/O^47L

I/O48R

I/O^48L

I/O^55R

I/O^55L

I/O^56R

I/O56L

I/O^63R

I/O^63L

I/O^64R

I/O^64L

I/O^71R

A

16L

A

11L

14L

A

7L

9L

R/W

L

CNTEN

L

A

4L

2L

C

D

E

F

INTL

I/O41L

I/O46R

I/O46L

I/O49R

I/O49L

I/O54R

I/O54L

I/O57R

I/O57L

I/O62R

I/O62L

I/O65R

I/O65L

I/O42L

I/O45R

I/O45L

I/O50R

I/O50L

I/O53R

I/O53L

I/O58R

I/O58L

I/O61R

I/O61L

I/O66R

I/O66L

I/O43L

I/O44R

I/O44L

I/O51R

I/O51L

I/O52R

I/O52L

I/O59R

I/O59L

I/O60R

I/O60L

I/O67R

I/O67L

TDI

NC

A

CLK

L

A

5L

ZZ

L

I/O31L

I/O24R

I/O24L

I/O23R

I/O23L

I/O16R

I/O16L

I/O15R

I/O15L

I/O8R

I/O8L

I/O30L

I/O25R

I/O25L

I/O22R

I/O22L

I/O17R

I/O17L

I/O14R

I/O14L

I/O9R

I/O9L

I/O29L

I/O26R

I/O26L

I/O21R

I/O21L

I/O18R

I/O18L

I/O13R

I/O13L

I/O10R

I/O10L

I/O5R

I/O28L

I/O27R

I/O27L

I/O20R

I/O20L

I/O19R

I/O19L

I/O12R

I/O12L

I/O11R

I/O11L

I/O4R

PL/FT

L

V

DD

V

DDQL

V

DDQR

V

DDQR

V

DDQL

V

DDQL

V

DDQR

V

DDQR

OPT

L

V

DD

V

ss

V

ss

DD

V

ss

V

DD

ss

DD

V

DD

ss

V

DD

V

DD

G

H

J

VDDQR

VDDQL

VDDQR

VDDQL

VDDQR

V

DDQR

DDQL

V

ss

V

DDQR

DDQL

VDDQR

VDDQL

VDDQR

VDDQL

VDDQR

G

H

J

V

ss

DD

V

ss

K

L

V

K

L

M

N

P

R

T

V

DDQL

DDQR

M

N

P

R

T

V

DDQR

V

DDQL

V

DDQL

V

DDQR

V

ZZR

TMS

V

DD

12R

13R

14R

V

DD

9R

7R

V

DDQL

V

DDQL

V

DD

6R

V

DD

2R

4R

OPT

R

A

17R⁽¹⁾

A

1R

0R

3R

5R

I/O7R

I/O7L

I/O6R

I/O6L

COL

R

BE4R

BE7R

BE2R

CE0R

BE3R

BE6R

OER

PL/FT

R

A

16R

A

CE1R

A

I/O5L

I/O4L

ADS

R

U

V

I/O70R

I/O69R

I/O68R

TCK

A

10R

R/W

R

REPEAT

R

I/O0R

I/O1R

I/O2R

I/O3R

I/O3L

U

V

INT

R

BE1R

I/O^71L

1

I/O70L

2

I/O69L

3

I/O68L

4

NC

15R

A

11R

A

8R

CLK

12

R

CNTEN

R

I/O0L

15

I/O1L

16

I/O2L

17

TRST

BE5R

BE0R

5

6

7

8

9

10

11

13

14

18

5687 tbl 01

NOTES:

1. Pin is a NC for IDT70T3799.

2. All VDD pins must be connected to 2.5V power supply.

3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is

set to VSS (0V).

4. All VSS pins must be connected to ground supply.

5. Package body is approximately 19mm x 19mm x 1.76mm, with 1.0mm ball-pitch.

6. This package code is used to reference the package diagram.

7. This text does not indicate orientation of the actual part-marking.

6.42

3

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Pin Names

Left Port

Right Port

CE0R CE1R

R/W

OE

Names

Chip Enables (Input)⁽⁶⁾

CE0L

R/W

OE

,

CE1L

,

L

R

Read/Write Enable (Input)

Output Enable (Input)

L

R

(5)

A

0L - A17L

A

0R - A17R

I/O0R - I/O71R

CLK

PL/FT

ADS

CNTEN

REPEAT

BE0R - BE7R

Address (Input)

I/O^0L- I/O71L

CLK

PL/FT

ADS

CNTEN

REPEAT

BE0L - BE7L

Data Input/Output

L

R

Clock (Input)

L

R

Pipeline/Flow-Through (Input)

Address Strobe Enable (Input)

Counter Enable (Input)

Counter Repeat⁽³⁾

L

R

L

R

L

R

Byte Enables (9-bit bytes) (Input)⁽⁶⁾

Power (I/O Bus) (3.3V or 2.5V)⁽¹⁾(Input)

Option for selecting VDDQX^(1,2)(Input)

Sleep Mode pin⁽⁴⁾(Input)

Power (2.5V)⁽¹⁾(Input)

V

DDQL

L

V

DDQR

R

OPT

ZZ

OPT

ZZ

L

R

V

DD

SS

NOTES:

1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2. OPTX selects the operating voltage levels for the I/Os and controls on that port.

If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V

levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that

port's I/Os and address controls will operate at 2.5V levels and VDDQX must be

supplied at 2.5V. The OPT pins are independent of one another—both ports can

operate at 3.3V levels, both can operate at 2.5V levels, or either can operate

at 3.3V with the other at 2.5V.

Ground (0V) (Input)

TDI

TDO

TCK

Test Data Input

Test Data Output

Test Logic Clock (10MHz) (Input)

Test Mode Select (Input)

Reset (Initialize TAP Controller) (Input)

Interrupt Flag (Output)

TMS

TRST

3. When REPEATX is asserted, the counter will reset to the last valid address loaded

via ADSX.

INT

R

INT

L

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when

asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins

themselves (ZZx) are not affected during sleep mode. It is recommended that

boundry scan not be operated during sleep mode.

COL

R

Collision Alert (Output)

COL

L

5687 tbl 02

5. Address A^17xis a NC for the IDT70T3799M.

6. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the

signals take two cycles to deselect.

6.42

4

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

(1,2,3,4,5)

Truth Table I—Read/Write and Enable Control

CLK

!

X

CE

1

Byte Enables

All BE = X

All BE = H

R/W

ZZ

L

I/O Operation⁽⁶⁾

MODE

OE

X

L

CE

H

X

L

0

X

All Bytes= High-Z

All Bytes = High-Z

Deselected: Power Down

All Bytes Deselected

L

X

H

X

L

Byten = DIN, All other Bytes = High-Z Write to Byte X Only

BEn = L, All other BE = H

L

Byte^4-7= DIN, Byte0-3 = High-Z

Byte^4-7= High-Z, Byte0-3 = DIN

Byte^0-7= DIN

Write to Lower Bytes Only

Write to Upper Bytes Only

Write to All Bytes

BE^4-7= L, BE0-3 = H

BE^4-7= H, BE0-3 = L

BE^0-7= L

L

H

X

Byten = DOUT, All other Bytes = High-Z Read Byte X Only

BEn = L, All other BE = H

L

Byte^4-7= DOUT, Byte0-3 = High-Z

Byte^4-7= High-Z, Byte0-3 = DOUT

All Bytes = DOUT

Read Lower Bytes Only

Read Upper Bytes Only

Read All Bytes

BE^4-7= L, BE0-3 = H

BE^4-7= H, BE0-3 = L

All BE = L

L

H

X

All BE = X

L

All Bytes = High-Z

Outputs Disabled

Sleep Mode

X

All BE = X

X

H

All Bytes = High-Z

5687 tbl 03

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, REPEAT = X.

3. OE and ZZ are asynchronous input signals.

4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

5. For the examples shown here, BEn may correspond to any of the eight byte enable signals.

(1,2)

Truth Table II—Address Counter Control

Previous Internal

Internal Address

I/O⁽³⁾

I/O(n) External Address Used

I/O(n+1) Counter Enabled-Internal Address generation

I/O(n+1) Enabled Address Blocked-Counter disabled (An + 1 reused)

I/O(n) Counter Set to last valid ADS load

ADS⁽⁴⁾

CNTEN REPEAT^(4,6)

MODE

Address Address

Used

An

CLK

!

An

X

An

L

X

H

L

D

An + 1

An

H

X

L⁽⁵⁾

H

D

!

X

An + 1

X

!

X

D

!

5687 tbl 04

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.

3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.

4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn.

5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.

6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded

via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.

6.42

5

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage

Ambient

(1)

Grade

Commercial

Temperature

0^OC to +70^OC

-40^OC to +85^OC

GND

0V

V

+

DD

2.5V

100mV

Industrial

0V

5687 tbl 05

NOTES:

1. This is the parameter TA. This is the "instant on" case temperature.

Recommended DC Operating

Conditions with VDDQ at 2.5V

Symbol

Parameter

Core Supply Voltage

I/O Supply Voltage⁽³⁾

Ground

Min.

2.4

0

Typ.

2.5

0

Max.

Unit

V

DD

DDQ

SS

2.6

0

V

Input High Volltage

(Address, Control &

Data I/O Inputs)⁽³⁾

____

V

DDQ + 100mV⁽²⁾

1.7

V

IH

Input High Voltage ^_

JTAG

____

V

DD + 100mV⁽²⁾

Input High Voltage -

ZZ, OPT, PIPE/FT

____

VIH

VIL

V

DD - 0.2V

-0.3⁽¹⁾

V

DD + 100mV⁽²⁾

V

Input Low Voltage

0.7

0.2

Input Low Voltage -

ZZ, OPT, PIPE/FT

-0.3⁽¹⁾

V

5687 tbl 06a

NOTES:

1. VIL (min.) = -1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.

2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.

3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT

pinforthatportmustbesettoVss(0V), andVDDQX forthatportmustbesuppliedasindicated

above.

Recommended DC Operating

Conditions with VDDQ at 3.3V

Symbol

Parameter

Core Supply Voltage

I/O Supply Voltage⁽³⁾

Ground

Min.

2.4

3.15

0

Typ.

2.5

3.3

0

Max.

2.6

3.45

0

Unit

V

VDD

VDDQ

VSS

V

Input High Voltage

(Address, Control

&Data I/O Inputs)⁽³⁾

VDDQ + 150mV⁽²⁾

VDD + 100mV⁽²⁾

V

____

2.0

1.7

VIH

_

Input High Voltage

JTAG

____

Input High Voltage -

ZZ, OPT, PIPE/FT

____

VIH

VIL

VDD - 0.2V

-0.3⁽¹⁾

VDD + 100mV⁽²⁾

V

Input Low Voltage

0.8

0.2

Input Low Voltage -

ZZ, OPT, PIPE/FT

-0.3⁽¹⁾

5687 tbl 06b

NOTES:

1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less.

2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.

3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin

for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied as indicated

above.

6.42

6

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Absolute Maximum Ratings ⁽¹⁾

Symbol

Rating

Commercial

& Industrial

Unit

V

TERM

V

DD Terminal Voltage

with Respect to GND

-0.5 to 3.6

(VDD

)

(2)

V

(VDDQ

TERM

V

DDQ Terminal Voltage

with Respect to GND

-0.3 to VDDQ + 0.3

-0.3 to V^DDQ+ 0.3

V

)

(2)

VTERM

(INPUTS and I/O's)

Input and I/O Terminal

Voltage with Respect to GND

V

(3)

T

BIAS

STG

JN

Temperature Under Bias

Storage Temperature

Junction Temperature

-55 to +125

-65 to +150

+150

^oC

T

^oC

I

OUT(For VDDQ = 3.3V) DC Output Current

OUT(For VDDQ = 2.5V) DC Output Current

NOTES:

50

mA

I

40

mA

5687 tbl 07

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation of the

device at these or any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

2. This is a steady-state DC parameter that applies after the power supply has reached its

nominal operating value. Power sequencing is not necessary; however, the voltage on

any Input or I/O pin cannot exceed V^DDQduring power supply ramp up.

3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.

Capacitance ⁽¹⁾

(TA = +25°C, F = 1.0MHZ)

Symbol

Parameter

Input Capacitance

Output Capacitance

Conditions⁽²⁾

IN = 0V

OUT = 0V

Max. Unit

CIN

V

15

pF

(2)

OUT

C

V

10.5

pF

5687 tbl 08

NOTES:

1. These parameters are determined by device characterization, but are not

production tested.

2. C^OUTalso references CI/O.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)

70T3719/99M

Symbol

|I^LI

|I^LO

Parameter

Test Conditions

DDQ = Max., VIN = 0V to VDDQ

DD = Max. IN = 0V to VDD

Min.

Max.

10

Unit

µA

V

___

|

Input Leakage Current⁽¹⁾

V

|

JTAG & ZZ Input Leakage Current^(1,2)

Output Leakage Current^(1,3)

,

V

30

|

10

CE

OL = +4mA, VDDQ = Min.

OH = -4mA, VDDQ = Min.

OL = +2mA, VDDQ = Min.

OH = -2mA, VDDQ = Min.

0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ

V

OL (3.3V) Output Low Voltage⁽¹⁾

OH (3.3V) Output High Voltage⁽¹⁾

OL (2.5V) Output Low Voltage⁽¹⁾

OH (2.5V) Output High Voltage⁽¹⁾

I

0.4

___

I

2.4

V

___

I

0.4

V

___

I

2.0

V

5687 tbl 09

NOTES:

1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.

2. Applicable only for TMS, TDI and TRST inputs.

3. Outputs tested in tri-state mode.

6.42

7

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

(3)

Temperature and Supply Voltage Range

(VDD = 2.5V ± 100mV)

70T3719/99M

S166

Com'l

70T3719/99M

S133

Com'l

Only

& Ind

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽⁴⁾

Max.

Typ.⁽⁴⁾

520

280

400

12

Max. Unit

IDD

Dynamic Operating

Current (Both

Ports Active)

CEL and CER= VIL,

Outputs Disabled,

f = fMAX

S

640

900

740

900

380

470

500

620

20

mA

___

(1)

IND

I

SB1⁽⁶⁾

Standby Current

(Both Ports - TTL

Level Inputs)

CE

f = fMAX

L

= CE

(1)

R

= VIH

COM'L

IND

350

460

___

SB2⁽⁶⁾

Standby Current

(One Port - TTL

Level Inputs)

(5)

I

CE"A" = VIL and CE"B" = VIH

Active Port Outputs Disabled,

COM'L

IND

500

650

___

(1)

f=fMAX

ISB3

Full Standby Current

(Both Ports - CMOS

Level Inputs)

Both Ports CE

R

L and

> VDDQ - 0.2V, VIN > VDDQ - 0.2V

or VIN < 0.2V, f = 0⁽²⁾

COM'L

IND

12

20

CE

___

12

25

SB4⁽⁶⁾

Full Standby Current

(One Port - CMOS

Level Inputs)

CE"A" < 0.2V and CE"B" > VDDQ - 0.2V⁽⁵⁾

IN > VDDQ - 0.2V or VIN < 0.2V

Active Port, Outputs Disabled, f = fMAX

I

COM'L

IND

500

650

400

12

500

620

20

V

___

(1)

Izz

Sleep Mode Current

(Both Ports - TTL

Level Inputs)

ZZL = ZZR = VIH

COM'L

IND

12

20

(1)

f=fMAX

mA

___

12

25

5687 tbl 10

NOTES:

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS".

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. V^DD= 2.5V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 30mA (Typ).

5. CEX = VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CE^X< 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V

CE^X> VDD - 0.2V means CE0X > VDD - 0.2V or CE1X - 0.2V

"X" represents "L" for left port or "R" for right port.

6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH.

6.42

8

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

AC Test Conditions (VDDQ - 3.3V/2.5V)

Input Pulse Levels (Address & Controls)

Input Pulse Levels (I/Os)

Input Rise/Fall Times

GND to 3.0V/GND to 2.4V

2ns

Input Timing Reference Levels

Output Reference Levels

Output Load

1.5V/1.25V

Figure 1

5687 tbl 11

50Ω

,

DATAOUT

1.5V/1.25

10pF

(Tester)

5687 drw 03

Figure 1. AC Output Test load.

∆

tCD

(Typical, ns)

5687 drw 04

∆

Capacitance (pF) from AC Test Load

6.42

9

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating Temperature Range

(2,3)

(Read and Write Cycle Timing)

(VDD = 2.5V ± 100mV, TA = 0°C to +70°C)

70T3719/99M

S166

Com'l

70T3719/99M

S133

Com'l

Only

& Ind

Symbol

Parameter

Min.

20

Max.

Min.

25

Max.

Unit

ns

t

CYC1

CYC2

CH1

CL1

CH2

CL2

SA

HA

SC

HC

SB

HB

SW

HW

SD

HD

SAD

HAD

SCN

HCN

SRPT

HRPT

OE

Clock Cycle Time (Flow-Through)⁽¹⁾

Clock Cycle Time (Pipelined)⁽¹⁾

Clock High Time (Flow-Through)⁽¹⁾

Clock Low Time (Flow-Through)⁽¹⁾

Clock High Time (Pipelined)⁽²⁾

Clock Low Time (Pipelined)⁽¹⁾

Address Setup Time

____

t

6

7.5

10

ns

t

8

ns

t

8

10

ns

t

2.4

1.7

0.5

1.7

0.5

1.7

0.5

1.7

0.5

1.7

0.5

1.7

0.5

1.7

0.5

1.7

3

ns

t

3

ns

t

1.8

0.5

1.8

0.5

1.8

0.5

1.8

0.5

1.8

0.5

1.8

0.5

1.8

0.5

1.8

ns

t

Address Hold Time

ns

t

Chip Enable Setup Time

Chip Enable Hold Time

Byte Enable Setup Time

Byte Enable Hold Time

R/W Setup Time

ns

t

ns

t

ns

t

ns

t

ns

t

R/W Hold Time

ns

t

Input Data Setup Time

ns

t

Input Data Hold Time

ns

t

ns

ADS Setup Time

t

ns

ADS Hold Time

t

ns

CNTEN Setup Time

t

ns

CNTEN Hold Time

t

ns

REPEAT Setup Time

t

0.5

ns

REPEAT Hold Time

____

t

Output Enable to Data Valid

Output Enable to Output Low-Z

Output Enable to Output High-Z

Clock to Data Valid (Flow-Through)⁽¹⁾

Clock to Data Valid (Pipelined)⁽¹⁾

Data Output Hold After Clock High

Clock High to Output High-Z

Clock High to Output Low-Z

Interrupt Flag Set Time

4.4

4.6

ns

(4)

____

t

OLZ

1

ns

(4)

OHZ

t

1

3.6

12

1

4.2

15

ns

____

t

CD1

CD2

DC

CKHZ

ns

____

t

3.6

4.2

ns

____

t

1

ns

(4)

t

3.6

4.2

ns

(4)

CKLZ

____

t

1

ns

____

t

INS

INR

COLS

COLR

ZZSC

ZZRC

7

ns

____

t

Interrupt Flag Reset Time

Collision Flag Set Time

Collision Flag Reset Time

Sleep Mode Set Cycles

Sleep Mode Recovery Cycles

ns

t

3.6

4.2

ns

t

3.6

4.2

ns

____

t

2

3

2

3

cycles

____

t

Port-to-Port Delay

Clock-to-Clock Offset

____

tCO

5

6

ns

Please refer to collision Detection Timing Table

on Page 19.

tOFS

Clock-to-Clock Offset for Collision Detection

5687 tbl 12

NOTES:

1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1)

apply when FT/PIPE = Vss (0V) for that port.

2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE and OPT. FT/PIPE and OPT should be

treated as DC signals, i.e. steady state during operation.

3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port.

4. Guaranteed by design (not production tested).

6.42

10

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Read Cycle for Pipelined Operation

(FT/PIPE'X' = VIH)^(1,2)

tCYC2

tCH2

tCL2

CLK

CE

0

t

SC

(3)

tHC

tSC

tHC

CE1

t

SB

tHB

tSB

tHB

(5)

BE

n

R/

W

tHW

tSW

t

SA

tHA

ADDRESS⁽⁴⁾

DATAOUT

An

An + 1

An + 2

Qn

An + 3

(1 Latency)

t

DC

tCD2

Qn + 1

Qn + 2⁽⁵⁾

(1)

t

CKLZ

t

OHZ

tOLZ

(1)

OE

,

tOE

5687 drw 05

Timing Waveform of Read Cycle for Flow-through Output

(FT/PIPE"X" = VIL)^(1,2,6)

tCYC1

tCH1

tCL1

CLK

CE

0

t

SC

(3)

tHC

t

SC

SB

tHC

CE1

t

tHB

t

HB

BEn

tSB

R/W

t

SW

t

HW

HA

t

SA

t

ADDRESS⁽⁴⁾

DATAOUT

An

An + 1

An + 2

An + 3

tDC

tCD1

tCKHZ

Qn

Qn + 1

Qn + 2⁽⁵⁾

t

CKLZ

tDC

t

OHZ

t

OLZ

(1)

OE

,

t

OE

5687 drw 06

NOTES:

1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.

2. ADS = VIL, CNTEN and REPEAT = VIH.

3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to

Truth Table 1.

4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).

6. "x" denotes Left or Right port. The diagram is with respect to that port.

6.42

11

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

(1,2)

Timing Waveform of a Multi-Device Pipelined Read

t

CYC2

t

CH2

t

CL2

CLK

ADDRESS(B1)

CE0(B1)

t

SA

tHA

A

6

A

5

A

4

A

3

A

2

A

0

A

1

t

SC

t

HC

t

SC

tHC

t

CD2

t

CD2

t

CKHZ

t

CD2

Q

0

Q3

Q

1

DATAOUT(B1)

ADDRESS(B2)

t

DC

t

CKLZ

t

DC

tCKHZ

t

SA

t

HA

A

6

A

5

A

4

A3

A

2

A

0

A

1

t

SC

t

HC

CE0(B2)

t

SC

t

HC

t

CD2

t

CKHZ

t

CD2

,

DATAOUT(B2)

Q

4

Q

2

t

CKLZ

t

CKLZ

5687 drw 07

(1,2)

Timing Waveform of a Multi-Device Flow-Through Read

t

CYC1

tCH1

tCL1

CLK

t

SA

tH

A

A6

A5

A4

A3

A2

A0

A1

ADDRESS(B1)

t

SC

tHC

CE0(B1)

t

SC

tHC

(1)

tCD1

t

CKHZ

t

CD1

(1)

tCD1

D0

D3

D5

D1

DATAOUT(B1)

ADDRESS(B2)

(1)

tDC

t

CKLZ

tCKLZ

t

DC

t

CKHZ

t

SA

tHA

A6

A5

A4

A3

A2

A

0

A1

t

SC

tHC

CE0(B2)

t

SC

t

HC

(1)

t

CD1

t

CKHZ

t

CD1

(1)

t

CKHZ

D4

DATAOUT(B2)

D2

(1)

,

t

CKLZ

tCKLZ

5687 drw 08

NOTES:

1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70T3719/99M for this waveform,

and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.

2. BEn, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.

6.42

12

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

(1,2,4)

Timing Waveform of Left Port Write to Pipelined Right Port Read

CLK"A"

t

SW

tHW

R/W"A

"

t

SA

MATCH

SD HD

VALID

tHA

NO

MATCH

ADDRESS"A"

DATAIN"A"

t

(3)

CO

t

CLK"B"

tCD2

R/W"B"

tSW

tHW

tSA

tHA

NO

ADDRESS"B"

DATAOUT"B"

MATCH

VALID

,

t

DC

5687 drw 09

NOTES:

1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.

3. If t^CO< minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be

tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port

will be tCO + tCYC2 + tCD2).

4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"

(1,2,4)

Timing Waveform with Port-to-Port Flow-Through Read

CLK "A"

tSW tHW

R/W "A"

tSA tHA

NO

ADDRESS "A"

DATAIN "A"

CLK "B"

MATCH

tSD tHD

VALID

(3)

tCO

tCD1

R/W "B"

tHW

tHA

tSW

tSA

NO

MATCH

ADDRESS "B"

DATAOUT "B"

MATCH

tCD1

VALID

,

tDC

5687 drw 10

NOTES:

1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.

3. If t^CO< minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be

tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will

be tCO + tCD1).

4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".

6.42

13

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Pipelined Read-to-Write-to-Read

(OE = VIL)⁽²⁾

tCYC2

tCH2

tCL2

CLK

CE0

CE1

BEn

t

SC

tHC

tSB

tHB

tSW tHW

R/W

tSW tHW

(3)

An + 3

An + 4

An

An +1

An + 2

ADDRESS

t

SA

tHA

t

SD

tHD

DATAIN

Dn + 2

tCD2

t

CD2

(1)

t

CKHZ

(4)

tCKLZ

Qn + 3

Qn

DATAOUT

READ

NOP

WRITE

READ

,

5687 drw 11

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

(2)

Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)

tCYC2

tCH2

tCL2

CLK

CE

0

t

SC

tHC

CE1

tSB

tHB

BE

n

t

SW tHW

R/

W

t

SW tHW

(3)

An + 4

An

An +1

An + 2

An + 3

Dn + 3

An + 5

ADDRESS

t

SA

tHA

t

SD

tHD

DATAIN

Dn + 2

t

CD2

t

CD2

t

CKLZ

(1)

Qn

Qn + 4

DATAOUT

(4)

tOHZ

OE

READ

WRITE

READ

,

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

5687 drw 12

2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference

use only.

4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.

6.42

14

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)⁽²⁾

t

CYC1

tCH1

tCL1

CLK

CE

0

1

t

SC

tHC

CE

t

SB

tHB

BEn

t

SW tHW

R/W

tSW tHW

(3)

An + 4

An

An + 3

An +1

An + 2

ADDRESS

t

SA

tHA

t

SD

tHD

DATAIN

Dn + 2

t

CD1

tCD1

t

CD1

tCD1

(1)

Qn + 3

Qn

READ

Qn + 1

DATAOUT

tDC

t

CKLZ

t

DC

tCKHZ

NOP⁽⁵⁾

,

READ

WRITE

5687 drw 13

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)⁽²⁾

t

CYC1

t

CH1

tCL1

CLK

CE

0

1

t

SC

tHC

CE

t

SB

tHB

BEn

t

SW tHW

t

SW tHW

R/

W

(3)

An + 5

An

An + 4

An +1

An + 2

An + 3

Dn + 3

ADDRESS

t

SA

tHA

t

SD tHD

DATAIN

Dn + 2

tOE

t

DC

t

CD1

tCD1

t

CD1

(1)

Qn + 4

Qn

DATAOUT

tCKLZ

t

DC

t

OHZ

OE

,

READ

WRITE

READ

5687 drw 14

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

6.42

15

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

(1)

Timing Waveform of Pipelined Read with Address Counter Advance

t

CYC2

tCH2

tCL2

CLK

tSA

tHA

An

ADDRESS

t

SAD tHAD

ADS

tSAD tHAD

CNTEN

tSCN tHCN

tCD2

,

Qn + 2⁽²⁾

Qx - 1⁽²⁾

Qx

Qn + 3

Qn + 1

Qn

DATAOUT

tDC

READ

EXTERNAL

ADDRESS

READ

WITH

COUNTER

HOLD

READ WITH COUNTER

5687 drw 15

(1)

Timing Waveform of Flow-Through Read with Address Counter Advance

t

CYC1

tCH1

tCL1

CLK

tSA

tHA

An

ADDRESS

t

SAD tHAD

t

SAD

t

HAD

ADS

t

SCN

tHCN

CNTEN

t

CD1

,

Qn + 3⁽²⁾

Qx⁽²⁾

Qn + 4

Qn + 1

Qn + 2

Qn

DATAOUT

tDC

READ

WITH

COUNTER

READ

EXTERNAL

ADDRESS

READ WITH COUNTER

COUNTER

HOLD

5687 drw 16

NOTES:

1. CE0, OE, BEn = VIL; CE1, R/W, and REPEAT = VIH.

2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then

the data output remains constant for subsequent clocks.

6.42

16

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Address Counter Advance

(1)

(Flow-through or Pipelined Inputs)

t

CYC2

tCH2

tCL2

CLK

t

SA

tHA

An

ADDRESS

INTERNAL⁽³⁾

ADDRESS

An⁽⁷⁾

An + 4

An + 2

An + 1

An + 3

t

SAD tHAD

ADS

t

SCN

t

HC

N

CNTEN

t

SD tHD

Dn + 4

Dn + 1

Dn + 3

Dn

Dn + 1

Dn + 2

DATAIN

WRITE

EXTERNAL

ADDRESS

WRITE

WITH COUNTER

WRITE

COUNTER HOLD

WRITE WITH COUNTER

,

5687 drw 17

(2,6)

Timing Waveform of Counter Repeat

tCYC2

CLK

tSA tHA

An

ADDRESS

INTERNAL⁽³⁾

ADDRESS

An+2

An+1

An+2

An

An+1

An+2

tSAD tHAD

ADS

tSW tHW

R/

W

t

SCN tHCN

CNTEN

(4)

REPEAT

_SRPTtHRPT

t

,

t

SD

t

HD

D3

D2

D0

D1

DATAIN

tCD1

An

An+1

An+2

HOLD

DATAOUT

,

ADVANCE

COUNTER

WRITE TO

An+2

ADVANCE

COUNTER

WRITE TO

An+1

HOLD

REPEAT

READ LAST

ADS

ADDRESS

An

ADVANCE

COUNTER

READ

WRITE TO

ADS

ADDRESS

An

ADVANCE

COUNTER

READ

COUNTER

WRITE TO

An+2

COUNTER

READ

An+1

An+2

5687 drw 18

NOTES:

1. CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.

CE0, BEn = VIL; CE1 = VIH.

2.

3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.

4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid

ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.

5. CNTEN = V^ILadvances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is

written to during this cycle.

6. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.

6.42

17

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

(2)

Waveform of Interrupt Timing

CLK

L

t

SW

tHW

R/W

L

t

SA

3FFFF

SC

t

HA

ADDRESSL⁽³⁾

CEL⁽¹⁾

t

tHC

tINS

INT

R

t

INR

CLKR

t

SC

tHC

CER⁽¹⁾

R/WR

t

SW

t

HW

HA

t

SA

ADDRESSR⁽³⁾

3FFFF

5687 drw 19

NOTES:

1. CE0 = VIL and CE1 = VIH

2. All timing is the same for Left and Right ports.

3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

(1)

Truth Table III — Interrupt Flag

Left Port

Right Port

(3,4)

(2)

(3,4)

(2)

CLK

L

R/W

L

A

17L-A0L

CLK

R

R/W

R

A

17R-A0R

Function

CE

L

INT

X

L

CE

R

INT

R

L

3FFFF

X

L

Set Right INT

Reset Right INT

Set Left INT Flag

Reset Left INT Flag

R

Flag

!

X

L

3FFFF

3FFFE

X

H

R

Flag

X

L

X

L

H

L

3FFFE

H

X

L

5687 tbl 13

NOTES:

1. INTL and INTR must be initialized at power-up by Resetting the flags.

2. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.

3. A17X is a NC for IDT70T3799, therefore Interrupt Addresses are 1FFFF and 1FFFE.

4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

6.42

18

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Waveform of Collision Timing^(1,2)

Both Ports Writing with Left Port Clock Leading

CLK

L

t

OFS

tSA

tHA

ADDRESS ⁽⁴⁾

L

A

3

A

1

A2

A

0

t

COLR

tCOLS

COL

L

(3)

tOFS

CLK

R

t

SA

t

HA

(4)

ADDRESS

R

A

3

A2

A

0

A1

t

COLR

tCOLS

COLR

5687 drw 20

NOTES:

1. CE0 = VIL, CE1 = VIH.

2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.

3. Leading Port Output flag might output 3tCYC2 + tCOLS after Address match.

4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

Collision Detection Timing^(3,4)

tOFS (ns)

Cycle Time

NOTES:

1. Region 1

(1)

(2)

Region 1 (ns)

Region 2 (ns)

Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.

2. Region 2

Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.

while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.

3. All the production units are tested to midpoint of each region.

5ns

6ns

0 - 2.8

2.81 - 4.6

0 - 3.8

0 - 5.3

3.81 - 5.6

5.31 - 7.1

7.5ns

4. These ranges are based on characterization of a typical device.

56876 tbl 14

Truth Table IV — Collision Detection Flag

Left Port

Right Port

(2)

(1)

(2)

(1)

CLK

L

R/W

H

L

A

17L-A0L

CLK

R

R/W

R

A

17R-A0R

Function

CE

L

COL

H

L

CE

R

COL

H

R

Both ports reading. Not a valid collision.

No flag output on either port

L

MATCH

H

L

MATCH

!

Left port reading, Right port writing.

Valid collision, flag output on Left port.

H

L

H

Right port reading, Left port writing.

Valid collision, flag output on Right port.

L

H

L

Both ports writing. Valid collision. Flag

output on both ports.

L

!

5687 tbl 15

NOTES:

1. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.

2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.

6.42

19

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

(1,2)

Timing Waveform - Entering Sleep Mode

R/W

(3)

(1,2)

Timing Waveform - Exiting Sleep Mode

An

An+1

(5)

R/W

OE

(5)

Dn

Dn+1

DATAOUT

(4)

NOTES:

1. CE1 = VIH.

2. All timing is same for Left and Right ports.

3. CE0 has to be deactivated (CE0 = VIH) three cycles prior to asserting ZZ (ZZx = VIH) and held for two cycles after asserting ZZ (ZZx = VIH).

4. CE0 has to be deactivated (CE0 = VIH) one cycle prior to de-asserting ZZ (ZZx = VIL) and held for three cycles after de-asserting ZZ (ZZx = VIL).

5. The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.

6.42

20

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

alertflagasappropriate.Intheeventthatauserinitiatesaburstaccess

onbothportswiththesamestartingaddressonbothportsandoneorboth

portswritingduringeachaccess(i.e.,imposesalongstringofcollisions

on contiguous clock cycles), the alert flag will be asserted and cleared

everyothercycle.PleaserefertotheCollisionDetectiontimingwaveform

on Page 19.

Functional Description

TheIDT70T3719/99MprovidesatruesynchronousDual-PortStatic

RAM interface.Registeredinputsprovideminimalset-upandholdtimes

onaddress, data, andallcriticalcontrolinputs. Allinternalregistersare

clocked on the rising edge of the clock signal, however, the self-timed

internalwritepulsewidthisindependentofthecycletime.

CollisiondetectionontheIDT70T3719/99Mrepresentsasignificant

advanceinfunctionalityovercurrentsyncmulti-ports,whichhavenosuch

capability. InadditiontothisfunctionalitytheIDT70T3719/99Msustains

thekeyfeaturesofbandwidthandflexibility. Thecollisiondetectionfunction

isveryusefulinthecaseofburstingdata,orastringofaccessesmadeto

sequentialaddresses,inthatitindicatesaproblemwithintheburst,giving

theusertheoptionofeitherrepeatingtheburstorcontinuingtowatchthe

alert flag to see whether the number of collisions increases above an

acceptablethresholdvalue.Offeringthisfunctiononchipalsoallowsusers

to reduce their need for arbitration circuits, typically done in CPLD’s or

FPGA’s.Thisreducesboardspaceanddesigncomplexity,andgivesthe

usermoreflexibilityindevelopingasolution.

An asynchronous output enable is provided to ease asyn-

chronousbusinterfacing.Counterenableinputsarealsoprovidedtostall

the operation of the address counters for fast interleaved

memoryapplications.

AHIGHonCE0oraLOWonCE1 foroneclockcyclewillpowerdown

the internal circuitry to reduce static power consumption. Multiple chip

enables allow easier banking of multiple IDT70T3719/99Ms for depth

expansionconfigurations. TwocyclesarerequiredwithCE0 LOWand

CE1 HIGHtore-activatetheoutputs.

Interrupts

If the user chooses the interrupt function, a memory location (mail

boxormessagecenter)isassignedtoeachport. Theleftportinterrupt

flag (INTL) is asserted when the right port writes to memory location

3FFFE (HEX), where a write is defined as CER = R/WR = VIL per the

Truth Table I. The left port clears the interrupt through access of

addresslocation3FFFEwhenCEL = VILandR/WL=VIH.Likewise,the

right port interrupt flag (INTR) is asserted when the left

port writes to memory location 3FFFF (HEX) and to clear the interrupt

flag(INTR),therightportmustreadthememorylocation3FFFF(1FFFF

or1FFFEforIDT70T3799M).Themessage(72bits)at3FFFEor3FFFF

(1FFFF or 1FFFE for 70T3799M) is user-defined since it is an addres-

sableSRAMlocation.Iftheinterruptfunctionisnotused,addresslocations

3FFFE and 3FFFF (1FFFF or 1FFFE for IDT70T3799M) are not used

asmailboxes,butaspartoftherandomaccessmemory.RefertoTruth

Table III for the interrupt operation.

Sleep Mode

TheIDT70T3719/99Misequippedwithanoptionalsleeporlowpower

modeonbothports.Thesleepmodepinonbothportsisasynchronous

andactivehigh.Duringnormaloperation,theZZpinispulledlow.When

ZZispulledhigh,theportwillentersleepmodewhereitwillmeetlowest

possible power conditions. The sleep mode timing diagram shows the

modes ofoperation:NormalOperation,NoRead/WriteAllowedandSleep

Mode.

Fornormaloperationallinputsmustmeetsetupandholdtimesprior

tosleepand afterrecoveringfromsleep.Clocksmustalsomeetcyclehigh

and low times during these periods. Three cycles prior to asserting ZZ

(ZZx=VIH)andthreecyclesafterde-assertingZZ(ZZx=VIL),thedevice

mustbedisabledviathechipenablepins.Ifawriteorreadoperationoccurs

duringtheseperiods,thememoryarraymaybecorrupted.Validityofdata

outfromtheRAMcannotbeguaranteedimmediatelyafterZZisasserted

(priortobeinginsleep).Whenexitingsleepmode,thedevicemustbein

Read mode (R/Wx = VIH)when chip enable is asserted, and the chip

enablemustbevalidforonefullcyclebeforeareadwillresultintheoutput

ofvaliddata.

DuringsleepmodetheRAMautomaticallydeselectsitself.TheRAM

disconnectsitsinternalclockbuffer.Theexternalclockmaycontinuetorun

withoutimpactingtheRAMssleepcurrent(IZZ).Alloutputswillremainin

high-Zstatewhileinsleepmode.Allinputsareallowedtotoggle.TheRAM

will not be selected and will not perform any reads or writes.

Collision Detection

Collision is defined as an overlap in access between the two ports

resulting in the potential for either reading or writing incorrect data to a

specificaddress. Forthespecificcases:(a)Bothportsreading-nodata

iscorrupted,lost,orincorrectlyoutput,sonocollisionflagisoutputoneither

port.(b)Oneportwriting,theotherportreading-theendresultofthewrite

willstillbevalid. However, thereadingportmightcapturedatathatisin

astateoftransitionandhencethereadingport’scollisionflagisoutput.(c)

Bothportswriting-thereisariskthatthetwoportswillinterferewitheach

other, andthedatastoredinmemorywillnotbeavalidwritefromeither

port(itmayessentiallybearandomcombinationofthetwo). Therefore,

thecollisionflagisoutputonbothports. PleaserefertoTruthTableIVfor

all of the above cases.

Thealertflag (COL_X)isassertedonthe2ndor3rdrisingclockedge

oftheaffectedportfollowingthecollision,andremainslowforonecycle.

PleaserefertoCollisionDetectionTimingtableonPage19.Duringthat

nextcycle,theinternalarbitrationisengagedinresettingthealertflag(this

avoidsaspecificrequirementonthepartoftheusertoresetthealertflag).

Iftwocollisionsoccuronsubsequentclockcycles,thesecondcollisionmay

notgeneratetheappropriatealertflag.Athirdcollisionwillgeneratethe

6.42

21

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Depth and Width Expansion

The IDT70T3719/99M can also be used in applications requiring

expandedwidth,asindicatedinFigure4.Throughcombiningthecontrol

signals, the devices can be grouped as necessary to accommodate

applicationsneeding144-bits.

The IDT70T3719/99M features dual chip enables (refer to Truth

Table I) in order to facilitate rapid and simple depth expansion with no

requirements for external logic. Figure 4 illustrates how to control the

various chip enables in order to expand two devices in depth.

(1)

A18/A17

IDT70T3719/99M

CE

0

1

CE

0

CE

CE1

V

DD

VDD

Control Inputs

IDT70T3719/99M

CE

1

0

CE

1

0

CE

BE,

R/W,

Control Inputs

OE,

CLK,

Figure 4. Depth and Width Expansion with IDT70T3719/99M

ADS,

REPEAT,

CNTEN

,

5687 drw 23

NOTE:

1. A18 is for IDT70T3719, A17 is for IDT70T3799.

JTAG Functionality and Configuration

The IDT70T3719/99M is composed of two independent memory

arrays,andthuscannotbetreatedasasingleJTAGdeviceinthescan

chain. Thetwoarrays(AandB)eachhaveidenticalcharacteristicsand

commandsbutmustbetreatedasseparateentitiesinJTAGoperations.

Please refer to Figure 5.

Register Sizes, and System Interface Parameter tables. Specifically,

commands for Array B must precede those for Array A in any JTAG

operationssenttotheIDT70T3719/99M. PleasereferenceApplication

NoteAN-411,"JTAGTestingofMultichipModules"forspecificinstruc-

tionsonperformingJTAGtestingontheIDT70T3719/99M. AN-411is

availableatwww.idt.com.

.

JTAGsignalingmustbeprovidedseriallytoeacharrayandutilizethe

informationprovidedintheIdentificationRegisterDefinitions,Scan

IDT70T3719/99M

TDO

TDI

TDOA

TDIB

Array A

Array B

TCK

TMS

TRST

5687 drw 24

Figure 5. JTAG Configuration for IDT70T3719/99M

6.42

22

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

JTAG Timing Specifications

t

JCYC

tJR

t

JF

tJCL

tJCH

TCK

Device Inputs⁽¹⁾/

TDI/TMS

tJDC

tJS

tJH

Device Outputs⁽²⁾/

TDO

t

JRSR

tJCD

TRST

,

5687 drw 25

t

JRST

Figure 5. Standard JTAG Timing

NOTES:

1. Device inputs = All device inputs except TDI, TMS, and TRST.

2. Device outputs = All device outputs except TDO.

JTAG AC Electrical

Characteristics ^(1,2,3,4)

70T3719/99M

Max.

Symbol

Parameter

JTAG Clock Input Period

JTAG Clock HIGH

JTAG Clock Low

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset

Min.

100

40

Units

ns

____

t

JCYC

JCH

JCL

JR

JF

JRST

JRSR

JCD

JDC

JS

JH

t

ns

t

40

ns

3⁽¹⁾

ns

____

t

3⁽¹⁾

ns

____

t

____

t

50

ns

____

t

JTAG Reset Recovery

JTAG Data Output

JTAG Data Output Hold

JTAG Setup

50

ns

____

t

25

ns

____

t

0

ns

____

t

15

ns

t

JTAG Hold

ns

5687 tbl 16

NOTES:

1. Guaranteed by design.

2. 30pF loading on external output signals.

3. Refer to AC Electrical Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at

any speed specified in this datasheet.

6.42

23

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Identification Register Definitions

Value

Array A

Instruction Field Array B

Instruction Field Array A

Description

Reserved for Version number

Array B

0x0

Revision Number (31:28)

Revision Number (63:60)

0x0

IDT Device ID (27:12)⁽¹⁾

IDT JEDEC ID (11:1)

IDT Device ID (59:44)⁽¹⁾

IDT JEDEC ID (43:33)

0x330

0x33

1

0x330

0x33

1

Defines IDT Part number

Allows unique identification of device vendor as IDT

Indicates the presence of an ID Register

ID Register Indicator Bit (Bit 0)

ID Register Indicator Bit (Bit 32)

5687 tbl 17

NOTE:

1. Device ID for IDT70T3719M is 0x330. Device ID for IDT70T3799M is 0x331.

Scan Register Sizes

Bit Size

Array A

Bit Size

Register Name

Array B

70T3719M

Instruction (IR)

Bypass (BYR)

4

1

4

1

8

2

Identification (IDR)

32

64

Boundary Scan (BSR)

Note (3)

5687 tbl 18

System Interface Parameters

Instruction

Code

Description

EXTEST

00000000

Forces contents of the boundary scan cells onto the device outputs⁽¹⁾.

Places the boundary scan register (BSR) between TDI and TDO.

BYPASS

IDCODE

11111111

Places the bypass register (BYR) between TDI and TDO.

00100010

Loads the ID register (IDR) with the vendor ID code and places the

register between TDI and TDO.

01000100

Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers except INTx and COLx to a High-Z state.

HIGHZ

Uses BYR. Forces contents of the boundary scan cells onto the device

outputs. Places the bypass register (BYR) between TDI and TDO.

CLAMP

00110011

00010001

SAMPLE/PRELOAD

Places the boundary scan register (BSR) between TDI and TDO.

SAMPLE allows data from device inputs⁽²⁾to be captured in the

boundary scan cells and shifted serially through TDO. PRELOAD allows

data to be input serially into the boundary scan cells via the TDI.

RESERVED

01010101, 01110111,

10001000, 10011001,

10101010, 10111011,

11001100

Several combinations are reserved. Do not use codes other than those

identified above.

PRIVATE

01100110,11101110,

11011101

For internal use only.

5687 tbl 19

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local

IDT sales representative.

6.42

24

IDT70T3719/99M

High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Ordering Information

A

XXXXX

A

999

A

Process/

Temperature

Range

Device

Type

Power Speed

Package

Tube or Tray

Tape and Reel

Blank

8

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Blank

I

G⁽¹⁾

BB

Green

324-pin BGA (BBG-324)

Commercial Only

166

133

Speed in Megahertz

Commercial & Industrial

Standard Power

S

18Mbit (256K x 72) 2.5V Synchronous Dual-Port RAM

9Mbit (128K x 72) 2.5V Synchronous Dual-Port RAM

70T3719M

70T3799M

5687 drw 26

NOTE:

1. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyourlocalsalesoffice.

LEADFINISH(SnPb)partsareinEOLprocess. ProductDiscontinuationNotice-PDN#SP-17-02

IDT Clock Solution for IDT70T3719/99M Dual-Port

Dual-Port I/O Specitications

Clock Specifications

IDT

PLL

Clock Device

IDT

Non-PLL

Clock Device

IDT Dual-Port

Part Number

Input Duty

Cycle

Requirement

Input

Capacitance

Maximum

Frequency Tolerance

Jitter

Voltage

3.3/2.5

I/O

5T9010

5T905, 5T9050

5T907, 5T9070

70T3719/99M

LVTTL

15pF

40%

166

75ps

5T2010

5687 tbl 20

Datasheet Document History:

06/27/05:

07/11/07:

01/19/09:

08/06/10:

07/15/14:

02/14/18:

InitialDatasheet

RemovedAdvancedstatus

Page 25 Removed "IDT" from orderable part number

Page 3 Footnote5-correctedatypointhepackagebodyandball-pitchdimensions

Page 25 Added Tape & Reel to Ordering Information

ProductDiscontinuationNotice-PDN#SP-17-02

Last time buy expires June 15, 2018

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

408-284-2794

DualPortHelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

25


型号：	IDT70T3719_18
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	HIGH-SPEED SYNCHRONOUS DUAL-PORT STATIC RAM
文件：	总25页 (文件大小：345K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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