IDT70T651S15BC8 [IDT]
Dual-Port SRAM, 256KX36, 15ns, CMOS, PBGA256, BGA-256;
| 型号： | IDT70T651S15BC8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 256KX36, 15ns, CMOS, PBGA256, BGA-256 静态存储器 内存集成电路 |
| 文件： | 总27页 (文件大小：340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT70T651/9S
HIGH-SPEED 2.5V
256/128K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
◆
Busy and Interrupt Flags
On-chip port arbitration logic
Features
◆
◆
True Dual-Port memory cells which allow simultaneous
◆
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
access of the same memory location
High-speed access
◆
◆
◆
– Commercial:8/10/12/15ns(max.)
– Industrial: 10/12ns(max.)
◆
RapidWrite Mode simplifies high-speed consecutive write
◆
◆
◆
◆
Sleep Mode Inputs on both ports
cycles
◆
Supports JTAG features compliant to IEEE 1149.1
Single 2.5V (±100mV) power supply for core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad
Flatpack and 208-ball fine pitch Ball Grid Array.
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Dual chip enables allow for depth expansion without
external logic
◆
IDT70T651/9 easily expands data bus width to 72 bits or
more using the Master/Slave select when cascading more
than one device
M/S = VIH for BUSY output flag on Master,
◆
◆
◆
M/S = VIL for BUSY input on Slave
Functional Block Diagram
BE3L
BE3R
BE2R
BE2L
BE1L
BE0L
BE1R
BE0R
R/WL
R/WR
B B B B
E E E E
B
E
3
B B B
E E E
2 1 0
0
1
2
3
CE0L
CE1L
CE0R
CE1R
L
L
L
L
R R R R
OEL
OER
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
256/128K x 36
MEMORY
ARRAY
I/O0L- I/O35L
Di n_L
Di n_R
I/O0R -I/O35R
(1)
A
17R
0R
(1)
17L
Address
Decoder
A
Address
Decoder
ADDR_L
ADDR_R
A
A0L
CE0L
CE1L
ARBITRATION
CE0R
CE1R
TDI
TC K
TMS
TRST
JTAG
INTERRUPT
SEMAPHORE
LOGIC
TD O
OE
L
OE
R
R/WL
R/W
R
(2,3)
(3)
(2,3)
R
BUSY
L
BUSY
SEM
M/S
SEM
L
R
(3)
INT
L
INT
R
ZZ
(4)
(4)
ZZR
ZZL
CONTROL
LOGIC
NOTES:
1. Address A17x is a NC for IDT70T659.
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
4869 drw 01
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep
mode pins themselves (ZZx) are not affected during sleep mode.
APRIL 2004
1
DSC-5632/4
©2004IntegratedDeviceTechnology,Inc.
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70T651/9 is a high-speed 256/128K x 36 Asynchronous
Dual-Port Static RAM. The IDT70T651/9 is designed to be used as a
stand-alone9216/4608K-bitDual-PortRAMorasacombinationMAS-
TER/SLAVEDual-PortRAMfor72-bit-or-morewordsystem.Usingthe
IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider
memory system applications results in full-speed, error-free operation
feature controlled by the chip enables (either CE0 or CE1) permit the
on-chip circuitry of each port to enter a very low standby power mode.
TheIDT70T651/9hasaRapidWriteModewhichallowsthedesigner
toperformback-to-backwriteoperationswithoutpulsingtheR/Winput
eachcycle.Thisisespeciallysignificantatthe8and10nscycletimesof
the IDT70T651/9, easing design considerations at these high perfor-
mancelevels.
withouttheneedforadditionaldiscretelogic.
This device provides two independent ports with separate control,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
reads or writes to any location in memory. An automatic power down
The70T651/9cansupportanoperatingvoltageofeither3.3Vor2.5V
on one or both ports, controlled by the OPT pins. The power supply for
the core of the device (VDD) is at 2.5V.
2
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinConfiguration(1,2,3)
70T651/9BC
BC-256(5,6)
256-Pin BGA
Top View
03/18/03
A1
A2
A3
A6
A7
A8
A9
A11
A12
A13
A14
A4
A5
A10
A15
A16
(4)
NC
TDI
NC
A
11L
A
8L
9L
7L
BE2L CE1L
INT
L
A
5L
A
2L
A
0L
A
17L
A
14L
OE
L
NC
NC
B1
B2
B3
B6
B7
B9
CE0L
B11
B12
B13
B4
B5
B8
B10
B14
B15
B16
I/O18L NC TDO
A
12L
A
NC
A4L
A
1L
NC
A
15L
BE3L
R/W
L
NC I/O17L NC
C1
C5
C6
C2
C3
C4
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
I/O18R
A
13L
A
10L
I/O19L
V
SS
A
16L
A
BE1L BE0L SEM
L
BUSY
L
A6L
A
3L
I/O16L
OPT
L
I/O17R
D1
D2
D6
D9
D11
D3
D5
D7
D8
D10
D12
D13
D14
D15
D16
D4
I/O20R I/O19R
VDDQL
VDDQL
VDDQR
I/O20L
VDDQL
V
DDQR
VDDQR
VDDQL
VDDQR
VDD I/O15R I/O15L I/O16R
V
DD
E5
E6
E7
E8
E9
E10
E11
E12
E13
E1
E2
E3
E4
DDQL
E14
E16
E15
V
DD
V
DD
V
SS
V
SS
SS
SS
V
SS
SS
SS
SS
VSS
V
DD
VDD
V
DDQR
I/O13L
I/O21R I/O21L I/O22L
V
I/O14R
I/O14L
F7
F1
F2
F3
F5
F6
F9
F10
F14
F15
F16
F11
F13
F4
F8
F12
V
SS
V
DD
NC
V
V
SS
I/O23L I/O22R I/O23R
I/O12R I/O13R I/O12L
DDQR
V
V
SS
V
DD
V
V
DDQL
G1
G5
H5
G2
G4
G6
G8
G9
G3
G7
G10
G12
G13
G14
I/O10L I/O11L I/O11R
DDQL
G15
G16
G11
I/O24R
V
SS
I/O24L
V
DDQR
V
SS
V
V
I/O25L
V
SS
VSS
VSS
V
V
SS
H13
H11
H12
H16
H7
H8
H9
H10
H14
H15
H3
H4
H6
H1
H2
VDDQL
VSS
V
SS
I/O10R
V
SS
V
SS
V
V
SS
SS
I/O9R IO9L
V
SS
VSS
I/O26R
V
DDQR
I/O26L I/O25R
J1
J2
J5
J3
J4
J6
J7
J8
J9
J13
J10
J11
J12
J14
J15
J16
I/O27L
I/O28R I/O27R
V
DDQL ZZ
R
V
SS
V
SS
V
SS
V
SS
SS
V
DDQR
I/O8R
V
V
SS
ZZ
L
I/O7R I/O8L
K6
K8
K10
K12
K13
K5
K7
K9
K11
K2
K4
K15
K16
K1
K3
K14
V
SS
V
SS
V
SS
SS
V
SS
V
DDQR
V
SS
V
SS
SS
SS
V
V
SS
SS
I/O29L
V
DDQL
I/O6L I/O7L
I/O29R
I/O28L
I/O6R
L7
L8
L11
L12
L13
L3
L4
L5
L6
L9
L10
L15
L16
L1
L2
L14
V
V
SS
V
V
DD
V
DDQL
I/O5L
I/O30R
V
DDQR
V
DD
NC
V
SS
V
I/O4R I/O5R
I/O30L I/O31R
M5
M6
M7
M8
M9
M10
M11
M12
M13
M1 M2
M3
M4
M16
M14
M15
V
DD
V
DD
V
V
SS
V
SS
V
SS
V
DD
V
DD
V
DDQL
I/O32R I/O32L I/O31L
V
DDQR
I/O4L
I/O3R I/O3L
N8
N12
N16
N13
N4
N5
N6
DDQR
N7
DDQL
N9
N10
N11
N15
N1
N2
N3
N14
VDDQL
VDDQL
VDD
I/O2R
I/O1R
V
DDQR
V
V
V
DDQR
V
DDQR
VDDQL
V
DD
I/O33L I/O34R I/O33R
I/O2L
P1
P2
P3
P4
P5
P7
P8
P9
P10
P11
P12
P14
P15
P16
P6
P13
I/O35R I/O34L TMS
A16R
A13R
A7R BE1R BE0R SEM
R
BUSY
R
A6R
I/O0L I/O0R I/O1L
A10R
A3R
R5
R6
R7
R8
R9
R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R15
,
A
15R
A
12R
A
9R
BE3R CE0R R/W
R
M/S
NC
I/O35L NC TRST NC
A4R
A1R OPTR
NC
T2
T3
T4
17R
T1
T5
T8
T9
T15
T16
T6
T7
T10
T11
T12
T13
2R
T14
(4)
TCK
NC
A
NC
A
14R
BE2R CE1R
NC
NC
A
11R
A
8R
OE
R
INT
R
A
5R
A
A
0R
5632 drw 02f
,
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground supply.
4. A17X is a NC for IDT70T659.
5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
3
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
03/18/03
I/O16L
156
1
2
3
4
5
6
I/O19L
I/O19R
I/O20L
I/O20R
I/O16R
155
I/O15L
154
I/O15R
153
V
V
SS
V
DDQL
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
DDQL
V
SS
I/O14L
I/O14R
I/O13L
I/O13R
7
8
9
I/O21L
I/O21R
I/O22L
I/O22R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
V
V
SS
V
DDQR
DDQR
V
SS
I/O12L
I/O12R
I/O11L
I/O11R
I/O23L
I/O23R
I/O24L
I/O24R
V
V
SS
V
DDQL
DDQL
V
SS
I/O10L
I/O10R
I/O9L
I/O25L
I/O25R
I/O26L
I/O26R
70T651/9DR
DR-208(5,6,7)
I/O9R
V
V
V
V
V
V
SS
V
DDQR
DDQR
DD
ZZR
V
V
DD
DD
DD
SS
V
V
SS
SS
208-Pin
PQFP
Top View(8)
SS
ZZ
L
V
DDQL
SS
V
DDQL
V
I/O8R
I/O8L
I/O7R
I/O7L
I/O27R
I/O27L
I/O28R
I/O28L
V
V
SS
V
DDQR
DDQR
V
SS
I/O6R
I/O6L
I/O5R
I/O5L
I/O29R
I/O29L
I/O30R
I/O30L
V
V
SS
V
DDQL
DDQL
V
SS
I/O4R
I/O4L
I/O3R
I/O3L
I/O31R
I/O31L
I/O32R
I/O32L
V
V
SS
V
DDQR
DDQR
V
SS
I/O2R
I/O2L
I/O1R
I/O1L
I/O33R
I/O33L
I/O34R
I/O34L
5632 drw 02d
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V) and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground.
4. A17X is a NC for IDT70T659.
5. Package body is approximately 28mm x 28mm x 3.5mm.
6. This package code is used to reference the package diagram.
7. 8ns Commercial and 10ns Industrial speed grades are not available in the DR-208 package.
8. This text does not indicate orientation of the actual part-marking.
4
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinConfigurations(1,2,3)(con't.)
03/18/03
1
2
3
4
5
6
7
8
9
11 12 13 14
10
16 17
15
I/O19L
V
V
V
DD
SS
SS
A
12L
A
B
C
D
E
F
I/O18L
V
SS
A
8L
A
0L
I/O17L
VSS
A
16L
A4
L
OPTL
TDO
NC
BE1L
SEM
L
INT
L
A
B
C
D
E
F
(4)
I/O20R
V
SS
A9L
I/O18R
I/O15R
A5
L
I/O16L
TDI
A
17L
A
13L
A
1L
2L
VDDQR
V
SS
DD
CE0L
BUSY
L
L
BE2L
BE3L
A
10L
7L
VSS
I/O19R
V
DD
NC
A
14L
CE1L
A6
L
A
V
I/O16R I/O15L
V
DDQL
VDDQR
R/W
I/O22L
VSS
I/O17R
I/O12L
I/O21L
A
15L
A
11L
A
V
DD
VDDQL
I/O14L I/O14R
I/O13L
I/O20L
NC
VDD
BE0L
A3L
OE
L
I/O23L I/O22R
VDDQR I/O21R
I/O13R
I/O12R
VSS
V
DDQL
I/O23R
VSS
V
DDQR
I/O24L
I/O25L
VSS
I/O11L
I/O10L
I/O26L
V
SS
I/O9L
VDDQL
I/O24R
I/O25R
I/O11R
I/O10R
G
H
J
G
H
J
70T651/9BF
BF-208(5,6)
VDD
I/O26R
V
DDQR
VDD
I/O9R
V
SS
V
DD
V
DDQL
ZZ
L
V
SS
VDDQR
VDD
V
SS
ZZR
208-Ball
fpBGA
Top View(7)
VDDQL
I/O7R
I/O6R
VSS
I/O8R
I/O28R
VSS
I/O27R
K
L
VS S
K
L
I/O29R I/O28L
VDDQR
I/O27L
I/O7L
I/O6L
V
SS
I/O8L
V
DDQL
I/O30R
VSS
I/O29L
VSS
I/O5R
I/O4R
V
DDQR
M
N
P
R
T
M
N
P
R
T
I/O31L
I/O32R
VSS
I/O3R
I/O2L
V
DDQL
I/O31R I/O30L
I/O5L
I/O4L
I/O3L
I/O32L
I/O33L
VDDQR
V
DD
INT
R
A
4R
VSS
A
16R
A
12R
A8R
TRST
I/O35R
TCK
BE1R
SEM
R
(4)
V
SS
VDDQL
I/O1R
VDDQR
A
17R
V
SS
SS
A5R
A
1R
2R
A
13R
14R
A9R
VSS
I/O34R
BE2R
BE3R
CE0
R
BUSY
R
I/O0R
VS S
VSS
V
A
I/O2R
I/O1L
A6R
A
A10R
NC
CE1R
I/O33R I/O34L
V
DDQL TMS
R/
W
R
V
DD
OPT
R
I/O0L
VDD
A
3R
A
0R
A
11R
A7R
VSS
V
DD
M/S
I/O35L
NC
A15R
BE0R
OE
R
U
U
5632 drw 02e
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V) and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground.
4. A17X is a NC for IDT70T659.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
5
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
CE1R
Names
Chip Enables (Input)
CE0L
R/W
OE
,
CE1L
CE0R
R/W
OE
,
L
R
Read/Write Enable (Input)
Output Enable (Input)
L
R
(1)
(1)
A
0L - A17L
A
0R - A17R
Address (Input)
I/O0L - I/O35L
I/O0R - I/O35R
Data Input/Output
Semaphore Enable (Input)
Interrupt Flag (Output)
SEM
INT
BUSY
BE0L - BE3L
L
SEM
INT
BUSY
BE0R - BE3R
R
L
R
Busy Flag (Output)
L
R
Byte Enables (9-bit bytes) (Input)
Power (I/O Bus) (3.3V or 2.5V)(2) (Input)
Option for selecting VDDQX(2,3) (Input)
Sleep Mode Pin(4) (Input)
Master or Slave Select (Input)(5)
Power (2.5V)(2) (Input)
V
DDQL
VDDQR
OPT
L
OPTR
ZZL
ZZR
M/S
NOTES:
V
V
DD
SS
1. Address A17x is a NC for IDT70T659.
Ground (0V) (Input)
2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on I/OX.
TDI
TDO
TCK
Test Data Input
3. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that
port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are
not affected during sleep mode. It is recommended that boundry scan not be
operated during sleep mode.
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
TMS
TRST
Reset (Initialize TAP Controller) (Input)
5632 tbl 01
5. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master
(M/S=VIH).
6
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2)
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
CE
X
1
R/W
X
X
X
L
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
MODE
OE
X
X
X
X
X
X
X
X
X
X
L
SEM CE
0
BE
3
BE
2
BE
1
BE0
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
H
H
H
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z Deselected–Power Down
High-Z Deselected–Power Down
High-Z All Bytes Deselected
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
DIN
Write to Byte 0 Only
H
H
H
L
L
D
IN
High-Z Write to Byte 1 Only
High-Z Write to Byte 2 Only
High-Z Write to Byte 3 Only
H
H
L
L
D
IN
High-Z
High-Z
H
H
L
L
D
IN
High-Z
High-Z
H
L
L
High-Z
DIN
DIN
Write to Lower 2 Bytes Only
H
L
H
L
L
D
IN
IN
D
IN
IN
High-Z
High-Z Write to Upper 2 bytes Only
L
L
L
D
D
DIN
DIN
Write to All Bytes
Read Byte 0 Only
H
H
H
L
H
H
L
H
L
L
H
H
H
H
H
H
H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
L
H
H
H
L
DOUT
High-Z Read Byte 1 Only
High-Z Read Byte 2 Only
High-Z Read Byte 3 Only
L
H
H
L
DOUT
High-Z
High-Z
L
H
H
L
DOUT
High-Z
High-Z
L
H
L
High-Z
DOUT
DOUT
Read Lower 2 Bytes Only
High-Z Read Upper 2 Bytes Only
Read All Bytes
L
H
L
H
L
D
OUT
OUT
D
OUT
OUT
High-Z
L
L
L
D
D
DOUT
DOUT
H
X
L
L
L
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z Outputs Disabled
High-Z High-Z Sleep Mode
X
X
X
X
5632 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table II – Semaphore Read/Write Control(1)
Inputs(1)
BE
Outputs
(2)
R/W
H
I/O1-35
I/O
0
Mode
CE
OE
L
BE
3
2
BE
1
BE
0
SEM
H
H
L
L
X
X
L
X
X
L
X
X
L
L
L
L
L
DATAOUT
DATAOUT Read Data in Semaphore Flag(3)
X
X
DATAIN
Write I/O
0 into Semaphore Flag
↑
______
______
X
X
X
Not Allowed
5632 tbl 03
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O35). These eight semaphore flags are addressed by A0-A2.
2. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.
3. Each byte is controlled by the respective BEn. To read data BEn = VIL.
7
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
RecommendedOperating
RecommendedDCOperating
TemperatureandSupplyVoltage(1)
Conditions with VDDQ at 2.5V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min.
2.4
2.4
0
Typ.
2.5
2.5
0
Max.
2.6
2.6
0
Unit
V
Ambient
V
DD
DDQ
SS
Grade
Commercial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
V
+
+
DD
V
V
2.5V
2.5V
100mV
100mV
V
V
Industrial
0V
Input High Volltage
(Address, Control &
Data I/O Inputs)(3)
V
DDQ + 100mV(2)
____
1.7
1.7
V
V
5632 tbl 04
V
IH
IH
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
Input High Voltage _
JTAG
V
V
DD + 100mV(2)
____
Capacitance(1)
V
V
V
IH
IL
IL
V
DD - 0.2V
-0.3(1)
V
DD + 100mV(2)
V
V
Input High Voltage -
ZZ, OPT, M/S
____
____
____
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Input Low Voltage
0.7
0.2
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
Input Low Voltage -
ZZ, OPT, M/S
-0.3(1)
V
CIN
V
8
pF
5632 tbl 05
NOTES:
(3)
OUT
C
V
10.5
pF
1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is
less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VSS(0V), and VDDQX for that port must be
supplied as indicated above.
5632 tbl 08
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
RecommendedDCOperating
Conditions with VDDQ at 3.3V
AbsoluteMaximumRatings(1)
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min.
2.4
3.15
0
Typ.
2.5
3.3
0
Max.
2.6
3.45
0
Unit
V
Symbol
Rating
Commercial
& Industrial
Unit
V
V
DD
DDQ
SS
V
V
V
TE RM
V
DD Terminal Voltage
-0.5 to 3.6
V
V
(VDD
)
with Respect to GND
Input High Voltage
(Address, Control
&Data I/O Inputs)(3)
(2 )
V
DDQ + 150mV(2)
V
V
V
(VDDQ
TE RM
V
DDQ Terminal Voltage
-0.3 to VDDQ + 0.3
-0.3 to VDDQ + 0.3
-55 to +125
V
____
2.0
1.7
V
IH
IH
)
with Respect to GND
_
(2)
Input High Voltage
JTAG
V
TERM
Input and I/O Terminal
Voltage with Respect to GND
V
DD + 100mV(2)
____
V
V
(INPUTS and I/O's)
Input High Voltage -
ZZ, OPT, M/S
(3)
oC
oC
DD + 100mV(2)
V
V
____
____
____
Temperature
Under Bias
TBIAS
V
V
V
IH
IL
IL
V
DD - 0.2V
-0.3(1)
V
Input Low Voltage
0.8
0.2
Storage
Temperature
-65 to +150
TSTG
Input Low Voltage -
ZZ, OPT, M/S
-0.3(1)
V
TJN
Junction Temperature
+150
50
oC
5632 tbl 06
NOTES:
I
OUT(For VDDQ = 3.3V) DC Output Current
mA
1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is
less.
I
OUT(For VDDQ = 2.5V) DC Output Current
40
mA
5632 tbl 07
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VDD (2.5V), and VDDQX for that port must be
supplied as indicated above.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any Input or I/O pin cannot exceed VDDQ during power
supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
8
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T651/9S
Symbol
Parameter
Test Conditions
DDQ = Max., VIN = 0V to VDDQ
DD = Max. IN = 0V to VDD
= VIH or CE = VIL, VOUT = 0V to VDDQ
OL = +4mA, VDDQ = Min.
OH = -4mA, VDDQ = Min.
OL = +2mA, VDDQ = Min.
OH = -2mA, VDDQ = Min.
Min.
Max.
10
Unit
µA
µA
µA
V
Input Leakage Current(1)
V
V
___
___
___
___
|ILI
|ILI
|ILO
|
|
JTAG & ZZ Input Leakage Current(1,2)
Output Leakage Current(1,3)
,
V
+30
10
|
CE
0
1
V
OL (3.3V) Output Low Voltage(1)
OH (3.3V) Output High Voltage(1)
OL (2.5V) Output Low Voltage(1)
OH (2.5V) Output High Voltage(1)
I
0.4
___
V
I
2.4
V
___
V
I
0.4
V
___
V
I
2.0
V
5632 tbl 09
NOTES:
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 6 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 2.5V ± 100mV)
70T651/9S8(7)
Com'l Only
70T651/9S10
Com'l
70T651/9S12
Com'l
70T651/9S15
Com'l Only
& Ind(7)
& Ind
Symbol
Parameter
Test Condition
= VIL
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
405
445
120
145
265
290
10
Typ.(4)
Max.
355
395
105
130
230
255
10
Typ.(4)
Max. Unit
IDD
Dynamic Operating
Current (Both
Ports Active)
mA
305
CE
L
and CE
R
,
S
S
S
S
S
S
S
S
S
S
S
S
350
475
300
300
90
90
200
200
2
300
300
75
75
180
180
2
225
Outputs Disabled
____
____
____
____
(1)
IND
f = fMAX
(6)
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
mA
mA
mA
mA
CEL
= CE
R
= VIH
COM'L
IND
115
140
60
85
(1)
f = fMAX
____
____
____
____
(6)
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
COM'L
IND
240
315
150
200
____
____
____
____
(1)
f = fMAX
ISB3
Full Standby Current Both Ports CEL and
COM'L
IND
2
10
2
10
(Both Ports - CMOS CER > VDD - 0.2V, VIN > VDD - 0.2V
____
____
____
____
or VIN < 0.2V, f = 0(2)
2
20
2
20
Level Inputs)
(6)
CE"A" < 0.2V and CE"B" > VDD - 0.2V(5)
IN > VDD - 0.2V or VIN < 0.2V, Active
Port, Outputs Disabled, f = fMAX
ISB4
Full Standby Current
(One Port - CMOS
Level Inputs)
COM'L
IND
240
315
200
200
2
265
290
10
180
180
2
230
255
10
150
200
V
____
____
____
____
(1)
IZZ
Sleep Mode Current ZZL = ZZR =
(Both Ports - TTL
Level Inputs)
V
IH
mA
COM'L
IND
2
10
2
10
(1)
f = fMAX
____
____
____
____
2
20
2
20
5632 tbl 10
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS" at input
levels of GND to 3.3V.
2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 100mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V
CEX > VDDQX - 0.2V means CE0X > VDDQX - 0.2V or CE1X < 0.2V.
"X" represents "L" for left port or "R" for right port.
6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and /or ZZR = VIH.
7. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
9
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels
GND to 3.0V / GND to 2.4V
2ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V/1.25V
1.5V/1.25V
Figure 1
5632 tbl 11
50Ω
50Ω
,
DATAOUT
1.5V/1.25
10pF
(Tester)
5632 drw 03
Figure 1. AC Output Test load.
4
3.5
3
2.5
∆ tAA/tACE
(Typical, ns)
2
1.5
1
0.5
0
0
160
20
40
60
120
140
80
100
∆
Capacitance (pF) from AC Test Load
5632 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
10
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
70T651/9S8(5)
Com'l Only
70T651/9S10
Com'l
70T651/9S12
Com'l
& Ind
70T651/9S15
Com'l Only
& Ind(5)
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
LZOB
HZ
PU
PD
SOP
SAA
SOE
Read Cycle Time
8
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
t
Address Access Time
8
8
4
10
10
5
12
12
6
15
15
7
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time
____
____
____
____
____
____
____
____
____
____
____
____
t
t
t
4
5
6
7
____
____
____
____
t
Output Hold from Address Change
3
3
0
0
3
3
0
0
3
3
0
0
3
3
0
0
t
Output Low-Z Time Chip Enable and Semaphore(1,2)
Output Low-Z Time Output Enable and Byte Enable(1,2)
Output High-Z Time(1,2)
____
____
____
____
____
____
____
____
t
t
3.5
4
6
8
t
Chip Enable to Power Up Time(2)
0
0
0
0
____
____
____
____
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
7
4
8
5
8
4
8
6
12
8
____
____
____
____
t
____
____
____
____
t
t
2
2
10
5
2
12
6
2
15
7
____
____
____
____
t
Semaphore Output Enable Access Time
ns
5632tbl 12
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(4)
70T651/9S8(5)
Com'l Only
70T651/9S10
Com'l
70T651/9S12
Com'l
& Ind
70T651/9S15
Com'l Only
& Ind(5)
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
DH
WZ
OW
SWRD
SPS
Write Cycle Time
8
6
6
0
6
0
4
10
7
12
9
15
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
7
9
t
0
0
t
7
9
12
0
t
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
0
0
t
5
7
10
t
0
0
0
0
Write Enable to Output in High-Z(1,2)
Output Active from End-of-Write(1,2)
SEM Flag Write to Read Time
SEM Flag Contention Window
3.5
4
6
8
____
____
____
____
t
____
____
____
____
t
3
4
4
3
5
5
3
5
5
3
5
5
____
____
____
____
____
____
____
____
t
t
ns
5632 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when
CE0 = VIL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
5. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
11
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE(6)
(4)
tAOE
OE
(4)
tABE
BEn
R/W
tOH
(1)
tLZ/tLZOB
VALID DATA(4)
DATAOUT
BUSYOUT
(2)
tHZ
.
(3,4)
5632 drw 06
tBDD
NOTES:
1. Timing depends on which signal is asserted last, OE, CE or BEn.
2. Timing depends on which signal is de-asserted first CE, OE or BEn.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, tABE or tBDD.
5. SEM = VIH.
6. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.
Timing of Power-Up Power-Down
CE
tPU
tPD
ICC
50%
50%
.
5632 drw 07
ISB
12
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
t
WC
ADDRESS
(7)
t
HZ
OE
t
AW
CE or SEM(9)
BEn(9)
R/W
(3)
(2)
tWP
(6)
t
WR
tAS
(7)
(7)
tWZ
t
OW
(4)
(4)
DATAOUT
DATAIN
t
DW
tDH
5632 drw 10
.
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5,8)
t
WC
ADDRESS
t
AW
CE or SEM(9)
BEn(9)
(6)
AS
(3)
WR
(2)
t
t
EW
t
R/W
t
DW
tDH
DATAIN
.
.
5632 drw 11
NOTES:
1. R/W or CE or BEn = VIH during all address transitions for Write Cycles 1 and 2.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE, BEn or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL
and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
13
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
takentostillmeettheWriteCycletime(tWC),thetimeinwhichtheAddress
inputsmustbestable. Inputdatasetupandholdtimes(tDW andtDH)will
nowbereferencedtotheendingaddresstransition. InthisRapidWrite
Mode theI/OwillremainintheInputmodeforthedurationoftheoperations
duetoR/Wbeingheldlow. AllstandardWriteCyclespecificationsmust
beadheredto.However,tAS andtWR areonlyapplicablewhenswitching
between read and write operations. Also, there are two additional
conditionsontheAddressInputsthatmustalsobemettoensurecorrect
addresscontrolledwrites. Thesespecifications,theAllowableAddress
Skew(tAAS)andtheAddressRise/Falltime(tARF),mustbemettousethe
RapidWriteMode. Iftheseconditionsarenotmetthereisthepotentialfor
inadvertent write operations at random intermediate locations as the
devicetransitionsbetweenthedesiredwriteaddresses.
RapidWrite Mode Write Cycle
Unlike other vendors' Asynchronous Random Access Memories,
theIDT70T651/9iscapableofperformingmultipleback-to-backwrite
operations without having to pulse the R/W, CE, or BEn signals high
duringaddresstransitions. ThisRapidWriteModefunctionalityallowsthe
systemdesignertoachieveoptimumback-to-backwritecycleperformance
withoutthedifficulttaskofgeneratingnarrowresetpulseseverycycle,
simplifyingsystemdesignandreducingtimetomarket.
DuringthisnewRapidWriteMode,theendofthewritecycleisnow
definedbytheendingaddresstransition,insteadoftheR/WorCEorBEn
transition to the inactive state. R/W, CE, and BEn can be held active
throughouttheaddresstransitionbetweenwritecycles.Caremustbe
Timing Waveform of Write Cycle No. 3, RapidWrite Mode Write Cycle(1,3)
(4)
WC
t
WC
t
t
WC
ADDRESS
(2)
EW
t
CE or SEM(6)
BEn
R/W
t
WR
t
WP
(5)
OW
(5)
WZ
t
t
DATAOUT
t
DH
t
DH
t
DH
t
DW
tDW
t
DW
DATAIN
5632 drw 08
NOTES:
1. OE = VIL for this timing waveform as shown. OE may equal VIH with same write functionality; I/O would then always be in High-Z state.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle. The last transition LOW of CE, BEn, and
R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence.
3. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes.
5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
6. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL
and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
14
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics over the Operating Temperature Range
and Supply Voltage Range for RapidWrite Mode Write Cycle(1)
Symbol
Parameter
Min
Max
Unit
____
t
AAS
Allowable Address Skew for RapidWrite Mode
Address Rise/Fall Time for RapidWrite Mode
1
ns
____
t
ARF
1.5
V/ns
5632 tbl 14
NOTE:
1. Timing applies to all speed grades when utilizing the RapidWrite Mode Write Cycle.
Timing Waveform of Address Inputs for RapidWrite Mode Write Cycle
A
0
t
ARF
t
AAS
(1)
A
17
t
ARF
5632 drw 09
NOTE:
1. A16 for IDT70T659.
15
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
t
tAW
tWR
ACE
tEW
SEM(1)
tOH
tSOP
tDW
OUT
DATA
VALID(2)
I/O
IN
DATA VALID
tAS
tWP
tDH
R/W
tSWRD
tSOE
OE
tSOP
Write Cycle
Read Cycle
.
5632 drw 12
NOTES:
1. CE0 = VIH and CE1 = VIL are required for the duration of both the write cycle and the read cycle waveforms shown above. Refer to Truth Table II for details and for
appropriate BEn controls.
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O35) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
t
SPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
.
5632 drw 13
NOTES:
1. DOR = DOL = VIL, CEL = CER = VIH. Refer to Truth Table II for appropriate BE controls.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
16
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70T651/9S8(6)
Com'l Only
70T651/9S10
Com'l
70T651/9S12
Com'l
70T651/9S15
Com'l Only
& Ind(6)
& Ind
Symbol
BUSY TIMING (M/S=VIH
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
8
8
8
10
10
10
12
12
12
15
15
15
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
t
8
10
12
15
____
____
____
____
t
2.5
2.5
2.5
2.5
____
____
____
____
BUSY Disable to Valid Data(3)
t
8
10
12
15
t
Write Hold After BUSY(5)
6
7
9
12
____
____
____
____
BUSY TIMING (M/S=VIL
)
____
____
____
____
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
6
0
7
0
9
0
ns
ns
tWH
12
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
12
12
14
14
16
16
20
20
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
5632 tbl 15
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1,2,3)
70T651/9S8(4)
Com'l Only
70T651/9S10
Com'l
70T651/9S12
Com'l
70T651/9S15
Com'l Only
& Ind(4)
& Ind
Symbol
SLEEP MODE TIMING (ZZx=VIH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
)
____
____
____
____
____
____
____
____
____
____
____
____
t
ZZS
ZZR
ZZPD
ZZPU
Sleep Mode Set Time
8
8
10
10
12
12
15
15
t
Sleep Mode Reset Time
t
Sleep Mode Power Down Time(5)
Sleep Mode Power Up Time(5)
8
10
12
15
____
____
____
____
t
0
0
0
0
5632 tbl 15a
NOTES:
1. Timing is the same for both ports.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected
during sleep mode. It is recommended that boundary scan not be operated during sleep mode.
3. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
4. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
5. This parameter is guaranteed by device characterization, but is not production tested.
17
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
TimingWaveformof WritewithPort-to-PortReadandBUSY (M/S =VIH)(2,4,5)
tWC
MATCH
ADDR"A"
t
WP
R/W"A"
t
DH
t
DW
VALID
DATAIN "A"
(1)
APS
t
MATCH
ADDR"B"
t
BDA
t
BAA
tBDD
BUSY"B"
t
WDD
DATAOUT "B"
VALID
(3)
tDDD
.
5632 drw 14
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CE0L = CE0R = VIL; CE1L = CE1R = VIH.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
t
WP
R/W"A"
(3)
WB
t
BUSY"B"
(1)
t
WH
(2)
R/W"B"
.
NOTES:
5632 drw 15
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB only applies to the slave mode.
18
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(M/S = VIH)(1)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
tAPS
CE"B"
tBAC
tBDC
BUSY"B"
.
5632 drw 16
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(M/S = VIH)(1,3,4)
ADDR"A"
ADDRESS "N"
(2)
tAPS
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
,
5632 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. CEX = VIL when CE0X = VIL and CE1X = VIH. CEX = VIH when CE0X = VIH and/or CE1X = VIL.
4. CE0X = OEX = BEnX = VIL. CE1X = VIH.
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1,2)
70T651/9S8(3)
Com'l Only
70T651/9S10
Com'l
70T651/9S12
Com'l
70T651/9S15
Com'l Only
& Ind(3)
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
0
ns
ns
ns
ns
t
0
0
0
0
____
____
____
____
t
8
8
10
10
12
12
15
15
____
____
____
____
t
Interrupt Reset Time
5632 tbl 16
NOTES:
1. Timing is the same for both ports.
2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
3. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
19
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
(2)
ADDR"A"
INTERRUPT SET ADDRESS
(5)
(4)
t
WR
tAS
(3)
CE"A"
R/W"A"
INT"B"
(4)
tINS
.
5632 drw 18
tRC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
(4)
tAS
(3)
CE"B"
OE"B"
INT"B"
(4)
tINR
.
5632 drw 19
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. CEX = VIL means CE0X = VIL and CE1X = VIH. CEX = VIH means CE0X = VIH and/or CE1X = VIL.
4. Timing depends on which enable signal (CE or R/W) is asserted last.
5. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III — Interrupt Flag(1,4)
Left Port
Right Port
(5)
(5)
R/W
L
L
A
17L-A0L
3FFFF
X
R/W
X
R
A
17R-A0R
Function
CE
L
L
OE
X
L
INT
L
CE
R
OE
R
INTR
X
X
X
X
L(2)
H(3)
X
Set Right INT
Reset Right INT
Set Left INT Flag
Reset Left INT Flag
R
Flag
X
X
X
X
X
L
L
3FFFF
3FFFE
X
R
Flag
X
X
X
X
L(3)
L
L
X
L
X
L
L
3FFFE
H(2)
X
X
X
X
L
5632 tbl 17
NOTES:
1. Assumes BUSYL = BUSYR =VIH. CE0X = VIL and CE1X = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. A17x is a NC for IDT70T659. Therefore, Interrupt Addresses are 1FFFF and 1FFFE.
20
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IV —
AddressBUSY Arbitration
Inputs
Outputs
(4)
A
OL-A17L
(5)
(5)
(1)
(1)
A
OR-A17R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
X
NO MATCH
MATCH
H
H
H
H
H
X
L
X
H
L
MATCH
H
H
MATCH
(2)
(2)
Write Inhibit(3)
5632 tbl 18
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70T651/9 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. A17 is a NC for IDT70T659. Address comparison will be for A0 - A16.
5. CEX = L means CE0X = VIL and CE1X = VIH. CEX = H means CE0X = VIH and/or CE1X = VIL.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D35 Left
D0
- D35 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
5632 tbl 19
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T651/9.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O35). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
boxormessagecenter)isassignedtoeachport. Theleftportinterrupt
flag (INTL) is asserted when the right port writes to memory location
3FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
address location 3FFFE when CEL = OEL = VIL, R/W is a "don't care".
Likewise,therightportinterruptflag(INTR)isassertedwhentheleftport
writes to memory location 3FFFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 3FFFF. The
message(36bits)at3FFFEor3FFFF(1FFFFor1FFFEforIDT70T659)
isuser-definedsinceitisanaddressableSRAMlocation.Iftheinterrupt
functionisnotused, addresslocations3FFFEand3FFFFarenotused
FunctionalDescription
TheIDT70T651/9providestwoportswithseparatecontrol,address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70T651/9 has an automatic power down
feature controlled by CE. The CE0 and CE1 control the on-chip power
downcircuitrythatpermitstherespectiveporttogointoastandbymode
when not selected (CE = HIGH). When a port is enabled, access to the
entirememoryarrayispermitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
21
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
asmailboxes,butaspartoftherandomaccessmemory.RefertoTruth
Table III for the interrupt operation.
The BUSY arbitration on a master is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
BusyLogic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
Semaphores
The IDT70T651/9 is an extremely fast Dual-Port 256/128K x 36
CMOS Static RAM with an additional 8 address locations dedicated to
binarysemaphoreflags.Theseflagsalloweitherprocessorontheleftor
rightsideoftheDual-PortRAMtoclaimaprivilegeovertheotherprocessor
for functions defined by the system designer’s software. As an ex-
ample, the semaphore can be used by one processor to inhibit the
other from accessing a portion of the Dual-Port RAM or any other
shared resource.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
and use anyBUSY indication as an interrupt source to flag the event of
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT70T651/9 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
The Dual-Port RAM features a fast access time, with both ports
being completely independent of each other. This means that the
activityontheleftportinnowayslowstheaccesstimeoftherightport.
Both ports are identical in function to standard CMOS Static RAM and
can be read from or written to at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic power-down
featurecontrolledbyCE0andCE1,theDual-PortRAMchipenables,and
SEM, thesemaphoreenable. TheCE0, CE1, andSEM pinscontrolon-
chippowerdowncircuitrythatpermitstherespectiveporttogointostandby
modewhennotselected.
A
18
CE0
CE
0
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSY
R
BUSY
R
BUSY
L
BUSYL
CE1
CE
1
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
Systems which can best use the IDT70T651/9 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70T651/9s
hardware semaphores, which provide a lockout mechanism without
requiringcomplexprogramming.
BUSY
L
BUSY
L
BUSY
R
BUSY
R
.
5632 drw 20
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70T651/9 Dual-Port RAMs.
If these RAMs are being expanded in depth, then theBUSY indication
Softwarehandshakingbetweenprocessorsoffersthemaximumin
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70T651/9 does not use its semaphore
flags to control any resources through hardware, thus allowing the
systemdesignertotalflexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speedsystems.
for the resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/SlaveArrays
When expanding an IDT70T651/9 RAM array in width while using
BUSYlogic, one master part is used to decide which side of the RAMs
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master use the BUSY signal as a write inhibit signal. Thus on the
IDT70T651/9 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignmentmethodcalled“TokenPassingAllocation.”Inthismethod,
the state of a semaphore latch is used as a token indicating that a
shared resource is in use. If the left processor wants to use this
resource,itrequeststhetokenbysettingthelatch.Thisprocessorthen
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicatingBUSYononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
22
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
the gap between the read and write cycles.
verifiesitssuccessinsettingthelatchbyreadingit. Ifitwassuccessful,it
proceeds to assume control over the shared resource. If it was not
successfulinsettingthelatch,itdeterminesthattherightsideprocessor
has set the latch first, has the token and is using the shared resource.
The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquishedthetoken,theleftsideshouldsucceedingainingcontrol.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
sidewritesaonetothatlatch.
The eight semaphore flags reside within the IDT70T651/9 in a
separate memory space from the Dual-Port RAM. This address space
isaccessedbyplacingalowinputonthe SEM pin(whichactsasachip
selectforthesemaphoreflags)andusingtheothercontrolpins(Address,
CE0, CE1,R/W and BEn) as they would be used in accessing a
standardStaticRAM.Eachoftheflagshasauniqueaddresswhichcan
beaccessedbyeithersidethroughaddresspinsA0–A2.Whenaccessing
thesemaphores, noneoftheotheraddresspinshasanyeffect.
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel
is written into an unused semaphore location, that flag will be set to
a zero on that side and a one on the other side (see Truth Table V).
Thatsemaphorecannowonlybemodifiedbythesideshowingthezero.
Whenaoneiswrittenintothesamelocationfromthesameside,the flag
will be set to a one for both sides (unless a semaphore request
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation. The
reason for this is easily understood by looking at the
simplelogicdiagramofthesemaphoreflaginFigure4.Twosemaphore
request latches feed into a semaphore flag. Whichever latch is first to
presentazerotothe semaphoreflagwillforceitssideofthesemaphore
flagLOWandtheothersideHIGH.Thisconditionwillcontinueuntilaone
is written to the same semaphore request latch. If the opposite side
semaphorerequestlatchhasbeenwrittentozerointhemeantime, the
semaphoreflagwillflipovertotheothersideassoonasaoneiswritten
intothefirstrequestlatch.TheoppositesideflagwillnowstayLOWuntil
its semaphore request latch is written to a one. From this it is easy to
L PORT
R PORT
SEMAPHORE
SEMAPHORE
REQUEST FLIP FLOP
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
5632 drw 21
Figure 4. IDT70T651/9 Semaphore Logic
fromtheothersideispending)andthencanbewrittentobybothsides. understand that, if a semaphore is requested and the processor which
The fact that the side which is able to write a zero into a semaphore requesteditnolongerneedstheresource,theentiresystemcanhangup
subsequently locks out writes from the other side is what makes untilaoneiswrittenintothatsemaphorerequestlatch.
semaphoreflagsusefulininterprocessorcommunications.(Athorough
The critical case of semaphore timing is when both sides request
discussionontheuseofthisfeaturefollowsshortly.)Azerowrittenintothe a single token by attempting to write a zero into it at the same time. The
samelocationfromtheothersidewillbestoredinthesemaphorerequest semaphore logic is specially designed to resolve this problem. If
latchforthatsideuntilthesemaphoreisfreedbythefirstside.
simultaneous requests are made, the logic guarantees that only one
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso side receives the token. If one side is earlier than the other in making
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining the request, the first side to make the request will receive the token. If
a zero reads as all zeros for a semaphore read, the SEM, BEn, and OE bothrequestsarriveatthesametime, theassignmentwillbearbitrarily
signalsneedtobeactive. (PleaserefertoTruthTableII). Furthermore, made to one port or the other.
thereadvalueislatchedintooneside’soutputregisterwhenthatside's
One caution that should be noted when using semaphores is that
semaphoreselect(SEM,BEn)andoutputenable(OE)signalsgoactive. semaphores alone do not guarantee that access to a resource is
Thisservestodisallowthesemaphorefromchangingstateinthemiddle secure. As with any powerful programming technique, if semaphores
of a read cycle due to a write cycle from the other side.
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A handled via the initialization program at power-up. Since any sema-
processor requests access to shared resources by attempting to write phore request flag which contains a zero must be reset to a one,
a zero into a semaphore location. If the semaphore is already in use, all semaphores on both sides should have a one written into them
the semaphore request latch will contain a zero, yet the semaphore at initialization from both sides to assure that they will be free
flag will appear as one, a fact which the processor will verify by the when needed.
subsequent read (see Table V). As an example, assume a processor
writes a zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written success-
fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side
during subsequent read. Had a sequence of READ/WRITE been
usedinstead,systemcontentionproblemscouldhaveoccurredduring
23
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
24
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
SleepMode
The IDT70T651/9 is equipped with an optional sleep or low power
modeonbothports.Thesleepmodepinonbothportsisactivehigh.During
operation occurs during these periods, the memory array may be
corrupted. Validity of data out from the RAM cannot be guaranteed
immediatelyafterZZisasserted(priortobeinginsleep).
DuringsleepmodetheRAMautomaticallydeselectsitself.TheRAM
disconnectsitsinternalbuffer.Alloutputswillremaininhigh-Zstatewhile
insleepmode.Allinputsareallowedtotoggle.TheRAMwillnotbeselected
and will not perform any reads or writes.
normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the
port will enter sleep mode where it will meet lowest possible power
conditions.Thesleepmodetimingdiagramshowsthemodesofoperation:
NormalOperation, NoRead/WriteAllowedandSleepMode.
Foraperiodoftime priortosleepmodeandafterrecoveringfromsleep
mode(tZZS andtZZR),newreadsorwritesarenotallowed.Ifawriteorread
JTAGTimingSpecifications
t
JCYC
tJR
tJF
tJCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
tJS
tJH
Device Outputs(2)/
TDO
t
JRSR
tJCD
TRST
x
5632 drw 23
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS, TCK and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4,5)
70T651/9
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
____
____
t
ns
t
40
ns
t
3(1)
ns
____
t
3(1)
ns
____
____
t
50
ns
____
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
____
t
25
ns
____
t
0
ns
____
____
t
15
15
ns
5. JTAG cannot be tested in sleep mode.
t
JTAG Hold
ns
5632 tbl 20
25
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
0x0
Reserved for version number
0x338(1)
0x33
1
IDT Device ID (27:12)
Defines IDT part number 70T651
IDT JEDEC ID (11:1)
Allows unique identification of device vendor as IDT
Indicates the presence of an ID register
ID Register Indicator Bit (Bit 0)
5632 tbl 21
NOTE:
1. Device ID for IDT70T659 is 0x339.
ScanRegisterSizes
Register Name
Bit Size
Instruction (IR)
4
1
Bypass (BYR)
Identification (IDR)
32
Boundary Scan (BSR)
Note (3)
5632 tbl 22
SystemInterfaceParameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
IDCODE
1111
Places the bypass register (BYR) between TDI and TDO.
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
HIGHZ
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
0011
0001
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
RESERVED
Several combinations are reserved. Do not use codes other than those
identified above.
All Other Codes
5632 tbl 23
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, TCK and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
26
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Commercial (0 C to +70 C)
Blank
I
°
°
Industrial (-40 C to +85 C)
°
°
BC
DR
BF
256-ball BGA (BC-256)
208-pin PQFP (DR-208)
208-ball fpBGA (BF-208)
Commercial Only(1)
8
.
Commercial & Industrial(1)
Commercial & Industrial
Commercial Only
10
12
15
peed in nanoseconds
S
S
Standard Power
9Mbit (256K x 36) Asynchronous Dual-Port RAM
4Mbit (128K x 36) Asynchronous Dual-Port RAM
70T651
70T659
5632 drw 24
NOTE:
1. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
DatasheetDocumentHistory:
04/25/03: InitialDatasheet
10/01/03: Page 9 Added 8ns speed DC power numbers to DC Electrical Characteristics Table
Page 9 Updated DC power numbers for 10, 12 & 15ns speeds in the DC Electrical Characteristics Table
Page 9, 11, 15, 17 & 25 Added footnote that indicates that 8ns speed is available in BF-208 and BC-256 packages only
Page 10 Added Capacitance Derating Drawing
Page11, 15&17Added8nsACtimingnumberstotheACElectricalCharacteristicsTables
Page 11 Added tSOE and tLZOB to the AC Read Cycle Electrical Characteristics Table
Page 12 Added tLZOB to the Waveform of Read Cycles Drawing
Page14 AddedtSOE toTimingWaveformofSemaphoreReadafterWriteTiming, EitherSideDrawing
Page 1 & 25 Added 8ns speed grade and 10ns I-temp to features and to ordering information
Page 1, 14 & 15 Added RapidWrite Mode Write Cycle text and waveforms
10/20/03:
04/21/04:
Page 15 Corrected tARF to 1.5V/ns Min.
RemovedPreliminarystatusfromentiredatasheet
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
for Tech Support:
831-754-4613
DualPortHelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
27
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