IDT70T9359L9PFG8 [IDT]
Dual-Port SRAM, 8KX18, 20ns, CMOS, PQFP100, TQFP-100;
| 型号： | IDT70T9359L9PFG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 8KX18, 20ns, CMOS, PQFP100, TQFP-100 静态存储器 |
| 文件： | 总16页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
IDT70T9359/49L
HIGH-SPEED 2.5V 8/4K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
◆
ꢀeatures:
Full synchronous operation on both ports
– 4.0ns setup to clock and 0.5ns hold on all control, data, and
addressinputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timedwriteallowsfastcycletime
– 12ns cycle time, 83MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 2.5V (±100mV) power supply
Industrial temperature range (–40°C to +85°C) is
available for 66MHz
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial:7.5/9/12ns(max.)
– Industrial:9ns (max.)
◆
◆
Low-power operation
◆
– IDT70T9359/49L
Active:225mW(typ.)
◆
◆
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
◆
◆
◆
◆
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin fine pitch Ball Grid Array (fpBGA) packages.
ꢀunctionalBlockDiagram
R/WL
UBL
R/WR
UBR
CE0L
CE1L
CE0R
CE1R
1
0
1
0
0/1
0/1
LBL
LBR
OEL
OER
1b 0b
0a 1a
0b 1b
1a 0a
a
FT/PIPEL
0/1
0/1
b
a
b
FT/PIPER
I/O9L-I/O17L
I/O0L-I/O8L
I/O9R-I/O17R
I/O0R-I/O8R
I/O
Control
I/O
Control
(1)
(1)
A12L
A12R
Counter/
Address
Reg.
Counter/
Address
Reg.
MEMORY
ARRAY
A0R
A0L
CLKL
ADSL
CLKR
ADSR
CNTENR
CNTENL
CNTRSTL
CNTRSTR
5640 drw 01
NOTE:
1. A12 is a NC for IDT70T9349.
JULY 2002
1
©2002 IntegratedDeviceTechnology,Inc.
DSC-5640/1
IDT70T9359/49L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Description:
The IDT70T9359/49 is a high-speed 8/4K x 18 bit synchronous
Withaninputdataregister,theIDT70T9359/49 hasbeenoptimized
forapplicationshavingunidirectionalorbidirectionaldataflowinbursts.An
automaticpowerdownfeature,controlledbyCE0andCE1, permitsthe
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typicallyoperate ononly225mWofpower.
Dual-Port RAM. The memory array utilizes Dual-Port memory cells
to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup
and hold times. The timing latitude provided by this approach allows
systemstobedesignedwithveryshortcycletimes.
Pin Configurations (1,2,3,4)
06/07/02
Index
100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
A8R
75
A9L
2
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A9R
A10R
A11R
A
12R
NC
NC
NC
LBR
UBR
A10L
3
A11L
(1)
4
A12L
(1)
5
NC
NC
NC
LBL
6
7
8
9
UBL
70T9359/49PF
PN100-1(5)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CE0L
CE1L
CNTRSTL
R/WL
OEL
CE
0R
CE
1R
100-Pin TQFP
Top View(6)
CNTRSTR
R/WR
VSS
VDD
OER
FT/PIPEL
I/O17L
I/O16L
VSS
FT/PIPER
I/O17R
VSS
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
.
5640 drw 02
NOTES:
1. A12 is a NC for IDT70T9349.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70T9359/49L
Preliminary
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations (con't.)(1,2,3,4)
70T9359/49BF
BF100(5)
100-PinfpBGA
TopView(6)
06/07/02
A1
A2
A3
A6
A7
A8
A9
A4
A5
A10
A
8R
6R
3R
A
11R UB
R
Vss
Vss I/O13R I/O10R
I/O
CNTRST
R
17R
Vss
B1
B2
B3
B4
B6
B7
B9
B5
B8
B10
(1)
12R
7R
4R
10R
OE
R
FT
R
9R
12R I/O
A
A
A
W
R
PL/
6R
A
R/
I/O
I/O
C1
C5
C6
C2
C3
C4
C7
C8
C9
C10
1R
16R
A
CE
I/O
A
A
5R
1R
A
9R
I/O15R I/O11R I/O7R I/O3R
D1
D2
D6
D9
D3
D5
D7
D8
D10
D4
0R
R
CE0R
5R
0R
1L
A
CLK
LB
R
14R
8R I/O
1R
I/O
A
I/O
I/O
2R
1L
3L
A
E5
ADS
E6
E7
E8
E9
E10
E1
E2
ADSR
E3
E4
L
4R
2R
2L
4L
7L
DD
R
Vss I/O
I/O
I/O
V
Vss
CNTEN
A
F7
F1
F2
F3
F5
F6
F9
F10
F4
F8
DD
DD
V
0L
I/O
L
A
0L
7L
V
Vss
I/O
Vss CLK
I/O
A
G1
G5
G2
G4
H4
G6
G8
G9
G3
G7
G10
L
CNTEN
4L
UB
L
Vss
A
13L
15L
I/O
I/O
Vss
A
NC
I/O3L
,
H7
H8
H9
H10
H3
H5
H6
H1
H2
9L
6L
5L
I/O
I/O
I/O
I/O
11L CE0L
CNTRST
L
I/O
A
2L
6L
9L
A
A
J1
J5
J6
J2
J3
J4
J7
J8
J9
J10
(1)
A
5L
8L
12L
W
R/
L
OE
L
FTL
PL/
I/O
A
A
12L
10L
14L
I/O
Vss
8L
I/O
K6
K8
K10
17L
11L I/O
I/O
K2
K4
CE1L
K5
K7
K9
K1
K3
DD
DD
V
16L I/O
10L
V
I/O
A
LB
L
A
5640 drw 03
NOTES:
1. A12 is a NC for IDT70T9349.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
3
IDT70T9359/49L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
PinNames
Left Port
Right Port
Names
Chip Enables(3)
CE0L, CE1L
CE0R, CE1R
R/WL
R/WR
Read/Write Enable
Output Enable
Address
OEL
OER
(1)
(1)
A0L - A12L
I/O0L - I/O17L
CLKL
A0R - A12R
I/O0R - I/O17R
CLKR
Data Input/Output
Clock
(2)
Upper Byte Select
UBL
UBR
(2)
Lower Byte Select
Address Strobe Enable
Counter Enable
LBL
LBR
ADSL
ADSR
NOTES:
1. A12 is a NC for IDT70T9349.
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CEo and CE1 are single buffered when FT/PIPE = VIL,
CEo and CE1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
CNTENL
CNTRSTL
FT/PIPEL
CNTENR
CNTRSTR
FT/PIPER
Counter Reset
Flow-Through / Pipeline
Power (2.5V)
VDD
Vss
Ground (0V)
5640 tbl 01
Truth Table IRead/Write and Enable Control(1,2,3)
Upper Byte
Lower Byte
(5)
CE1
MODE
(5)
CE0
(4)
(4)
LB
CLK
↑
R/W
X
X
X
L
I/O9-17
I/O0-8
OE
X
X
X
X
X
X
L
UB
H
X
L
L
L
L
L
L
L
L
X
L
X
X
High-Z
High-Z
High-Z
DATAIN
High-Z
DATAIN
DATAOUT
High-Z
DATAOUT
High-Z
High-Z
High-Z
High-Z
High-Z
DATAIN
DATAIN
High-Z
DATAOUT
DATAOUT
High-Z
Deselected–Power Down
Deselected–Power Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
X
H
L
X
H
H
L
↑
H
H
H
H
H
H
H
H
↑
↑
H
L
L
↑
L
L
↑
L
H
L
H
H
H
X
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
↑
L
H
L
↑
L
L
↑
H
X
X
X
Outputs Disabled
5640 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
4. LB and UB are single buffered regardless of state of FT/PIPE.
5. CEo and CE1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.
6.42
4
IDT70T9359/49L
Preliminary
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IIAddress Counter Control(1,2)
Previous
Internal
Address
Internal
Address
Used
External
Address
MODE
CLK
↑
I/O(3)
I/O (n)
I/O(n+1) Counter Enabled—Internal Address generation
I/O(n+1) External Addre ss Blocked—Counter disab led (An + 1 reused)
I/O
D (0) Counter Reset to Address 0
ADS CNTEN CNTRST
(4)
An
X
X
An
An
L
H
H
X
X
H
H
D
External Address Used
(5)
An + 1
An + 1
L
H
X
D
↑
X
An + 1
X
H
D
↑
(4)
0
A
X
L
↑
5640 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
RecommendedDCOperating
Conditions
RecommendedOperating
TemperatureandSupplyVoltage
Symbol
Parameter
Supply Voltage
Ground
Min.
2.4
0
Typ.
Max.
2.6
0
Unit
V
Ambient
Grade
Commercial
Temperature(1)
0OC to +70OC
-40OC to +85OC
GND
0V
VDD
V
DD
2.5
2.5V + 100mV
V
SS
0
V
Industrial
0V
2.5V + 100mV
____
(2)
VIH
VIL
Input High Voltage
Input Low Voltage
1.7
V +0.3V
DD
V
5640 tbl 04
(1)
____
NOTES:
-0.3
0.7
V
1. This is the parameter TA. This is the "instant on" case temperature.
5640 tbl 05
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDD +0.3V.
AbsoluteMaximumRatings(1)
Capacitance(1)
(TA = +25°C, f = 1.0MHZ)
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
VIN = 3dV
Max. Unit
(2)
VTE RM
Terminal Voltage
with Respect to
GND
-0.5 to +3.6
V
CIN
9
pF
(3)
COUT
VOUT = 3dV
10
pF
TBIAS
TSTG
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
5640 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
Storage
Temperature
IOUT
DC Output Current
mA
3. COUT also references CI/O.
5640 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
6.42
5
IDT70T9359/49L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T9359/49L
Symbol
|ILI|
Parameter
Test Conditions
Min.
Max.
5
Unit
µA
µA
V
(1)
___
___
___
Input Leakage Current
Output Leakage Current
Output Low Voltage
VDD = 2.6V, VIN = 0V to VDD
|ILO|
IH
1
IL OUT
o
5
CE = V or CE = V , V = 0V t VDD
VOL
IOL = +2mA
0.4
___
VOH
Output High Voltage
IOH = -2mA
2.0
V
5640 tbl 08
NOTE:
1. At VDD < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(3) (VDD= 2.5V ± 100mV)
70T9359/49L7
Com'l Only
70T9359/49L9
Com'l & Ind
70T9359/49L12
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
175
220
50
Typ.(4)
Max.
Unit
IDD
Dynamic Operating
Current (Both
Ports Active)
mA
L
L
L
L
L
L
80
200
75
75
20
20
47
70
150
CEL and CER= VIL,
Outputs Disabled,
(1)
____
____
____
____
IND
f = fMAX
ISB1
ISB2
Standby Current
(Both Ports - TTL
Level Inputs)
mA
mA
COM'L
IND
20
60
20
40
CEL = CER = VIH
____
(1)
____
____
____
70
f = fMAX
Standby
COM'L
IND
50
115
100
45
85
CE"A" = VIL and
(5)
Current (One
Port - TTL
Level Inputs)
CE"B" = VIH
Active Port Outputs
Disabled, f=fMAX
____
____
____
____
47
0.1
0.1
47
190
3.0
3.0
100
(1)
ISB3
ISB4
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CEL and
CER >VDD - 0.2V,
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(2)
mA
mA
COM'L
IND
L
L
0.1
3.0
0.1
3.0
____
____
____
____
Full Standby
Current (One
Port - CMOS
Level Inputs)
COM'L
IND
L
L
50
115
45
85
CE"A" < 0.2V and
(5)
CE"B" > VDD - 0.2V
VIN > VDD - 0.2V or
____
____
____
____
47
190
VIN < 0.2V, Active Port,
Outputs Disabled, f = fMAX
(1)
5640 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 2.5V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 75mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6.42
6
IDT70T9359/49L
Preliminary
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 2.5V
2ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.25V
1.25V
Figure 1 and 2
5640 tbl 10
50Ω
50Ω
OUT
DATA
1.25V
10pF / 5pF*
(Tester)
5640 drw 04
Figure 1. AC Output Test load.
*
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
∆ tCD
(Typical, ns)
5640 drw 05
∆ Capacitance (pF) from AC Test Load
Figure 2. Typical Output Derating (Lumped Capacitive Load).
6.42
7
IDT70T9359/49L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C)
70T9359/49L7
Com'l Only
70T9359/49L9
Com'l & Ind
70T9359/49L12
Com'l Only
Symbol
tCYC1
Parameter
Min.
22
Max.
Min.
25
15
12
12
6
Max.
Min.
30
20
12
12
8
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
____
____
____
Clock Cycle Time (Flow-Through)
(2)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tCYC2
tCH1
tCL1
tCH2
tCL2
tR
Clock Cycle Time (Pipelined)
12
Clock High Time (Flow-Through)(2)
7.5
7.5
5
(2)
Clock Low Time (Flow-Through)
(2)
Clock High Time (Pipelined)
(2)
Clock Low Time (Pipelined)
5
6
8
____
____
____
Clock Rise Time
3
3
3
____
____
____
tF
Clock Fall Time
3
3
3
____
____
____
tSA
Address Setup Time
Address Hold Time
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tHA
tSC
tHC
tSB
tHB
tSW
tHW
tSD
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
tHD
tSAD
tHAD
tSCN
tHCN
tSRST
tHRST
tOE
ADS Hold Time
____
____
____
____
____
____
____
____
____
____
____
____
CNTEN Setup Time
CNTEN Hold Time
CNTRST Setup Time
CNTRST Hold Time
Output Enable to Data Valid
0
1
1
____
____
____
7.5
9
12
(1)
____
____
____
tOLZ
tOHZ
tCD1
tCD2
tDC
Output Enable to Output Low-Z
2
2
2
(1)
Output Enable to Output High-Z
1
7
1
7
1
7
Clock to Data Valid (Flow-Through)(2)
18
20
25
____
____
____
(2)
____
____
____
Clock to Data Valid (Pipelined)
7.5
9
12
____
____
____
Data Output Hold After Clock High
2
2
2
2
2
2
2
2
2
(1)
tCKHZ
tCKLZ
Clock High to Output High-Z
9
9
9
(1)
____
____
____
Clock High to Output Low-Z
Port-to-Port Delay
tCWDD Write Port Clock High to Read Data Delay
tCCS Clock-to-Clock Setup Time
____
____
____
____
____
____
28
10
35
15
40
15
ns
ns
5640 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both the Left and Right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply
when FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER, and FT/PIPEL.
6.42
8
IDT70T9359/49L
Preliminary
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for ꢀlow-Through Output
(FT/PIPE"X" = VIL)(3,7)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
tSC tHC
CE1
tSB
tHB
tHB
tSB
UB, LB
R/W
tSW tHW
tSA tHA
An
ADDRESS(5)
DATAOUT
An + 1
An + 2
An + 3
tDC
(1)
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2
(1)
(1)
tDC
tCKLZ
tOHZ
(1)
tOLZ
OE (2)
tOE
5640 drw 06
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE"X" = VIH)(3,7)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
(4)
tHC
tHB
tSC tHC
CE1
tSB
(6)
tSB
tHB
UB, LB
R/W
tHW
tHA
tSW
tSA
ADDRESS(5)
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
Qn + 2 (6)
DATAOUT
Qn + 1
(1)
tCKLZ
(1)
(1)
tOHZ
tOLZ
tOE
OE(2)
5640 drw 07
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL, CNTEN and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
7. "X' here denotes Left or Right port. The diagram is with respect to that port.
6.42
9
IDT70T9359/49L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Timing Waveform of a Bank Select Pipelined Read(1,2)
tCYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
tSA tHA
A6
A5
A4
A3
A2
A0
A1
tSC tHC
tSC tHC
(3)
tCD2
tCKHZ
tCD2
(3)
tCD2
Q0
Q3
A5
Q1
DATAOUT(B1)
ADDRESS(B2)
(3)
tDC
tCKLZ
DC
tCKHZ
t
tSA tHA
A0
A6
A4
A3
A2
A1
tSC tHC
CE0(B2)
tSC tHC
(3)
tCD2
(3)
tCKHZ
tCD2
(3)
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
5640 drw 08
Timing Waveform with Port-to-Port ꢀlow-Through Read(4,5,7)
CLK "A"
tSW tHW
R/W "A"
tSA tHA
NO
ADDRESS "A"
DATAIN "A"
CLK "B"
MATCH
MATCH
tSD tHD
VALID
(6)
tCCS
tCD1
R/W "B"
tHW
tHA
tSW
tSA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
(6)
tCD1
tCWDD
VALID
VALID
tDC
tDC
5640 drw 09
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70T9359/49 for this waveform, and are setup for depth expansion in this
example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
6.42
10
IDT70T9359/49L
Preliminary
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
CE1
tSC tHC
tSB
tHB
UB LB
,
tSW tHW
R/W
tSW tHW
(4)
An + 4
An + 3
An
tSA tHA
An +1
An + 2
An + 2
ADDRESS
tSD
tHD
DATAIN
Dn + 2
(1)
(1)
tCKLZ
tCD2
tCD2
(2)
tCKHZ
Qn + 3
Qn
DATAOUT
READ
NOP(5)
WRITE
READ
5640 drw 10
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB, LB
R/W
tSW tHW
tSW tHW
(4)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
tSA tHA
tSD tHD
DATAIN
Dn + 2
(1)
tCD2
tCD2
tCKLZ
(2)
Qn
Qn + 4
DATAOUT
(1)
tOHZ
OE
READ
WRITE
READ
5640 drw 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
11
IDT70T9359/49L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Timing Waveform of ꢀlow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCYC1
tCH1
tCL1
CLK
CE0
CE1
tSC tHC
tSB tHB
,
UB LB
tSW tHW
R/W
tSW tHW
(4)
An + 4
An
An + 3
An +1
An + 2
An + 2
tSD tHD
Dn + 2
ADDRESS
tSA tHA
DATAIN
tCD1
tCD1
tCD1
tCD1
(2)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
(1)
(1)
tDC
tCKLZ
tDC
tCKHZ
NOP(5)
READ
WRITE
5640 drw 12
TimingWaveformof ꢀlow-ThroughRead-to-Write-to-Read(OEControlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC tHC
CE1
tSB
tHB
UB LB
,
tSW tHW
tSW tHW
R/W
(4)
An + 5
An
tSA tHA
An + 4
tOE
An +1
An + 2
An + 3
Dn + 3
ADDRESS
tSD tHD
DATAIN
Dn + 2
tDC
tCD1
tCD1
tCD1
(2)
Qn + 4
tDC
Qn
DATAOUT
(1)
tCKLZ
(1)
tOHZ
OE
READ
WRITE
READ
5640 drw 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
12
IDT70T9359/49L
Preliminary
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD2
Qn + 2(2)
Qn + 3
Qx - 1(2)
Qn + 1
Qn
Qx
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
5640 drw 14
TimingWaveformof ꢀlow-ThroughReadwithAddressCounterAdvance(1)
tCYC1
tCH1
tCL1
CLK
tSA tHA
An
ADDRESS
tSAD tHAD
tSAD tHAD
tSCN tHCN
ADS
CNTEN
tCD1
Qn + 3(2)
Qx(2)
Qn + 4
Qn + 1
Qn + 2
Qn
DATAOUT
tDC
READ
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
WITH
COUNTER
5640 drw 15
NOTES:
1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data
output remains constant for subsequent clocks.
6.42
13
IDT70T9359/49L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Timing Waveform of Write with Address Counter Advance
(ꢀlow-Through or Pipelined Outputs)(1)
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 1
An + 3
An + 4
An + 2
tSAD tHAD
ADS
CNTEN(7)
tSD tHD
Dn
Dn + 4
Dn + 1
Dn + 3
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
5640 drw 16
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
tCYC2
tCH2
tCL2
CLK
tSA tHA
An
ADDRESS(4)
An + 2
An + 1
INTERNAL(3)
ADDRESS
Ax(6)
0
1
An
An + 1
tSW tHW
R/W
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tSRST
tHRST
CNTRST
tSD
tHD
D0
DATAIN
(5)
Qn
Q1
Q0
DATAOUT
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
READ
READ
ADDRESS 1
ADDRESS n ADDRESS n+1
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH.
CE0, UB, LB = VIL; CE1 = VIH.
5640 drw 17
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance.
The ‘An +1’ Address is written to during this cycle.
6.42
14
IDT70T9359/49L
Preliminary
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
ꢀunctionalDescription
The IDT70T9359/49 provides a true synchronous Dual-Port Static
Depth and Width Expansion
TheIDT70T9359/49featuresdualchipenables(refertoTruthTable
RAMinterface.Registeredinputsprovideminimalset-upandholdtimes I)inordertofacilitaterapidandsimpledepthexpansionwithnorequire-
onaddress,data,andallcriticalcontrolinputs.Allinternalregistersare mentsforexternallogic.Figure4illustrateshowtocontrolthevarioiuschip
clocked on the rising edge of the clock signal, however, the self-timed enables in order to expand two devices in depth.
internalwritepulseisindependentoftheLOWtoHIGHtransitionoftheclock
signal.
The IDT70T9359/49 can also be used in applications requiring
expandedwidth,asindicatedinFigure4.Sincethebanksareallocated
An asynchronous output enable is provided to ease asynchronous atthediscretionoftheuser,theexternalcontrollercanbesetuptodrive
bus interfacing. Counter enable inputs are also provided to stall the theinputsignalsforthevariousdevicesasrequiredtoallowfor36-bitor
operationoftheaddresscountersforfastinterleavedmemoryapplications. widerapplications.
CE0 = VIL and CE1 = VIH for one clock cycle will power down the
internalcircuitrytoreducestaticpowerconsumption.Multiplechipenables
alloweasierbankingofmultiple IDT70T9359/49's fordepthexpansion
configurations.WhenthePipelinedoutputmodeisenabled,twocyclesare
required with CE0 = VIL and CE1 = VIH to re-activate the outputs.
(1)
A13/A12
IDT70T9359/49
Control Inputs
IDT70T9359/49
Control Inputs
CE
0
CE
0
CE
1
CE
1
V
DD
V
DD
IDT70T9359/49
Control Inputs
IDT70T9359/49
Control Inputs
CE
1
CE
1
CE
0
CE
0
CNTRST
CLK
ADS
CNTEN
R/W
5640 drw 18
LB, UB
OE
Figure 4. Depth and Width Expansion with IDT70T9359/49
NOTE:
1. A13 is for IDT70T9359, A12 is for IDT70T9349.
6.42
15
IDT70T9359/49L
Preliminary
Industrial and Commercial Temperature Ranges
High-Speed 2.5V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
OrderingInformation
IDT XXXXX
A
99
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Commercial (0
°
C to +70
°C)
Blank
I(1)
Industrial (-40 C to +85
°
°
C)
PF
BF
100-pin TQFP (PN100-1)
100-pin fpBGA (BF100)
7
9
12
Commercial Only
Commercial & Industrial
Commercial Only
Speed in nanoseconds
L
Low Power
70T9359 144K (8K x 18) 2.5V Synchronous Dual-Port RAM
70T9349 72K (4K x 18) 2.5V Synchronous Dual-Port RAM
5640 drw 19
NOTE:
1. Contact your local sales office for Industrial temp range for other speeds, packages and powers.
DatasheetDocumentHistory
07/08/02:
InitialPublicRelease
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
831-754-4613
DualPortHelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
16
相关型号：
IDT70V05L15J8
Dual-Port SRAM, 8KX8, 15ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68
IDT
IDT70V05L15JG8
Dual-Port SRAM, 8KX8, 15ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68
IDT
©2020 ICPDF网 联系我们和版权申明