IDT70V05L35J8 [IDT]
Dual-Port SRAM, 8KX8, 35ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68;
| 型号： | IDT70V05L35J8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 8KX8, 35ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68 静态存储器 内存集成电路 |
| 文件： | 总22页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT70V05S/L
HIGH-SPEED 3.3V
8K x 8 DUAL-PORT
STATIC RAM
Features
◆
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
◆
◆
–
–
Commercial: 15/20/25/35/55ns (max.)
Industrial:20/25/35/55ns(max.)
◆
◆
◆
◆
Low-power operation
–
IDT70V05S
Active:400mW(typ.)
Standby: 3.3mW (typ.)
IDT70V05L
◆
◆
◆
◆
–
Active:380mW(typ.)
Standby: 660µW (typ.)
IDT70V05 easily expands data bus width to 16 bits or more
◆
Functional Block Diagram
OER
CER
OEL
CEL
R/W
R/W
R
L
I/O0L- I/O7L
I/O0R-I/O7R
I/O
Control
I/O
Control
(1,2)
(1,2)
BUSYL
BUSYR
A12L
A0L
A12R
A0R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
13
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CEL
OEL
CER
OER
R/WR
R/WL
SEM
INTL
L
SEM
INTR
R
M/S
(2)
(2)
2941 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
MARCH 2000
1
DSC 2941/6
©2000IntegratedDeviceTechnology,Inc.
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
reads or writes to any location in memory. An automatic power down
featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
FabricatedusingIDT’sCMOShigh-performancetechnology,these
devices typicallyoperate ononly400mWofpower.
The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The
IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port
SRAMorasacombinationMASTER/SLAVEDual-PortSRAMfor16-bit-
or-morewordsystems. UsingtheIDTMASTER/SLAVEDual-PortSRAM
approach in 16-bit or wider memory system applications results in full-
speed,error-freeoperationwithouttheneedforadditionaldiscretelogic.
This device provides two independent ports with separate control,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
The IDT70V05 is packaged in a ceramic 68-pin PGA and PLCC
and a 64-pin thin quad flatpack (TQFP).
Pin Configurations(1,2,3)
INDEX
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
I/O2L
I/O3L 11
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
10
59
58
57
56
55
I/O4L
I/O5L
12
13
GND 14
I/O6L
I/O7L
VCC
15
16
17
IDT70V05J
J68-1(4)
54
53
52
51
50
49
48
47
46
45
44
68-Pin PLCC
Top View(5)
GND 18
I/O0R
I/O1R 20
19
,
I/O2R
VCC
I/O3R
21
22
23
A
0R
A1R
A2R
A3R
A4R
I/O4R 24
I/O5R 25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O6R
2941 drw 02
INDEX
A4L
A3L
1
48
47
46
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
2
3
A
2L
A1L
A0L
INTL
4
5
6
45
44
43
42
41
40
39
38
37
,
70V05PF
PN-64(4)
BUSY
L
7
8
GND
M/S
64-Pin TQFP
Top View(5)
9
GND
I/O0R
I/O1R
I/O2R
VCC
10
11
12
BUSYR
INTR
A0R
13
14
A1R
36
35
34
33
I/O3R
I/O4R
I/O5R
A
2R
NOTES:
15
16
A3R
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
A
4R
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
2941 drw 03
6.42
2
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
51
A5L
52
A6L
54
A8L
56
50
A4L
48
A2L
46
44
42
40
INT
38
A
1R
36
A3R
11
10
09
08
07
S
A0L BUSY M/
L
R
53
A
49
A
3L
47
45
INT
43
GND
41
BUSY
39
A
37
35
A4R
34
A
L
R
A
1L
A
2R
7L
0R
5R
6R
8R
55
A9L
32
33
A
A
7R
57
30
A9R
31
A
A
11L
A10L
58
59
28
A11R
29
A10R
VCC
A12L
60
IDT70V05G
G68-1(4)
61
26
GND
27
A12R
06
05
04
03
02
01
N/C
63
SEM
N/C
68-Pin PGA
Top View(5)
62
24
N/C
25
N/C
L
CE
L
65
OE
64
22
SEM
23
CE
R
R
L
R/WL
67
I/O0L
66
20
OE
21
R/
R
W
R
N/C
1
3
5
GND
7
9
68
11
13
V
15
18
I/O7R
19
N/C
GND
I/O7L
CC
I/O1L
I/O4L
I/O
I/O
I/O
4R
2L
1R
,
2
4
6
8
10
12
14
16
17
I/O
5L
I/O0R I/O2R I/O3R I/O5R I/O6R
VCC
E
I/O6L
I/O3L
A
B
C
D
F
G
H
J
K
L
INDEX
2941 drw 04
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking.
Pin Names
Left Port
Right Port
Names
Chip Enable
CEL
CER
L
R
R/W
R/W
Read/Write Enable
Output Enable
Address
L
R
OE
OE
0L
A
12L
0R
A
12R
- A
- A
0L
7L
0R
7R
I/O - I/O
I/O - I/O
SEMR
INTR
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
SEML
INTL
BUSYL
BUSYR
S
M/
Master or Slave Select
Power
VCC
GND
Ground
2941 tbl 01
6.42
3
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table: Non-Contention Read/Write Control
Inputs(1)
Outputs
R/W
I/O0-7
Mode
CE
H
L
OE
X
X
L
SEM
H
X
L
High-Z
DATAIN
DATAOUT
High-Z
Deselected: Power-Down
Write to Memory
H
L
H
X
H
Read Memory
X
H
X
Outputs Disabled
2941 tbl 02
NOTE:
1. A0L — A12L≠ A0R — A12R
Truth Table II: Semaphore Read/Write Control(1)
Inputs(1)
Outputs
R/W
I/O0-7
Mode
CE
H
OE
L
SEM
L
H
↑
DATAOUT
Read Data in Semaphore Flag
Write I/O0 into Semaphore Flag
Not Allowed
H
X
L
DATAIN
____
L
X
X
L
2941 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from I/O0 -I/O7. These eight semaphores are addressed by A0-A2.
6.42
4
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AbsoluteMaximumRatings(1)
MaximumOperatingTemperature
andSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
Ambient
Temperature
GND
Vcc
(2)
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
Commercial
Industrial
0OC to +70OC
0V
0V
+
3.3V 0.3V
-40OC to +85OC
3.3V 0.3V
Temperature
Under Bias
-55 to +125
-55 to +125
50
oC
oC
+
TBIAS
TSTG
IOUT
2941 tbl 05
NOTE:
Storage
Temperature
1. This is the parameter TA.
DC Output
Current
mA
2941 tbl 04
NOTES:
RecommendedDCOperating
Conditions
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
VCC
Supply Voltage
3.0
3.3
3.6
GND Ground
0
0
0
V
VCC+0.3(2)
0.8
V
____
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
-0.5(1)
V
____
Capacitance(TA = +25°C, f = 1.0MHz)
2941 tbl 06
NOTES:
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
1. VIL> -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VCC +0.3V.
CIN
9
pF
COUT
10
pF
2941 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitznce when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V05S
70V05L
Min.
Symbol
|ILI|
Parameter
Test Conditions
VCC = 3.6V, VIN = 0V to VCC
VOUT = 0V to VCC
Min.
Max.
10
Max.
5
Unit
µA
µA
V
(1)
___
___
___
___
Input Leakage Current
___
___
|ILO|
Output Leakage Current
Output Low Voltage
Output High Voltage
10
5
VOL
IOL = +4mA
0.4
0.4
___
___
VOH
IOH = -4mA
2.4
2.4
V
2941 tbl 08
NOTE:
1. At VCC < 2.0V input leakages are undefined.
6.42
5
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 3.3V ± 0.3V)
70V05X15
Com'l Only
70V05X20
Com'l
& Ind
70V05X25
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
S
L
150
140
215
185
140
130
200
175
130
125
190
165
mA
CE = VIL, Outputs Open
SEM = VIH
(3)
f = fMAX
____
____
____
____
IND
S
L
140
130
225
195
130
125
210
180
mA
mA
mA
mA
mA
mA
mA
mA
mA
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
25
20
35
30
20
15
30
25
16
13
30
25
CER = CEL = VIH
SEMR = SEML = VIH
(3)
f = fMAX
____
____
____
____
S
L
20
15
45
40
16
13
45
40
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
85
80
120
110
80
75
110
100
75
72
110
95
CEL or CER = VIH
Active Port Outputs Open,
(3)
f=fMAX
____
____
____
____
S
L
80
75
130
115
75
72
125
110
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V,
COM'L
IND
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
VIN > VCC - 0.2V or
____
____
____
____
VIN < 0.2V, f = 0(4)
S
L
1.0
0.2
15
5
1.0
0.2
15
5
SEMR = SEML > VCC - 0.2V
Full Standby Current
(One Port -
CMOS Level Inputs)
One Port CEL or
COM'L
IND
S
L
85
80
125
105
80
75
115
100
75
70
105
90
CER > VCC - 0.2V
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Open,
____
____
____
____
S
L
80
75
130
115
75
70
120
105
(3)
f = fMAX
2941 tbl 09a
70V05X35
Com'l
& Ind
70V05X55
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating
Current
COM'L
S
120
115
180
155
120
115
180
155
mA
CE = VIL, Outputs Open
SEM = VIH
L
(3)
(Both Ports Active)
f = fMAX
IND
S
L
120
115
200
170
120
115
200
170
mA
mA
mA
mA
mA
mA
mA
mA
mA
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
13
11
25
20
13
11
25
20
CER = CEL = VIH
SEMR = SEML = VIH
(3)
f = fMAX
S
L
13
11
40
35
13
11
40
35
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
70
65
100
90
70
65
100
90
CEL or CER = VIH
Active Port Outputs Open,
(3)
f=fMAX
S
L
70
65
120
105
70
65
120
105
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
COM'L
IND
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
S
L
1.0
0.2
15
5
1.0
0.2
15
5
=
SEML > VCC - 0.2V
SEMR
Full Standby Current
(One Port -
CMOS Level Inputs)
One Port L or
CE
COM'L
IND
S
L
65
60
100
85
65
60
100
85
CER > VCC - 0.2V
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Open,
S
L
65
60
115
100
65
60
115
100
(3)
f = fMAX
2941 tbl 09b
NOTES:
1. “X” in part number indicates power rating (S or L)
2. VCC = 3.3V, TA = +25°C.
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
6.42
6
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
3.3V
3.3V
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
1.5V
590Ω
590Ω
Input Rise/Fall Times
DATAOUT
BUSY
INT
DATAOUT
Input Timing Reference Levels
Output Reference Levels
Output Load
5pF*
435Ω
30pF
435Ω
1.5V
Figures 1 and 2
2941 drw 05
2941 tbl 10
Figure 2. Output Test Load
*Including scope and jig.
(For tLZ, tHZ, tWZ, tOW)
Figure 1. AC Output Test Load
Timing of Power-Up Power-Down
CE
tPU
tPD
ICC
ISB
50%
50%
,
2941 drw 06
6.42
7
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
70V05X15
Com'l Only
70V05X20
Com'l
& Ind
70V05X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
tRC
Read Cycle Time
15
20
25
ns
ns
ns
____
____
____
tAA
tACE
Address Access Time
15
15
20
20
25
25
Chip Enable Access Time(3)
____
____
____
____
____
____
Output Enable Access Time(3)
Output Hold from Address Change
Output Low-Z Time(1,2)
tAOE
tOH
tLZ
10
12
13
ns
ns
ns
ns
ns
ns
ns
____
____
____
3
3
3
____
____
____
3
3
3
____
____
____
Output High-Z Time(1,2)
tHZ
10
12
15
____
____
____
Chip Enable to Power Up Time(1,2)
tPU
tPD
tSOP
tSAA
0
0
0
____
____
____
Chip Disable to Power Down Time(1,2)
15
20
25
____
____
____
Semaphore Flag Update Pulse (OE or SEM)
10
10
10
____
____
____
Semaphore Address Access(3)
15
20
25
ns
2941 tbl 11a
70V05X35
Com'l
& Ind
70V05X55
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
tRC
Read Cycle Time
35
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
tAA
tACE
tAOE
tOH
tLZ
Address Access Time
35
35
55
55
Chip Enable Access Time(3)
Output Enable Access Time(3)
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
20
30
____
____
3
3
____
____
3
3
Output High-Z Time(1,2)
15
25
____
____
tHZ
tPU
tPD
tSOP
tSAA
Chip Enable to Power Up Time(1,2)
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access(3)
0
0
____
____
____
____
35
50
____
____
15
15
____
____
35
55
ns
2941 tbl 11b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization but is not production tested.
3. To access SRAM, CE = VIL, SEM = VIH.
4. 'X' in part number indicates power rating (S or L).
6.42
8
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
tAA
(4)
tACE
CE
(4)
tAOE
OE
R/W
(1)
tOH
tLZ
VALID DATA(4)
DATAOUT
(2)
tHZ
BUSY
OUT
(3,4)
2941 drw 07
tBDD
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.42
9
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
70V05X15
Com'l Only
70V05X20
Com'l
& Ind
70V05X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time
15
12
12
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
tWP
12
0
15
0
20
0
tWR
tDW
tHZ
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
10
15
15
____
____
____
10
12
15
____
____
____
tDH
0
0
0
(1,2)
____
____
____
tWZ
tOW
tSWRD
tSPS
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
12
15
____
____
____
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
ns
2941 tbl 12a
70V05X35
Com'l
& Ind
70V05X55
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time
35
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
tWP
25
0
40
0
tWR
tDW
tHZ
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
15
30
____
____
15
25
____
____
tDH
0
0
(1,2)
____
____
tWZ
tOW
tSWRD
tSPS
Write Enable to Output in High-Z
15
25
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
0
5
5
0
5
5
____
____
____
____
____
____
ns
2941 tbl 12b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization but is not production tested.
3. To access SRAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. “X” in part number indicates power rating (S or L).
6.42
10
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,3,5,8)
tWC
ADDRESS
(7)
tHZ
OE
tAW
(9)
or
CE
SEM
(3)
(2)
(6)
tWR
tAS
tWP
R/W
(7)
tWZ
tOW
(4)
(4)
DATAOUT
DATAIN
tDW
tDH
2941 drw 08
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,3,5,8)
tWC
ADDRESS
tAW
CE or SEM(9)
(6)
(2)
(3)
tWR
tAS
tEW
R/
W
tDW
tDH
DATAIN
2941 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE, or R/W.
7. Timing depends on which enable signal is de-asserted first, CE, or R/W.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIN. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.42
11
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
tOH
A0-A2
VALID ADDRESS
VALID ADDRESS
tAW
tEW
tWR
tACE
SEM
tDW
tSOP
OUT
DATA
DATA0
DATAIN VALID
tWP tDH
VALID(2)
tAS
R/W
tSWRD
tAOE
OE
tSOP
Read Cycle
Write Cycle
2941 drw 10
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
2941 drw 11
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.42
12
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6)
70V05X15
Com'l Ony
70V05X20
Com'l
& Ind
70V05X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
____
____
____
____
____
____
____
____
____
____
____
____
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
15
15
15
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
15
17
17
____
____
____
5
5
5
____
____
____
BUSY Disable to Valid Data(3)
18
30
30
Write Hold After BUSY(5)
12
15
17
____
____
____
BUSY TIMING (M/S = VIL)
____
____
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
tWB
0
0
0
ns
ns
tWH
12
15
17
(1)
____
____
____
____
____
____
Write Pulse to Data Delay
30
25
45
35
50
35
ns
Write Data Valid to Read Data Delay(1)
ns
2941 tbl 13a
70V05X35
Com'l
& Ind
70V05X55
Com'l
& Ind
Symbol
BUSY TIMING (M/S = VIH)
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
20
20
20
45
40
40
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
20
35
____
____
5
5
____
____
BUSY Disable to Valid Data(3)
35
40
Write Hold After BUSY(5)
25
25
____
____
BUSY TIMING (M/S = VIL)
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
PORT-TO-PORT DELAY TIMING
tWB
0
0
ns
ns
tWH
25
25
(1)
____
____
____
____
tWDD
tDDD
Write Pulse to Data Delay
60
45
80
65
ns
Write Data Valid to Read Data Delay(1)
ns
2941 tbl 13b
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to “Timing Waveform of Read With BUSY (M/S = VIH)” or “Timing Waveform of Write With Port-
To-Port Delay (M/S = VIL)”.
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' is part number indicates power rating (S or L).
6.42
13
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
TimingWaveformof WritewithPort-to-PortReadwithBUSY(2,4,5)(M/S=VIH)
tWC
MATCH
ADDR"A"
R/W"A"
tWP
tDW
tDH
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBDA
tBDD
tBAA
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
2941 drw 12
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE) then BUSY is input. For this example, BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the port opposite from Port “A”.
6.42
14
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
tWH
(2)
W"B"
R/
,
2941 drw 13
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on port “B” Blocking R/W“B”, until BUSY“B” goes HIGH.
3. tWB is only for the slave version.
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
ADDRESSES MATCH
and "B"
CE
"A"
(2)
tAPS
CE"B"
tBAC
tBDC
BUSY"B"
2941 drw 14
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDR"B"
ADDRESS "N"
(2)
tAPS
MATCHING ADDRESS "N"
tBAA
tBDA
"B"
BUSY
2941 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
6.42
15
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
70V05X15
Com'l Only
70V05X20
Com'l
& Ind
70V05X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
tAS
Address Set-up Time
0
0
0
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
0
0
0
____
____
____
15
15
20
20
20
20
____
____
____
Interrupt Reset Time
ns
2941 tbl 14a
70V05X35
Com'l
& Ind
70V05X55
Com'l
& Ind
Symbol
INTERRUPT TIMING
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
tAS
Address Set-up Time
0
0
ns
ns
ns
WR
t
Write Recovery Time
Interrupt Set Time
0
0
____
____
tINS
tINR
25
25
40
40
____
____
Interrupt Reset Time
ns
2941 tbl 14b
NOTES:
1. 'X' in part number indicates power rating (S or L).
6.42
16
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
INTERRUPT SET ADDRESS (2)
ADDR"A"
CE"A"
(3)
(4)
tAS
tWR
R/W"A"
INT"B"
(3)
tINS
2941 drw 16
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
(3)
tAS
CE"B"
"B"
OE
(3)
tINR
INT"B"
2941 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.42
17
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table III Interrupt Flag(1)
Left Port
Right Port
R/WL
L
L
L
A12L-A0L
1FFF
X
L
R/WR
X
R
R
A12R-A0R
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
CE
OE
INT
CE
OE
INT
R
(2)
L
X
X
L
X
X
X
L
X
X
L
L
X
X
L
L
(3)
X
X
X
1FFF
1FFE
X
H
(3)
X
X
L
L
X
X
X
X
(2)
X
1FFE
H
X
Reset Left INTL Flag
2941tbl 15
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
Truth Table IV Address BUSY
Arbitration
Inputs
Outputs
A12L-A0L
A12R-A0R
(1)
(1)
Function
Normal
Normal
Normal
CEL CER
BUSYL
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
MATCH
(2)
(2)
Write Inhibit(3)
2941 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V05 are push
pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. VIL if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be low simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving low regardless of actual logic level on the pin.
Truth Table V Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D7 Left
D0 - D7 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2941 tbl 17
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V05.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
6.42
18
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
CE
(R)
CE
MASTER
Dual Port
SRAM
SLAVE
Dual Port
SRAM
(L)
(L)
(R)
BUSY
BUSY
BUSY
BUSY
MASTER
Dual Port
SRAM
SLAVE
Dual Port
SRAM
CE
CE
(L)
BUSY (R)
BUSY (R)
(L)
BUSY
BUSY
BUSY (R)
(L)
BUSY
2941 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V05 SRAMs.
Functional Description
The IDT70V05 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V05 has an automatic power down
featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry
that permits the respective port to go into a standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
The BUSY outputs on the IDT 70V05 SRAM in master mode, are
push-pull type outputs and do not require pull up resistors to
operate. If these SRAMs are being expanded in depth, then the
BUSY indication for the resulting array requires the use of an external
AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
Interrupts
When expanding an IDT70V05 SRAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT70V05 SRAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicatingBUSYononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)is assignedtoeachport. Theleftportinterrupt
flag (INTL) is set when the right port writes to memory location 1FFE
(HEX). The left port clears the interrupt by reading address location
1FFE. Likewise, the right port interrupt flag (INTR) is set when the left
port writes to memory location 1FFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 1FFF. The
message (8 bits) at 1FFE or 1FFF is user-defined. If the interrupt
function is not used, address locations 1FFE and 1FFF are not used
as mail boxes, but as part of the random access memory. Refer to
Truth Table III for the interrupt operation.
Busy Logic
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “busy”. The BUSY pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
Semaphores
The IDT70V05 is a fast Dual-Port 8K x 8 CMOS Static RAM with
The use of BUSY logic is not required or desirable for all applica-
tions. Insome cases itmaybe usefultologicallyORthe BUSYoutputs
togetheranduseanyBUSYindicationasaninterruptsourcetoflagthe anadditional8addresslocationsdedicatedtobinarysemaphoreflags.
event of an illegal or illogical operation. If the write inhibit function of These flags allow either processor on the left or right side of the Dual-
BUSYlogicis notdesirable,the BUSYlogiccanbedisabledbyplacing Port SRAM to claim a privilege over the other processor for functions
the part in slave mode with the M/S pin. Once in slave mode the BUSY defined by the system designer’s software. As an example, the
pinoperates solelyas awriteinhibitinputpin.Normaloperationcanbe semaphore can be used by one processor to inhibit the other from
programmed by tying the BUSY pins HIGH. If desired, unintended accessing a portion of the Dual-Port SRAM or any other shared
write operations can be prevented to a port by tying the BUSY pin for resource.
thatportLOW.
TheDual-PortSRAMfeaturesafastaccesstime,andbothportsare
6.42
19
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
completelyindependentofeachother.Thismeansthattheactivityonthe beaccessedbyeithersidethroughaddresspinsA0–A2.Whenaccessing
leftportinnowayslows theaccess timeoftherightport.Bothports are thesemaphores,noneoftheotheraddresspinshasanyeffect.
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel
oraccessed,atthesametimewiththeonlypossibleconflictarisingfrom iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
thesimultaneouswritingof,orasimultaneousREAD/WRITEof,anon- on that side and a one on the other side (see Truth Table V). That
semaphorelocation. Semaphoresareprotectedagainstsuchambiguous semaphorecannowonlybemodifiedbythesideshowingthezero.When
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
in the non-semaphore portion of the Dual-Port SRAM. These devices settoaoneforbothsides(unlessasemaphorerequestfromtheotherside
haveanautomaticpower-downfeaturecontrolledbyCE,theDual-Port ispending)andthencanbewrittentobybothsides. Thefactthattheside
SRAMenable,andSEM,thesemaphoreenable.TheCEandSEMpins whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites
controlon-chippowerdowncircuitrythatpermitstherespectiveporttogo fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
intostandbymodewhennotselected. Thisistheconditionwhichisshown communications.(Athoroughdiscussionontheuseofthisfeaturefollows
in Truth Table II where CE and SEM are both HIGH.
shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe
SystemswhichcanbestusetheIDT70V05containmultipleprocessors storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis
or controllers and are typically very high-speed systems which are freedbythefirstside.
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
a performance increase offered by the IDT70V05's hardware sema- thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
phores,whichprovidealockoutmechanismwithoutrequiringcomplex azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
programming.
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
Softwarehandshakingbetweenprocessors offers themaximumin signalsgoactive.Thisservestodisallowthesemaphorefromchanging
system flexibility by permitting shared resources to be allocated in stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
varying configurations. The IDT70V05 does not use its semaphore Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
flags to control any resources through hardware, thus allowing the cause either signal (SEM or OE) to go inactive or the output will never
system designer total flexibility in system architecture.
change.
A sequence WRITE/READ must be used by the semaphore in
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred order to guarantee that no system level contention will occur. A
in either processor. This can prove to be a major advantage in very processor requests access to shared resources by attempting to write
high-speed systems.
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Truth Table V). As an example, assume a
processorwritesazerototheleftportatafreesemaphorelocation.On
asubsequentread,theprocessorwillverifythatithas writtensuccess-
fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
factthataonewillbereadfromthatsemaphoreontherightsideduring
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
secondside’s flagwillnowstayLOWuntilits semaphore requestlatch
is written to a one. From this it is easy to understand that, if a
semaphoreisrequestedandtheprocessorwhichrequesteditnolonger
needstheresource,theentiresystemcanhangupuntilaoneiswritten
intothatsemaphorerequestlatch.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dentofthe Dual-PortSRAM. These latches canbe usedtopass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignmentmethodcalled“TokenPassingAllocation.”Inthis method,
thestateofasemaphorelatchisusedasatokenindicatingthatshared
resource is in use. If the left processor wants to use this resource, it
requests the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
Thesemaphoreflagsareactivelow.Atokenisrequestedbywriting
a zero into a semaphore latch and is released when the same side
writes a one to that latch.
The eight semaphore flags reside within the IDT70V05 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOWinput on the SEM pin (which acts
as a chip select for the semaphore flags) and using the other control
pins (Address, OE, and R/W) as they would be used in accessing a
standardStaticRAM.Eachoftheflagshasauniqueaddresswhichcan
6.42
20
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
The criticalcase ofsemaphore timingis whenbothsides requesta theleftside.
single token by attempting to write a zero into it at the same time. The
Once the left side was finished with its task, it would write a one to
semaphore logic is specially designed to resolve this problem. If Semaphore 0 and may then try to gain access to Semaphore 1. If
simultaneous requests are made, the logic guarantees that only one Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo
side receives the token. If one side is earlier than the other in making itssemaphorerequestandperformothertasksuntilitwasabletowrite,then
the request, the first side to make the request will receive the token. If readazerointoSemaphore1.Iftherightprocessorperformsasimilartask
bothrequests arriveatthesametime,theassignmentwillbearbitrarily withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap
made to one port or the other.
4Kblocks ofDual-PortSRAMwitheachother.
One caution that should be noted when using semaphores is that
The blocks do not have to be any particular size and can even be
semaphores alone do not guarantee that access to a resource is variable, depending upon the complexity of the software using the
secure. As with any powerful programming technique, if semaphores semaphore flags. All eight semaphores could be used to divide the
are misused or misinterpreted, a software error can easily happen.
Dual-PortSRAMorothersharedresourcesintoeightparts.Semaphores
Initialization of the semaphores is not automatic and must be canevenbeassigneddifferentmeaningsondifferentsidesratherthan
handled via the initialization program at power-up. Since any sema- being given a common meaning as was shown in the example above.
phore request flag which contains a zero must be reset to a one, all
Semaphores are a useful form of arbitration in systems like disk
semaphores on both sides should have a one written into them at interfaces where the CPU must be locked out of a section of memory
initialization from both sides to assure that they will be free when during a transfer and the I/O device cannot tolerate any wait states.
needed.
With the use of semaphores, once the two devices has determined
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assignedSRAMsegmentsatfullspeed.
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
goinandupdatethedatastructure.Whentheupdateiscompleted,the
data structure blockis released. This allows the interpretingprocessor
to come back and read the complete data structure, thereby guaran-
teeing a consistent data structure.
UsingSemaphoresSomeExamples
Perhaps the simplest application of semaphores is their applica-
tionasresourcemarkersfortheIDT70V05’sDual-PortSRAM.Saythe
8Kx8SRAMwas tobe dividedintotwo4Kx8blocks whichwere tobe
dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
thelowersectionofmemory,andSemaphore1couldbedefinedasthe
indicator for the upper section of memory.
To take a resource, in this example the lower 4K of Dual-Port
SRAM, the processor on the left port could write and then read a
zero in to Semaphore 0. If this task were successfully completed
(a zero was read back rather than a one), the left processor would
assume control of the lower 4K. Meanwhile the right processor was
attempting to gain control of the resource after the left processor, it
would read back a one in response to the zero it had attempted to
write into Semaphore 0. At this point, the software could choose to try
andgaincontrolofthesecond4Ksectionbywriting,thenreadingazero
into Semaphore 1. If it succeeded in gaining control, it would lock out
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
D0
D
D
D0
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
2941 drw 19
Figure 4. IDT70V05 Semaphore Logic
6.42
21
IDT70V05S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0 C to +70 C)
°
°
Industrial (-40 C to +85 C)
°
°
PF
G
J
64-pin TQFP (PN64-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
15
20
25
35
55
Commercial Only
,
Commercial & Industrial
Commercial & Industrial
Commercial & Industrial
Commercial & Industrial
Speed in nanoseconds
S
L
Standard Power
Low Power
64K (8K x 8) 3.3V Dual-Port RAM
70V05
2941 drw 20
Datasheet Document History
3/11/99:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 and 3 Added additional notes to pin configurations
Changeddrawingformat
6/9/99:
11/10/99:
3/10/00:
Replaced IDT logo
Added 15 & 20ns speed grades
UpgradedDCparameters
AddedIndustrialTemperatureinformation
Changed±200mVto0mVinnotes
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Dual-Port SRAM, 8KX8, 55ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68
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IDT70V05L55JG8
Dual-Port SRAM, 8KX8, 55ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68
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