IDT70V07L [IDT]
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM; 高速3.3V 32K ×8双端口静态RAM
| 型号： | IDT70V07L |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM |
| 文件： | 总18页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT70V07S/L
HIGH-SPEED 3.3V
32K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Commercial: 25/35/55ns (max.)
• Low-power operation
• LVTTL-compatible, single 3.3V (±0.3V) power supply
• Available in 68-pin PGA, 68-pin PLCC, and a 64-pin
TQFP
— IDT70V07S
Active: 450mW (typ.)
Standby: 5mW (typ.)
— IDT70V07L
DESCRIPTION:
Active: 450mW (typ.)
Standby: 5mW (typ.)
The IDT70V07 is a high-speed 32K x 8 Dual-Port Static
RAM. The IDT70V07 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 16-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
• IDT70V07 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• Busy and Interrupt Flags
FUNCTIONAL BLOCK DIAGRAM
OER
OEL
CER
CEL
R/WR
R/W
L
I/O0L- I/O7L
I/O0R-I/O7R
(1,2)
I/O
Control
I/O
Control
(1,2)
BUSY
L
BUSY
R
A
14R
0R
A
14L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
0L
A
15
15
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
R/W
L
CE
OE
R/W
R
R
L
R
L
SEM
L
SEMR
M/S
INT (2)
L
(2)
INTR
2943 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
COMMERCIAL TEMPERATURE RANGE
OCTOBER 1996
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
©1996 Integrated Device Technology, Inc.
DSC-2943/3
6.37
1
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
This device provides two independent ports with separate
Fabricated using IDT’s CMOS high-performance technol-
control, address, and I/O pins that permit independent, ogy, these devices typically operate on only 450mW of power.
asynchronous access for reads or writes to any location in The IDT70V07 is packaged in a ceramic 68-pin PGA, a 68-
memory. An automatic power down feature controlled by CE pin PLCC, and a 80-pin thin plastic quad flatpack (TQFP).
permits the on-chip circuitry of each port to enter a very low
standby power mode.
PIN CONFIGURATIONS (1,2)
INDEX
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
A
A
A
A
A
A
INT
BUSY
GND
M/S
5L
4L
3L
2L
1L
0L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59
58
57
56
55
IDT70V07
J68-1
54
53
52
51
50
49
48
47
46
45
44
L
VCC
L
GND
I/O0R
I/O1R
I/O2R
PLCC
TOP
(3)
VIEW
BUSY
INT
R
R
VCC
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
1R
2R
3R
4R
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2943 drw 02
INDEX
N/C
I/O2L
N/C
1
2
3
4
5
6
7
8
60
59
A
A
A
A
A
A
5L
4L
3L
2L
1L
0L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
70V07
INT
L
PN80-1
VCC
BUSY
GND
M/S
BUSY
L
9
N/C
GND
I/O0R
I/O1R
I/O2R
TQFP
TOP
10
11
12
13
14
15
16
17
18
19
20
(3)
R
VIEW
INT
R
A
A
A
A
A
0R
VCC
1R
2R
3R
4R
I/O3R
I/O4R
I/O5R
I/O6R
N/C
N/C
N/C
2943 drw 03
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate the actual part marking.
6.37
2
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONT'D) (1,2)
51
50
48
A
46
A
44
42
M/S
40
38
36
11
10
09
08
07
06
05
04
03
02
01
A
4L
2L
1L
0L
A1R
A
3R
BUSY
L
INT
R
A
5L
53
52
49
47
45
INT
43
41
39
37
35
34
A
4R
L
GND BUSYR
A
7L
9L
A
3L
A
A
0R
A
2R
A
5R
6R
8R
A
6L
55
54
32
33
A
A
7R
A
A
8L
57
A
56
A
30
31
A
A
9R
11L
10L
12L
13L
59
58
A
28
29
A
A
11R
IDT70V07
G68-1
10R
12R
13R
V
CC
61
60
A
26
GND
27
A
68-PIN PGA
TOP VIEW(3)
A
14L
63
62
24
25
A
SEM
L
A14R
CE
L
65
64
22
SEM
23
CER
R
OE
L
R/W
L
67
I/O0L
66
20
OE
21
R/WR
R
N/C
1
3
5
7
9
68
I/O1L
11
13
V
15
18
I/O7R
19
N/C
GND
GND
I/O7L
CC
I/O4L
I/O2L
I/O1R
I/O4R
2
4
6
8
10
12
14
16
17
I/O5L
I/O0R I/O2R I/O3R I/O5R I/O6R
V
CC
I/O6L
I/O3L
K
A
B
C
D
E
F
G
H
J
L
INDEX
2943 drw 04
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left Port
Right Port
CER
Names
Chip Enable
CEL
R/WL
R/WR
Read/Write Enable
Output Enable
Address
OEL
OER
A0L – A14L
I/O0L – I/O7L
SEML
A0R – A14R
I/O0R – I/O7R
SEMR
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
INTL
INTR
BUSYL
BUSYR
M/S
VCC
Master or Slave Select
Power
GND
Ground
2943 tbl 01
6.37
3
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
Inputs(1)
Outputs
CE
R/W
OE
X
SEM
H
I/O0-7
Mode
H
X
L
High-Z
Deselected: Power-Down
Write to Memory
L
X
H
DATAIN
DATAOUT
High-Z
L
X
H
X
L
H
Read Memory
H
X
Outputs Disabled
NOTE:
2943 tbl 02
1. A0L — A14L ≠ A0R — A14R.
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL(1)
Inputs
Outputs
CE
R/W
OE
L
SEM
I/O0-7
Mode
H
H
H
L
L
L
DATAOUT
DATAIN
—
Read Data in Semaphore Flag
Write I/O0 into Semaphore Flag
Not Allowed
X
L
X
X
NOTE:
2943 tbl 03
1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.
ABSOLUTE MAXIMUM RATINGS (1)
RECOMMENDED OPERATING
Symbol
Rating
Commercial Unit
TEMPERATURE AND SUPPLY VOLTAGE
(2)
Ambient
VTERM
Terminal Voltage
with Respect
to GND
–0.5 to +4.6
V
Grade
Temperature
GND
VCC
Commercial
0°C to +70°C
0V
3.3V ± 0.3V
2943 tbl 05
TA
Operating
0 to +70
°C
Temperature
RECOMMENDED DC OPERATING
CONDITIONS (2)
TBIAS
TSTG
IOUT
Temperature
Under Bias
–55 to +125 °C
–55 to +125 °C
Symbol
Parameter
Min. Typ. Max. Unit
Storage
Temperature
VCC
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
3.0
0
3.3
0
3.6
0
V
V
V
V
GND
VIH
DC Output
Current
50
mA
2.0
–0.3(1)
—
—
VCC+0.3
0.8
NOTES:
2943 tbl 04
VIL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2943 tbl 06
conditions above those indicated in the operational sections of this 2. VTERM must not exceed Vcc + 0.3V.
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time
CAPACITANCE(1)
(TA = +25°C, f = 1.0MHz)TQFP ONLY
or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc
+ 0.3V.
Symbol
CIN
Parameter
Conditions(2) Max. Unit
Input Capacitance
VIN = 3dV
9
pF
pF
COUT
Output
VOUT = 3dV
10
Capacitance
NOTES:
2943 tbl 07
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.37
4
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 3.3V ± 0.3V)
IDT70V07S
IDT70V07L
Symbol
Parameter
Input Leakage Current(1)
Test Conditions
Min.
Max.
Min.
Max.
Unit
|ILI|
VCC = 3.6V, VIN = 0V to VCC
—
—
10
—
5
µA
|ILO|
VOL
VOH
Output Leakage Current
Output Low Voltage
Output High Voltage
CE = VIH, VOUT = 0V to VCC
IOL = 4mA
10
0.4
—
—
—
5
µA
—
0.4
—
V
IOH = -4mA
2.4
2.4
V
2943 tbl 08
NOTE:
1. At Vcc ≤ 2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 3.3V ± 0.3V)
70V07X25
70V07X35
70V07X55
Test
Symbol
Parameter
Condition
Version Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
CE = VIL, Outputs Open
SEM = VIH
f = fMAX
COM’L.
COM’L.
COM’L.
S
L
100
100
170
140
90
90
140
120
90
90
140 mA
120
(3)
ISB1
ISB2
Standby Current
(Both Ports — TTL
Level Inputs)
CER = CEL = VIH
S
L
14
12
30
24
12
10
30
24
12
10
30 mA
24
SEMR = SEML = VIH
(3)
f = fMAX
(5)
Standby Current
(One Port — TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Open,
S
L
50
50
95
85
45
45
87
75
45
45
87 mA
75
(3)
f = fMAX
SEMR = SEML = VIH
ISB3
ISB4
Full Standby Current
(Both Ports — All
Both Ports CEL and
CER > VCC - 0.2V
COM’L.
COM’L.
S
L
1.0
0.2
6
3
1.0
0.2
6
3
1.0
0.2
6
3
mA
CMOS Level Inputs)
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
Full Standby Current
(One Port — All
CE"A" < 0.2V and
S
L
60
60
90
80
55
55
85
74
55
55
85 mA
74
CE"B" > VCC - 0.2V(5)
CMOS Level Inputs)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Open
(3)
f = fMAX
NOTES:
2943 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 80mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / tRC, and using “AC Test Conditions”
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.37
5
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
3.3V
3.3V
AC TEST CONDITIONS
590Ω
590Ω
5pF
Input Pulse Levels
GND to 3.0V
DATAOUT
BUSY
INT
DATAOUT
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5ns Max.
1.5V
435Ω
30pF
435Ω
1.5V
Figures 1 and 2
2943 drw 05
2943 drw 06
2943 tbl 10
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
* Including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT70V07X25
IDT70V07X35
IDT70V07X55
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
READ CYCLE
tRC
tAA
Read Cycle Time
25
—
—
—
3
—
25
25
15
—
—
15
—
25
—
35
35
—
—
—
3
—
35
35
20
—
—
20
—
35
—
45
55
—
—
—
3
—
55
55
30
—
—
25
—
50
—
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Enable Access Time(3)
tACE
tAOE
tOH
tLZ
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1, 2)
Output High-Z Time(1, 2)
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
3
3
3
tHZ
—
0
—
0
—
0
tPU
tPD
—
15
—
—
15
—
—
15
—
tSOP
tSAA
ns
NOTES:
2943 tbl 11
1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. "X" in part numbers indicates power rating (S or L).
TIMING OF POWER-UP POWER-DOWN
CE
t
PU
t
PD
I
CC
50%
50%
I
SB
2943 drw 07
6.37
6
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
WAVEFORM OF READ CYCLES(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
t
AOE
R/W
t
OH
(1)
t
LZ
(4)
DATAOUT
VALID DATA
(2)
t
HZ
BUSYOUT
(3, 4)
t
BDD
2943 drw 08
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDDdelayisrequiredonlyincaseswheretheoppositeportiscompletingawriteoperationtothesameaddresslocation. Forsimultaneous readoperations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)
IDT70V07X25
IDT70V07X35
IDT70V07X55
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tWC
tEW
Write Cycle Time
Chip Enable to End-of-Write(3)
25
20
20
0
—
—
—
—
—
—
—
15
—
15
—
—
—
35
30
30
0
—
—
—
—
—
—
—
20
—
20
—
—
—
55
45
45
0
—
—
—
—
—
—
—
25
—
25
—
—
—
ns
ns
tAW
Address Valid to End-of-Write
Address Set-up Time(3)
ns
tAS
ns
tWP
Write Pulse Width
20
0
25
0
40
0
ns
tWR
Write Recovery Time
ns
tDW
Data Valid to End-of-Write
Output High-Z Time(1, 2)
Data Hold Time(4)
Write Enable to Output in High-Z(1, 2)
Output Active from End-of-Write(1, 2, 4)
SEM Flag Write to Read Time
SEM Flag Contention Window
15
—
0
20
—
0
30
—
0
ns
tHZ
ns
tDH
ns
tWZ
—
0
—
0
—
0
ns
tOW
ns
tSWRD
tSPS
NOTES:
5
5
5
ns
5
5
5
ns
2943 tbl 12
1. Transition is measured ±200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. "X" in part numbers indicates power rating (S or L).
6.37
7
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
t
AW
CE or SEM(9)
(3)
(2)
(6)
tWR
tAS
tWP
R/W
DATAOUT
DATAIN
(7)
t
OW
t
WZ
(4)
(4)
t
DW
tDH
2943 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING(1,5)
tWC
ADDRESS
t
AW
CE or SEM(9)
(3)
WR
(6)
AS
(2)
t
t
tEW
R/W
tDW
tDH
DATAIN
2943 drw 10
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 200mV from steady state with the Output
Test Load (Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.37
8
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
t
OH
t
SAA
A0-A2
VALID ADDRESS
VALID ADDRESS
t
WR
t
ACE
t
AW
t
EW
SEM
t
SOP
t
DW
DATAIN
VALID
DATAOUT
I/O0
(2)
VALID
t
AS
t
WP
t
DH
R/W
t
SWRD
tAOE
OE
Write Cycle
Read Cycle
2943 drw 11
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
A
0"A"-A2"A"
MATCH
SIDE(2)
“A”
R/W"A"
SEM"A"
t
SPS
A
0"B"-A2"B"
MATCH
SIDE(2)
“B”
R/W"B"
SEM"B"
2943 drw 12
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/WB or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
6.37
9
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
IDT70V07X25
IDT70V07X35
IDT70V07X55
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S = VIH)
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
—
—
—
—
5
25
25
25
25
—
35
—
—
—
—
—
5
35
35
35
35
—
40
—
—
—
—
—
5
45
45
45
45
—
50
—
ns
ns
ns
ns
ns
ns
ns
—
20
—
25
—
25
BUSY TIMING (M/S = VIL)
tWB
tWH
BUSY Input to Write(4)
Write Hold After BUSY(5)
0
—
—
0
—
—
0
—
—
ns
ns
20
25
25
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
—
—
55
50
—
—
65
60
—
—
85
80
ns
ns
NOTES:
2943 tbl 13
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. "X" in part numbers indicates power rating (S or L).
6.37
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IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (2,4,5)
t
WC
MATCH
ADDR"A"
R/W"A"
tWP
tDH
t
DW
VALID
DATAIN "A"
(1)
t
APS
MATCH
ADDR"B"
tBDA
tBDD
BUSY"B"
t
WDD
DATAOUT "B"
VALID
(3)
tDDD
2943 drw 13
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
TIMING WAVEFORM OF WRITE WITH BUSY
tWP
R/W"A"
(3)
t
WB
BUSY"B"
(1)
tWH
R/W"B"
(2)
2943 drw 14
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes High.
6.37
11
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(1)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
tAPS
CE"B"
tBAC
tBDC
BUSY"B"
2943 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING(1)
ADDRESS "N"
ADDR"A"
ADDR"B"
BUSY"B"
(2)
APS
t
MATCHING ADDRESS "N"
t
BAA
tBDA
2943 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the busy signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
IDT70V07X25
IDT70V07X35
IDT70V07X55
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
INTERRUPT TIMING
tAS
tWR
Address Set-up Time
0
0
—
—
25
30
0
0
—
—
30
35
0
0
—
—
40
45
ns
ns
Write Recovery Time
Interrupt Set Time
tINS
—
—
—
—
—
—
ns
tINR
Interrupt Reset Time
ns
NOTE:
2942 tbl 14
1. "X" in part numbers indicates power rating (S or L).
6.37
12
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
WAVEFORM OF INTERRUPT TIMING(1)
tWC
INTERRUPT SET ADDRESS(2)
tWR
ADDR"A"
CE"A"
(3)
(4)
t
AS
R/W"A"
INT"B"
(3)
t
INS
2943 drw 17
t
RC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
CE"B"
(3)
t
AS
OE"B"
(3)
INR
t
INT"B"
2943 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
TRUTH TABLES
TRUTH TABLE III — INTERRUPT FLAG(1)
Left Port
Right Port
OER A14R-A0R INTR
R/WL
CEL
L
OEL A14L-A0L INTL
R/WR
CER
X
Function
Set Right INTR Flag
L
X
X
X
L
7FFF
X
X
X
L(3)
H(2)
X
X
L
X
L
X
L(2)
H(3)
X
X
X
L
7FFF
7FFE
X
Reset Right INTR Flag
Set Left INTL Flag
X
X
X
X
L
X
X
L
7FFE
X
X
X
Reset Left INTL Flag
NOTES:
2942 tbl 15
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
6.37
13
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE IV —
ADDRESS BUSYARBITRATION
Inputs
Outputs
A0L-A14L
CER A0R-A14R BUSYL
(1)
(1)
CEL
X
BUSYR
Function
Normal
X
X
H
L
NO MATCH
MATCH
H
H
H
H
H
Normal
X
MATCH
H
H
Normal
Write Inhibit(3)
L
MATCH
(2)
(2)
NOTES:
2943 tbl 16
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT7007 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
TRUTH TABLE V — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1,2)
Functions
D0 - D7 Left
D0 - D7 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
NOTES:
2943 tbl 17
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V07.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.
FUNCTIONAL DESCRIPTION
7FFF location 7FFF. The message (8 bits) at 7FFE or 7FFF
The IDT70V07 provides two ports with separate control,
is user-defined since it is an addressable SRAM location. If
addressandI/Opinsthatpermitindependentaccessforreads
the interrupt function is not used, address locations 7FFE and
or writes to any location in memory. The IDT70V07 has an
7FFF are not used as mail boxes, but as part of the random
automatic power down feature controlled by CE. The CE
access memory. Refer to Truth Table for the interrupt
operation.
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports
INTERRUPTS
of the RAM have accessed the same location at the same
If the user chooses to use the interrupt function, a memory
time. It also allows one of the two accesses to proceed and
location(mailboxormessagecenter)isassignedtoeachport.
signalstheothersidethattheRAMis“Busy”. Thebusypincan
Theleftportinterruptflag(INTL)isassertedwhentherightport
thenbeusedtostalltheaccessuntiltheoperationon theother
writes to memory location 7FFE (HEX), where a write is
side is completed. If a write operation has been attempted
defined as CE = R/W = VIL per the Truth Table. The left port
from the side that receives a busy indication, the write signal
clears the interrupt through access of address location 7FFE
is gated internally to prevent the write from proceeding.
when CER = OER = VIL, R/W is a "don't care". Likewise, the
The use of busy logic is not required or desirable for all
right port interrupt flag (INTR) is asserted when the left port
applications. In some cases it may be useful to logically OR
writes to memory location 7FFF (HEX) and to clear the
the busy outputs together and use any busy indication as an
interrupt flag (INTR), the right port must read the memory
6.37
14
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
interrupt source to flag the event of an illegal or illogical CMOS Static RAM with an additional 8 address locations
operation. If the write inhibit function of busy logic is not dedicatedtobinarysemaphoreflags. Theseflagsalloweither
desirable, the busy logic can be disabled by placing the part processorontheleftorrightsideoftheDual-PortRAMtoclaim
in slave mode with the M/Spin. Once in slave mode theBUSY a privilege over the other processor for functions defined by
pin operates solely as a write inhibit input pin. Normal opera- the system designer’s software. As an example, the sema-
tion can be programmed by tying the BUSY pins high. If phore can be used by one processor to inhibit the other from
desired, unintended write operations can be prevented to a accessing a portion of the Dual-Port RAM or any other shared
port by tying the busy pin for that port low.
resource.
The Dual-Port RAM features a fast access time, and both
The busy outputs on the IDT 70V07 RAM in master mode,
are push-pull type outputs and do not require pull up resistors ports are completely independent of each other. This means
to operate. If these RAMs are being expanded in depth, then that the activity on the left port in no way slows the access time
the busy indication for the resulting array requires the use of oftherightport. Bothportsareidenticalinfunctiontostandard
an external AND gate.
CMOS Static RAM and can be read from, or written to, at the
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
anon-semaphorelocation. Semaphoresareprotectedagainst
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IDT70V07 contain mul-
tiple processors or controllers and are typically very high-
speed systems which are software controlled or software
intensive. These systems can benefit from a performance
increase offered by the IDT70V07's hardware semaphores,
which provide a lockout mechanism without requiring com-
plex programming.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an IDT70V07 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
MASTER
Dual Port
RAM
CE
SLAVE
Dual Port
RAM
CE
BUSY
L
BUSY
R
BUSY
L
BUSY
R
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
CE
CE
BUSY
R
BUSY
L
BUSYL
BUSY
R
BUSYR
BUSY
L
2943 drw 19
Software handshaking between processors offers the
maximum in system flexibility by permitting shared resources
to be allocated in varying configurations. The IDT70V07 does
not use its semaphore flags to control any resources through
hardware, thus allowing the system designer total flexibility in
system architecture.
An advantage of using semaphores rather than the more
common methods of hardware arbitration is that wait states
are never incurred in either processor. This can prove to be
a major advantage in very high-speed systems.
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70V07 RAMs.
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT70V07 RAM the busy pin
is an output if the part is used as a master (M/Spin = H), and
the busy pin is an input if the part used as a slave (M/S pin =
L) as shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busyononeothersideofthearray. Thiswouldinhibitthewrite
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enableandaddresssignalsonly.Itignoreswhetheranaccess
is a read or write. In a master/slave array, both address and
chip enable must be valid long enough for a busy flag to be
output from the master before the actual write pulse can be
initiatedwiththeR/Wsignal. Failuretoobservethistimingcan
result in a glitched internal write inhibit signal and corrupted
data in the slave.
HOW THE SEMAPHORE FLAGS WORK
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provideahardwareassistforauseassignmentmethodcalled
“Token Passing Allocation.” In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
overthesharedresource. Ifitwasnotsuccessfulinsettingthe
latch, it determines that the right side processor has set the
latchfirst, hasthetokenandisusingthesharedresource. The
SEMAPHORES
The IDT70V07 is an extremely fast Dual-Port 32K x 8
6.37
15
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
left processor can then either repeatedly request that Had a sequence of READ/WRITE been used instead, system
semaphore’s status or remove its request for that semaphore contention problems could have occurred during the gap
to perform another task and occasionally attempt again to between the read and write cycles.
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
D0
D0
D
D
Q
Q
WRITE
WRITE
The eight semaphore flags reside within the IDT70V07 in
a separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
eithersidethroughaddresspinsA0–A2. Whenaccessingthe
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If
a low level is written into an unused semaphore location, that
flagwillbesettoazeroonthatsideandaoneontheotherside
(see Table III). That semaphore can now only be modified by
thesideshowingthezero. Whenaoneiswrittenintothesame
locationfromthesameside,theflagwillbesettoaoneforboth
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communica-
tions. (Athoroughdiscussingontheuseofthisfeaturefollows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
until the semaphore is freed by the first side.
SEMAPHORE
READ
SEMAPHORE
READ
2943 drw 20
Figure 4. IDT70V07 Semaphore Logic
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a
semaphore flag. Whichever latch is first to present a zero to
the semaphore flag will force its side of the semaphore flag
low and the other side high. This condition will continue until
a one is written to the same semaphore request latch. Should
the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side’s
request latch. The second side’s flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
When a semaphore flag is read, its value is spread into all
data bits so that a flag that is a one reads as a one in all data
bits and a flag containing a zero reads as all zeros. The read
valueislatchedintooneside’soutputregisterwhenthatside's
semaphore select (SEM) and output enable (OE) signals go
active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the
other side. Because of this latch, a repeated read of a
semaphoreinatestloopmustcauseeithersignal(SEMorOE)
to go inactive or the output will never change.
A sequence WRITE/READ must be used by the sema-
phore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
is that semaphores alone do not guarantee that access to a
resource is secure. As with any powerful programming tech-
nique, if semaphores are misused or misinterpreted, a soft-
ware error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES—SOME EXAMPLES
Perhaps the simplest application of semaphores is their
applicationasresourcemarkersfortheIDT70V07’sDual-Port
RAM. Say the 32K x 8 RAM was to be divided into two 16K
6.37
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IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
x 8 blocks which were to be dedicated at any one time to software using the semaphore flags. All eight semaphores
servicing either the left or right port. Semaphore 0 could be could be used to divide the Dual-Port RAM or other shared
usedtoindicatethesidewhichwouldcontrolthelowersection resourcesintoeightparts.Semaphorescanevenbeassigned
of memory, and Semaphore 1 could be defined as the indica- different meanings on different sides rather than being given
tor for the upper section of memory.
a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like
To take a resource, in this example the lower 16K of
Dual-Port RAM, the processor on the left port could write and disk interfaces where the CPU must be locked out of a section
then read a zero in to Semaphore 0. If this task were ofmemoryduringatransferandtheI/Odevicecannottolerate
successfully completed (a zero was read back rather than a any wait states. With the use of semaphores, once the two
one), the left processor would assume control of the lower deviceshasdeterminedwhichmemoryareawas“off-limits”to
16K. Meanwhile the right processor was attempting to gain the CPU, both the CPU and the I/O devices could access their
control of the resource after the left processor, it would read assigned portions of memory continuously without any wait
backaoneinresponsetothezeroithadattemptedtowriteinto states.
Semaphore 0. At this point, the software could choose to try
Semaphores are also useful in applications where no
and gain control of the second 16K section by writing, then memory “WAIT” state is available on one or both sides. Once
reading a zero into Semaphore 1. If it succeeded in gaining a semaphore handshake has been performed, both proces-
control, it would lock out the left side.
sors can access their assigned RAM segments at full speed.
Another application is in the area of complex data struc-
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to tures. In this case, block arbitration is very important. For this
Semaphore 1. If Semaphore 1 was still occupied by the right applicationoneprocessormayberesponsibleforbuildingand
side, the left side could undo its semaphore request and updating a data structure. The other processor then reads
perform other tasks until it was able to write, then read a zero andinterpretsthatdatastructure. Iftheinterpretingprocessor
into Semaphore 1. If the right processor performs a similar reads an incomplete data structure, a major error condition
task with Semaphore 0, this protocol would allow the two may exist. Therefore, some sort of arbitration must be used
processors to swap 16K blocks of Dual-Port RAM with each between the two different processors. The building processor
other.
arbitrates for the block, locks it and then is able to go in and
The blocks do not have to be any particular size and can update the data structure. When the update is completed, the
even be variable, depending upon the complexity of the data structure block is released. This allows the interpreting
processortocomebackandreadthecompletedatastructure,
thereby guaranteeing a consistent data structure.
6.37
17
IDT70V07S/L
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
PF
G
J
80-pin TQFP (PN80-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
25
35
55
Speed in nanoseconds
S
L
Standard Power
Low Power
70V07 256K (32K x 8) 3.3V Dual-Port RAM
2943 drw 21
6.37
18
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