IDT70V08S15PF9 [IDT]
Dual-Port SRAM, 64KX8, 15ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100;
| 型号： | IDT70V08S15PF9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 64KX8, 15ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT70V08S/L
HIGH-SPEED 3.3V
64K x 8 DUAL-PORT
STATIC RAM
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
IDT70V08 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
◆
– Commercial:15/20/25/35ns(max.)
– Industrial:20ns (max.)
Low-power operation
◆
◆
◆
◆
– IDT70V08S
Active: 550mW (typ.)
Standby: 5mW (typ.)
– IDT70V08L
◆
◆
◆
◆
Active: 550mW (typ.)
Standby: 1mW (typ.)
◆
Dual chip enables allow for depth expansion without
external logic
Functional Block Diagram
R/WL
CE0L
CE1L
R/WR
CE0
R
CE1R
OEL
OER
I/O
Control
I/O
Control
0-7L
I/O
0-7R
I/O
(1,2)
L
(1,2)
BUSY
BUSY
R
64Kx8
MEMORY
ARRAY
70V08
15R
A
15L
A
Address
Decoder
Address
Decoder
A
0L
0R
A
A15L
A15R
A0L
CE 0L
CE1L
A0R
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE0R
CE1R
OER
OEL
R/WL
R/WR
SEM
INT
L
L
SEM
R
(2)
(2)
R
INT
M/S(1)
3740 drw 01
NOTES:
1. BUSY is an input as a Slave (M/S-VIL) and an output when it is a Master (M/S-VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
MARCH 2004
1
DSC-3740/6
©2004IntegratedDeviceTechnology,Inc.
IDT70V08S/L
High-Speed 3.3.V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V08is a high-speed64Kx8Dual-PortStaticRAM. The for reads or writes to any location in memory. An automatic power
IDT70V08 is designed to be used as a stand-alone 512K-bit Dual-Port down feature controlled by the chip enables (either CE0 or CE1)
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit- permit the on-chip circuitry of each port to enter a very low standby
or-more word system. Using the IDT MASTER/SLAVE Dual-Port power mode.
RAM approach in 16-bit or wider memory system applications results
in full-speed, error-free operation without the need for additional these devices typically operate on only 550mW of power.
discrete logic. The IDT70V08 is packaged in a 100-pin Thin Quad Flatpack
This device provides two independent ports with separate control, (TQFP).
Fabricated using IDT’s CMOS high-performance technology,
address, and I/O pins that permit independent, asynchronous access
Pin Configurations(1,2,3)
11/26/01
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
NC
NC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
2
3
A7L
A8L
A9L
A
A
A
A
A
A
A
A
A
7R
4
8R
5
9R
6
A10L
A11L
A12L
A13L
A14L
A15L
10R
11R
12R
13R
14R
15R
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
IDT70V08PF
PN100-1
(4
)
NC
NC
Vss
NC
NC
NC
NC
CE0R
CE1R
VDD
100-Pin TQFP
NC
NC
NC
NC
CE0L
CE1L
(5
)
Top View
,
SEM
R/W
OE
L
SEM
R/W
OE
R
L
R
L
R
Vss
NC
NC
Vss
Vss
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3740 drw 02
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
IDT70V08S/L
High-Speed 3.3V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Maximum Operating Temperature
andSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
Ambient
GND
VDD
(2)
Temperature
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
Commercial
Industrial
0OC to +70OC
0V
0V
3.3V
3.3V
+
0.3V
0.3V
-40OC to +85OC
+
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
T
BIAS
3740 tbl 02
NOTES:
TSTG
Storage
Temperature
1. This is the parameter TA. This is the "instant on" case temperature.
DC Output
Current
mA
IOUT
3740 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Capacitance(1) (TA = +25°C, f = 1.0mhz)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max. Unit
CIN
VIN = 3dV
9
pF
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.
COUT
VOUT = 3dV
10
pF
3740 tbl 03
NOTES:
1. This parameter is determined by device characterization but is not produc-
tion tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Pin Names
Left Port
Right Port
Names
Chip Enables
CE0L, CE1L
R/W
OE
CE0R, CE1R
R/W
OE
L
R
Read/Write Enable
Output Enable
Address
Recommended DC Operating
Conditions
L
R
A0L - A15L
A
0R - A15R
Symbol
Parameter
Supply Voltage
Ground
Min.
Typ.
Max.
3.6
0
Unit
V
I/O0L - I/O7L
SEM
INT
BUSY
I/O0R - I/O7R
Data Input/Output
Semaphore Enable
Interrupt Flag
V
DD
SS
IH
IL
NOTES:
3.0
3.3
L
SEM
INT
BUSY
M/S
R
V
0
0
V
L
R
____
V
Input High Voltage
Input Low Voltage
2.0
V
DD+0.3(2)
V
Busy Flag
L
R
V
-0.3(1)
0.8
V
____
Master or Slave Select
Power (3.3V)
3740 tbl 05
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.3V.
VDD
VSS
Ground (0V)
3740 tbl 04
3
IDT70V08S/L
High-Speed 3.3.V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I – Chip Enable(1,2)
CE
1
Mode
CE
CE0
VIL
VIH
Port Selected (TTL Active)
L
< 0.2V
>VCC -0.2V
X
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
VIH
X
VIL
H
(3)
>VCC -0.2V
X
(3)
X
<0.2V
3740 tbl 06
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels; CE is a reference only.
2. 'H' = VIH and 'L' = VIL.
3. CMOS standby requires 'X' to be either < 0.2V or >VCC-0.2V.
Truth Table II – Non-Contention Read/Write Control
Inputs(1)
Outputs
CE(2)
H
OE
X
X
L
SEM
H
R/W
I/O0-7
Mode
X
L
High-Z
DATAIN
DATAOUT
High-Z
Deselected: Power-Down
Write to Memory
Read Memory
L
H
L
H
X
H
X
H
X
Outputs Disabled
3740 tbl 07
NOTES:
1. A0L — A15L ≠ A0R — A15R
2. Refer to Chip Enable Truth Table.
Truth Table III – Semaphore Read/Write Control(1)
Inputs(1)
Outputs
(2)
R/W
H
I/O0-7
Mode
CE
OE
L
SEM
L
H
DATAOUT
Read Semaphore Flag Data Out
Write I/O into Semaphore Flag
Not Allowed
H
L
X
L
DATAIN
0
↑
______
X
X
L
3740 tbl 08
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2.
2. Refer to Chip Enable Truth Table.
4
IDT70V08S/L
High-Speed 3.3V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V08S
70V08L
Max.
Symbol
|ILI
|ILO
Parameter
Test Conditions
Min.
Max.
10
Min.
Unit
µA
µA
V
(1)
___
___
|
Input Leakage Current
Output Leakage Current
Output Low Voltage
V
DD = 3.6V, VIN = 0V to VDD
5
5
CE(2) = VIH, VOUT = 0V to VDD
___
___
___
___
|
10
VOL
IOL = +4mA
0.4
0.4
___
___
VOH
Output High Voltage
IOH = -4mA
2.4
2.4
V
3740 tbl 09
NOTES:
1. At VDD < 2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6) (VDD = 3.3V ± 0.3V)
70V08X15
70V08X20
Com'l & Ind
Typ.(2) Max
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2) Max
Unit
mA
IDD
Dynamic Operating Current
(Both Ports Active)
S
L
170
170
260
225
165
165
255
220
CE = VIL, Outputs Disabled
SEM = VIH
(3)
f = fMAX
____
____
____
____
____
____
IND
S
L
165
280
mA
mA
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
COM'L
IND
S
L
44
44
70
60
39
39
60
50
CE
L
SEM
= CE
R
= VIH
= VIH
R
= SEM
L
(3)
f = fMAX
____
____
____
____
____
____
S
L
39
65
(5)
ISB2
Standby Current
(One Port - TTL Level Inputs)
COM'L
IND
S
L
115
115
160
145
105
105
155
140
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
SEM
____
____
____
____
____
____
S
L
R
= SEML = VIH
105
155
mA
mA
I
SB3
Full Standby Current (Both
Ports - All CMOS Level
Inputs)
Both Ports CE
CE > VDD - 0.2V
IN > VDD - 0.2V or
IN < 0.2V, f = 0(4)
SEM = SEM > VDD - 0.2V
L and
COM'L
IND
S
L
1.0
0.2
6
3
1.0
0.2
6
3
R
V
V
____
____
____
____
____
____
S
L
R
L
0.2
6
ISB4
Full Standby Current
(One Port - All CMOS Level
Inputs)
CE"A" < 0.2V and
COM'L
IND
S
L
115
115
155
140
105
105
150
135
(5)
CE"B" > VDD - 0.2V
SEM = SEM > VDD - 0.2V
R
L
V
IN > VDD - 0.2V or VIN < 0.2V
____
____
____
____
____
____
S
L
Active Port Outputs Disabled
(3)
105
150
f = fMAX
3740 tbl 10a
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 90mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions" of input levels of GND
to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
5
IDT70V08S/L
High-Speed 3.3.V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6) (VDD = 3.3V ± 0.3V)
70V08X25
70V08X35
Com'l Only
Typ.(2) Max
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2) Max
Unit
mA
IDD
Dynamic Operating Current
(Both Ports Active)
S
L
120
120
205
170
110
110
195
160
CE = VIL, Outputs Disabled
SEM = VIH
(3)
f = fMAX
____
____
____
____
____
____
____
____
IND
S
L
mA
mA
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
COM'L
IND
S
L
17
15
45
40
15
13
40
35
CE
L
SEM
= CE
R
= VIH
= VIH
R
= SEM
L
(3)
f = fMAX
____
____
____
____
____
____
____
____
S
L
(5)
ISB2
Standby Current
(One Port - TTL Level Inputs)
COM'L
IND
S
L
60
60
115
100
50
50
105
90
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
SEM
____
____
____
____
____
____
____
____
S
L
R
= SEML = VIH
mA
mA
I
SB3
Full Standby Current (Both
Ports - All CMOS Level
Inputs)
Both Ports CE
CE > VDD - 0.2V
IN > VDD - 0.2V or
IN < 0.2V, f = 0(4)
SEM = SEM > VCC - 0.2V
L and
COM'L
IND
S
L
1.0
0.2
6
3
1.0
0.2
6
3
R
V
V
____
____
____
____
____
____
____
____
S
L
R
L
ISB4
Full Standby Current
(One Port - All CMOS Level
Inputs)
CE"A" < 0.2V and
COM'L
IND
S
L
70
70
110
95
60
60
100
85
(5)
CE"B" > VDD - 0.2V
SEM = SEM > VDD - 0.2V
R
L
V
IN > VDD - 0.2V or VIN < 0.2V
____
____
____
____
____
____
____
____
S
L
Active Port Outputs Disabled
(3)
f = fMAX
3740 tbl 10b
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 90mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions" of input levels of GND
to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
3.3V
3.3V
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
1.5V
590Ω
590Ω
Input Rise/Fall Times
DATAOUT
BUSY
INT
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAOUT
1.5V
30pF
435Ω
5pF
435Ω
Figures 1 and 2
3740 tbl 11
3740 drw 03
3740 drw 04
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
Figure 1. AC Output Load
* Including scope and jig.
6
IDT70V08S/L
High-Speed 3.3V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
70V08X15
Com'l Only
70V08X20
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
Address Access Time
15
15
20
20
Chip Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
t
t
10
12
____
____
t
3
3
____
____
t
3
3
Output High-Z Time(1,2)
12
12
____
____
t
t
Chip Enable to Power Up Time(2,5)
Chip Disable to Power Down Time(2,5)
0
0
____
____
____
____
t
15
20
____
____
t
Semaphore Flag Update Pulse (OE or SEM)
10
10
____
____
t
Semaphore Address Access Time
15
20
ns
3740 tbl 12a
70V08X25
Com'l Only
70V08X35
Com'l Only
Symbol
READ CYCLE
Parameter
Min. Max.
Min. Max.
Unit
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
25
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
Address Access Time
25
25
35
35
Chip Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
t
t
15
20
____
____
t
3
3
____
____
t
3
3
Output High-Z Time(1,2)
15
20
____
____
t
t
Chip Enable to Power Up Time(2,5)
Chip Disable to Power Down Time(2,5)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
0
0
____
____
____
____
t
25
45
____
____
t
15
15
____
____
t
35
45
ns
3740 tbl 12b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
7
IDT70V08S/L
High-Speed 3.3.V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
t
RC
ADDR
(4)
t
t
AA
(4)
CE(6)
OE
ACE
(4)
AOE
t
R/W
(1)
t
OH
(2)
t
LZ
(4)
DATAOUT
VALID DATA
t
HZ
BUSYOUT
(3,4)
BDD
3740 drw 05
t
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer to Chip Enable Truth Table.
Timing of Power-Up Power-Down
CE
tPU
tPD
ICC
50%
50%
ISB
,
3740 drw 06
8
IDT70V08S/L
High-Speed 3.3V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
70V08X20
70V08X15
Com'l
Com'l Only
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
15
12
12
0
20
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
12
0
15
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
10
15
____
____
t
10
10
____
____
t
0
0
(1,2)
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
10
____
____
t
0
5
5
0
5
5
____
____
____
____
t
t
ns
3740 tbl 13a
70V08X25
Com'l Only
70V08X35
Com'l Only
Symbol
WRITE CYCLE
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
25
20
20
0
35
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
20
0
25
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
15
20
____
____
t
15
20
____
____
t
0
0
(1,2)
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
15
20
____
____
t
0
5
5
0
5
5
____
____
____
____
t
t
ns
3740 tbl 13b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
9
IDT70V08S/L
High-Speed 3.3.V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
t
WC
ADDRESS
(7)
t
HZ
OE
t
AW
CE or SEM(9,10)
(3)
(6)
(2)
t
WP
tAS
tWR
R/W
DATAOUT
DATAIN
(7)
t
OW
tWZ
(4)
(4)
t
DH
t
DW
3740 drw 07
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
t
WC
ADDRESS
t
AW
CE or SEM(9,10)
(3)
(6)
(2)
t
WR
tAS
tEW
R/W
tDW
tDH
DATAIN
3740 drw 08
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Chip Enable Truth Table.
10
IDT70V08S/L
High-Speed 3.3V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
t
SAA
A0-A2
VALID ADDRESS
VALID ADDRESS
tAW
tWR
tACE
tEW
SEM
t
OH
tSOP
tDW
OUT
DATA
VALID(2)
I/O
IN
DATA VALID
t
AS
tWP
tDH
R/W
t
SWRD
tAOE
OE
Write Cycle
Read Cycle
3740 drw 09
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).
2. DATAOUT VALID represents I/O0-7 equal to semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
3740 drw 10
NOTES:
1. DOR = DOL = VIL, CEL = CER = VIH (Refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
11
IDT70V08S/L
High-Speed 3.3.V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating TemperatureandSupplyVoltageRange(6)
70V08X15
Com'l Only
70V08X20
Com'l
& Ind
Symbol
BUSY TIMING (M/S=VIH
Parameter
Min.
Max.
Min.
Max. Unit
)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
t
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
15
20
____
____
t
5
5
____
____
BUSY Disable to Valid Data(3)
t
17
35
t
Write Hold After BUSY(5)
12
15
____
____
BUSY TIMING (M/S=VIL
)
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
0
ns
ns
tWH
12
15
PORT-TO-PORT DELAY TIMING
Write Pulse to Data Delay
Write Data Valid to Read Data Delay(1)
(1)
____
____
____
____
t
WDD
30
25
45
30
ns
tDDD
ns
3740 tbl 14a
70V08X25
Com'l Only
70V08X35
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max. Unit
BUSY TIMING (M/S=VIH
)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
25
25
25
35
35
35
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
t
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Access Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
25
35
____
____
t
5
5
____
____
BUSY Disable to Valid Data(3)
t
35
40
t
Write Hold After BUSY(5)
20
25
____
____
BUSY TIMING (M/S=VIL
)
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
0
ns
ns
tWH
20
25
PORT-TO-PORT DELAY TIMING
Write Pulse to Data Delay
Write Data Valid to Read Data Delay(1)
(1)
____
____
____
____
t
WDD
55
50
65
60
ns
tDDD
ns
3740 tbl 14b
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
12
IDT70V08S/L
High-Speed 3.3V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
TimingWaveformof WritewithPort-to-PortReadandBUSY (M/S =VIH)(2,4,5)
tWC
MATCH
ADDR"A"
R/W"A"
tWP
tDW
t
DH
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
3740 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL, refer to Chip Enable Truth Table.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
tWH
(2)
R/W"B"
3740 drw 12
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
13
IDT70V08S/L
High-Speed 3.3.V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing(M/S = VIH)(1,3)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
t
APS
CE"B"
t
BAC
tBDC
BUSY"B"
3740 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(M/S = VIH)(1)
ADDR"A"
ADDRESS "N"
(2)
t
APS
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
3740 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Chip Enable Truth Table.
14
IDT70V08S/L
High-Speed 3.3V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
70V08X20
Com'l
& Ind
70V08X15
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
0
____
____
t
15
25
20
20
____
____
t
Interrupt Reset Time
ns
3740 tbl 15a
70V08X25
Com'l Only
70V08X35
Com'l Only
Symbol
INTERRUPT TIMING
Parameter
Min. Max.
Min.
Max.
Unit
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
0
____
____
t
25
30
30
35
____
____
t
Interrupt Reset Time
ns
3740 tbl 15b
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
15
IDT70V08S/L
High-Speed 3.3.V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1,5)
tWC
INTERRUPT SET ADDRESS(2)
ADDR"A"
(3)
(4)
tAS
tWR
CE"A"
R/W"A"
INT"B"
(3)
t
INS
3740 drw 15
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
tAS
OE"B"
(3)
tINR
INT"B"
3740 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Chip Enable Truth Table.
Truth Tables
Truth Table IV — Interrupt Flag(1,4,5)
Left Port
Right Port
OE
R/W
L
L
A
15L-A0L
R/W
R
A15R-A0R
Function
CE
L
OE
L
INT
L
CE
R
R
INTR
(2)
L
X
X
L
X
X
X
L
FFFF
X
X
X
X
L
X
L
L
X
X
L
X
FFFF
FFFE
X
L
Set Right INT
Reset Right INT
Set Left INT Flag
Reset Left INT Flag
R
Flag
(3)
X
X
H
R
Flag
(3)
X
X
L
X
X
X
L
(2)
X
FFFE
H
X
X
L
3740 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. Refer to Chip Enable Truth Table.
16
IDT70V08S/L
High-Speed 3.3V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table V —
Address BUSY Arbitration(4)
Inputs
Outputs
A
OL-A15L
(1)
(1)
A
OR-A15R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
MATCH
(2)
(2)
(3)
Write Inhibit
3740 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V08 are push-
pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. Refer to Chip Enable Truth Table.
Truth Table VI — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D7
Left
D0
- D7
Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
3740 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V08.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT70V08 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V08 has an automatic power down
feature controlled by CE. The CE0 and CE1 control the on-chip power
down circuitry that permits the respective port to go into a standby
mode when not selected (CE HIGH). When a port is enabled, access
to the entire memory array is permitted.
boxormessagecenter)is assignedtoeachport. Theleftportinterrupt
flag (INTL) is asserted when the right port writes to memory location
FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
address location FFFE when CEL = OEL = VIL, R/W is a "don't care".
Likewise, the right port interrupt flag (INTR) is asserted when the left
port writes to memory location FFFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location FFFF. The
message (8 bits) at FFFE or FFFF is user-defined since it is an
addressable SRAM location. If the interrupt function is not used,
Interrupts
If the user chooses the interrupt function, a memory location (mail
17
IDT70V08S/L
High-Speed 3.3.V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
address locations FFFE and FFFF are not used as mail boxes, but as ofthearrayandanothermasterindicatingBUSYononeothersideofthe
part of the random access memory. Refer to Truth Table IV for the array.Thiswouldinhibitthewriteoperationsfromoneportforpartofaword
interruptoperation.
andinhibitthewriteoperationsfromtheotherportfortheotherpartofthe
word.
The BUSY arbitration on a master is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
RAMhave accessedthe same locationatthe same time. Italsoallows
one of the two accesses to proceed and signals the other side that the
RAMis “Busy”.TheBUSY pincanthenbeusedtostalltheaccess until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the
write signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applica-
tions. Insome cases itmaybe usefultologicallyORthe BUSYoutputs
Semaphores
TheIDT70V08is anextremelyfastDual-Port64Kx8CMOSStatic
togetheranduseanyBUSYindicationasaninterruptsourcetoflagthe RAM with an additional 8 address locations dedicated to binary
event of an illegal or illogical operation. If the write inhibit function of semaphore flags. These flags alloweitherprocessoronthe leftorright
BUSYlogicis notdesirable,the BUSYlogiccanbedisabledbyplacing side ofthe Dual-PortRAMtoclaima privilege overthe otherprocessor
the part in slave mode with the M/S pin. Once in slave mode the BUSY for functions defined by the system designer’s software. As an ex-
pinoperates solelyas awriteinhibitinputpin.Normaloperationcanbe ample, the semaphore can be used by one processor to inhibit the
programmed by tying the BUSY pins HIGH. If desired, unintended other from accessing a portion of the Dual-Port RAM or any other
write operations can be prevented to a port by tying the BUSY pin for shared resource.
The Dual-Port RAM features a fast access time, with both ports
being completely independent of each other. This means that the
A16
activityonthe leftportinnowayslows the access time ofthe rightport.
Both ports are identical in function to standard CMOS Static RAM and
can be read from or written to at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic power-down
feature controlled by CE, the Dual-Port RAM enable, and SEM, the
semaphore enable. The CE and SEM pins control on-chip power
downcircuitrythatpermits the respective porttogointostandbymode
when not selected. This is the condition which is shown in Truth Table
III where CE and SEM are both HIGH.
CE
0
CE0
MASTER
SLAVE
Dual Port RAM
Dual Port RAM
BUSY
R
BUSY
L
BUSY
R
BUSYL
CE1
CE1
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSY
L
BUSYL
BUSY
R
BUSY
R
3740 drw 17
Figure 3. Busy and chip enable routing for both width and depth expansion
with IDT70V08 RAMs.
Systems which can best use the IDT70V08 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70V08s
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Softwarehandshakingbetweenprocessors offers themaximumin
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70V08 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
thatportLOW.
The BUSY outputs on the IDT 70V08 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
Ifthese RAMs are beingexpandedindepth, thentheBUSY indication
for the resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V08 RAM array in width while using
BUSYlogic, one master part is used to decide which side of the RAMs
array will receive aBUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master use the BUSY signal as a write inhibit signal. Thus on the
IDT70V08 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicatingBUSYononeside
18
IDT70V08S/L
High-Speed 3.3V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
read,theprocessorwillverifythatithaswrittensuccessfullytothatlocation
and will assume control over the resource in question. Meanwhile, if a
processorontherightsideattemptstowriteazerotothesamesemaphore
flagitwillfail,aswillbeverifiedbythefactthataonewillbereadfromthat
semaphoreontherightsideduringsubsequentread. Hadasequence
ofREAD/WRITEbeenusedinstead,systemcontentionproblemscould
have occurred during the gap between the read and write cycles.
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation.The
reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
isinuse.Thesemaphoresprovideahardwareassistforauseassignment
methodcalled“TokenPassingAllocation.”Inthismethod,thestateofa
semaphorelatchisusedasatokenindicatingthatasharedresourceis
inuse.Iftheleftprocessorwantstousethisresource,itrequeststhetoken
bysettingthelatch.Thisprocessorthenverifiesitssuccessinsettingthe
latchbyreadingit. Ifitwassuccessful,itproceedstoassumecontrolover
thesharedresource.Ifitwasnotsuccessfulinsettingthelatch,itdetermines
thattherightsideprocessorhassetthelatchfirst, hasthetokenandisusing
thesharedresource.Theleftprocessorcantheneitherrepeatedlyrequest
that semaphore’s status or remove its request for that semaphore to
performanothertaskandoccasionallyattemptagaintogaincontrolofthe
tokenviathesetandtestsequence.Oncetherightsidehasrelinquished
thetoken,theleftsideshouldsucceedingainingcontrol.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
L PORT
R PORT
SEMAPHORE
The eight semaphore flags reside within the IDT70V08 in a
separate memoryspace fromthe Dual-PortRAM. This address space
is accessedbyplacingalowinputonthe SEM pin(whichacts as achip
select for the semaphore flags) and using the other control pins
(Address, CE, and R/W) as they would be used in accessing a
standard Static RAM. Each of the flags has a unique address which
can be accessed by either side through address pins A0 – A2. When
accessing the semaphores, none of the other address pins has any
effect.
SEMAPHORE
REQUEST FLIP FLOP
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
3740 drw 18
Figure 4. IDT70V08 Semaphore Logic
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel
is written into an unused semaphore location, that flag will be set to a sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
zeroonthatside anda one onthe otherside (see TruthTable VI). That semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch
semaphore can now only be modified by the side showing the zero. havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
When a one is written into the same location from the same side, the overtotheothersideassoonasaoneiswrittenintothefirstside’srequest
flag will be set to a one for both sides (unless a semaphore request latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest
fromtheothersideispending)andthencanbewrittentobybothsides. latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
The fact that the side which is able to write a zero into a semaphore is requestedandthe processorwhichrequesteditnolongerneeds the
subsequently locks out writes from the other side is what makes resource, the entire system can hang up until a one is written into that
semaphore flags useful in interprocessor communications. (A thor- semaphorerequestlatch.
ough discussion on the use of this feature follows shortly.) A zero
The critical case of semaphore timing is when both sides request
written into the same location from the other side will be stored in the a single tokenbyattemptingtowrite a zerointoitatthe same time. The
semaphore request latch for that side until the semaphore is freed by semaphore logic is specially designed to resolve this problem. If
the first side.
simultaneous requests are made, the logic guarantees that only one
Whena semaphore flagis read, its value is spreadintoalldata bits side receives the token. If one side is earlier than the other in making
so that a flag that is a one reads as a one in all data bits and a flag the request, the first side to make the request will receive the token. If
containinga zeroreads as allzeros. The readvalue is latchedintoone bothrequests arriveatthesametime,theassignmentwillbearbitrarily
side’s output register when that side's semaphore select (SEM) and made to one port or the other.
output enable (OE) signals go active. This serves to disallow the
One caution that should be noted when using semaphores is that
semaphore from changing state in the middle of a read cycle due to a semaphores alone do not guarantee that access to a resource is
write cycle from the other side. Because of this latch, a repeated read secure. As with any powerful programming technique, if semaphores
of a semaphore in a test loop must cause either signal (SEM or OE) to are misused or misinterpreted, a software error can easily happen.
go inactive or the output will never change.
Initialization of the semaphores is not automatic and must be
A sequence WRITE/READ must be used by the semaphore in handled via the initialization program at power-up. Since any sema-
order to guarantee that no system level contention will occur. A phore request flag which contains a zero must be reset to a one, all
processor requests access to shared resources by attempting to write semaphores on both sides should have a one written into them at
a zero into a semaphore location. If the semaphore is already in use, initialization from both sides to assure that they will be free when
the semaphore request latch will contain a zero, yet the semaphore needed.
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Table VI). As an example, assume a processor
writesazerototheleftportatafreesemaphorelocation.Onasubsequent
19
IDT70V08S/L
High-Speed 3.3.V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
(1)
I
PF
100-pin TQFP (PN100-1)
15
20
25
35
Commercial Only
,
Commercial & Industrial
Speed in nanoseconds
Commercial Only
Commercial Only
S
L
Standard Power
Low Power
70V08 512K (64K x 8) 3.3V Dual-Port RAM
NOTE:
3740 drw 19
1. Industrial temperature range is available. For other speeds, packages and powers contact your sales office.
DatasheetDocumentHistory:
3/15/99:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 Addedadditionalnotestopinconfigurations
Added 15ns speed grade
6/9/99:
Changeddrawingformat
11/10/99:
1/12/01:
Replaced IDT logo
Page 3 Increasedstoragetemperatureparameter
ClarifiedTAparameter
Page 5 DCElectricparameters–changedwordingfromopentodisabled
Page 18 Added IV to Truth Table in first paragraph
Changed±200mVto0mVinnotes
RemovedPreliminarystatus
12/03/01:
03/24/04:
Page 2 Addeddaterevisiontopinconfigurations
Page 2, 3, 5 & 6 Changed naming conventions from Vcc to VDD and from GND to Vss
Page 5 Addedindustrialtempfor20nsspeedtoDCElectricalCharacteristics
Page 7, 9, 12 & 15 Addedindustrialtempto20nsspeedtoACElectricalCharacteristics
Page 20 Addedindustrialtempto20nsandadded3.3Vspecificationtoorderinginformation
Page 1 & 20 Replaced TM logo with ® logo
Page5 CorrectedtheIDD 15ns commerciallowerpowervalueto225mAintheDCElectricalCharacteristics table
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