IDT70V15S20J [IDT]
HIGH-SPEED 3.3V 16/8K X 9 DUAL-PORT STATIC RAM; 高速3.3V 16 / 8K ×9双端口静态RAM
| 型号： | IDT70V15S20J |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 3.3V 16/8K X 9 DUAL-PORT STATIC RAM |
| 文件： | 总18页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 3.3V
16/8K X 9 DUAL-PORT
STATIC RAM
PRELIMINARY
IDT70V16/5S/L
ꢀeatures
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial:15/20/25ns(max.)
– Industrial:20ns (max.)
Low-power operation
– IDT70V16/5S
Active:430mW(typ.)
Standby: 3.3mW (typ.)
– IDT70V16/5L
more using the Master/Slave select when cascading more
than one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flag
On-chip port arbitration logic
◆
◆
◆
◆
◆
◆
Full on-chip hardware support of semaphore signaling
between ports
◆
◆
◆
◆
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (+0.3V) power supply
Available in 68-pin PLCC and an 80-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Active:415mW(typ.)
Standby:660µW(typ.)
IDT70V16/5 easily expands data bus width to 18 bits or
◆
ꢀunctionalBlockDiagram
OEL
CEL
OER
CER
R/WR
R/
WL
I/O0L- I/O8L
I/O0R-I/O8R
I/O
I/O
Control
Control
(2,3)
BUSYL
(2,3)
BUSYR
(1)
(1)
A13L
A13R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A0R
A0L
14
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CEL
OEL
CER
OER
R/
WR
R/WL
SEML
SEMR
INTR
M/S
(3)
(3)
INTL
5669 drw 01
NOTES:
1. A13 is a NC for IDT70V15.
2. In MASTER mode: BUSY is an output and is a push-pull driver
In SLAVE mode: BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
AUGUST 2002
1
DSC 5669/1
©2002 IntegratedDeviceTechnology,Inc.
P
R
E
L
I
M
I
N
A
R
Y
P
R
E
PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Description
reads or writes to any location in memory. An automatic power down
featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
FabricatedusingIDT’sCMOShigh-performancetechnology,these
devices typicallyoperate ononly430mWofpower.
The IDT70V16/5 is a high-speed 16/8K x 9 Dual-Port Static RAM.
TheIDT70V16/5isdesignedtobeusedasstand-aloneDual-PortRAMs
orasacombinationMASTER/SLAVEDual-PortRAMfor18-bit-or-more
wider systems. Using the IDT MASTER/SLAVE Dual-Port RAM ap-
proachin18-bitorwidermemorysystemapplicationsresultsinfull-speed,
error-freeoperationwithouttheneedforadditionaldiscretelogic.
This device provides two independent ports with separate control,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
The IDT70V16/5 is packaged in a 64-pin PLCC (Plastic Leaded
Chip Carriers) and an 80-pinTQFP (Thin Quad Flatpack).
PinConfigurations(1,2,3,4)
08/26/02
INDEX
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O2L
I/O3L
I/O4L
I/O5L
VSS
A5L
A4L
A3L
A2L
A1L
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
6L
I/O
0L
A
IDT70V16/5J
,
INTL
BUSYL
VSS
(5)
J68-1
I/O7L
DD
V
68-Pin PLCC
VSS
I/O0R
(6)
Top View
S
M/
BUSYR
INTR
A0R
A1R
A2R
1R
I/O
I/O2R
VDD
I/O3R
I/O4R
I/O5R
I/O6R
A3R
A4R
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
5669 drw 02
NOTES:
1. A13 is a NC for IDT70V15.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. Package body is approximately .95 in x .95 in x .17 in.
5. This package code is used to reference the package diagram.
6. This text does not imply orientation of Part-marking.
2
6.42
E
L
I
M
I
N
A
R
Y
IDT70V16/5S/L
PRELIMINARY
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinConfigurations(1,2,3,4)(con't.)
08/26/02
INDEX
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC
1
2
NC
I/O2L
I/O3L
I/O4L
I/O5L
A5L
A
4L
3
A3L
A2L
A1L
A0L
4
5
6
VSS
I/O6L
I/O7L
VDD
7
IDT70V16/5PF
INT
L
8
(5)
PN80-1
BUSY
L
9
VSS
10
11
12
13
14
15
16
17
18
19
20
NC
80-Pin TQFP
S
M/
VSS
(6)
Top View
BUSY
R
I/O0R
I/O1R
I/O2R
INT
R
A0R
A1R
A2R
A3R
A4R
NC
VDD
I/O3R
I/O
4R
I/O5R
I/O6R
NC
NC
5669 drw 03
NOTES:
1. A13 is a NC for IDT70V15.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. PN80-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.432
P
R
E
L
I
M
I
N
A
R
Y
P
R
E
PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
PinNames
Left Port
Right Port
Names
CEL
CER
Chip Enable
WL
WR
R/
R/
Read/Write Enable
Output Enable
Address
OEL
0L
OER
(1)
(1)
13L
0R
13R
A
- A
A
- A
0L
8L
0R
8R
I/O - I/O
I/O - I/O
SEMR
INTR
Data Input/Output
Semaphore Enable
Interrupt Flag
SEML
INTL
BUSYL
BUSYR
S
Busy Flag
M/
Master or Slave Select
Power (3.3V)
CC
V
GND
Ground (0V)
5669 tbl 01
NOTE:
1. A13 is a NC for IDT70V15.
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
R/W
I/O0-8
Mode
CE
H
L
OE
X
X
L
SEM
H
X
L
High-Z
DATAIN
DATAOUT
High-Z
Deselcted: Power-Down
Write to Memory
Read Memory
H
L
H
X
H
X
H
X
Outputs Disabled
5669 tbl 02
NOTE:
1. Condition: A0L — A13L ≠ A0R — A13R
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
R/W
H
I/O0-8
Mode
Read Semaphore Flag Data Out (I/O0 - I/O8)
CE
H
OE
L
SEM
L
DATAOUT
IN
DATA
0
H
↑
X
L
Write I/O into Semaphore Flag
____
L
X
X
L
Not Allowed
5669 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0-I/O8). These eight semaphores are addressed by A0 - A2.
4
6.42
E
L
I
M
I
N
A
R
Y
IDT70V16/5S/L
PRELIMINARY
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AbsoluteMaximumRatings(1)
MaximumOperating
TemperatureandSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Unit
V
Grade
Ambient
Temperature
GND
Vcc
(2)
Terminal Voltage
with Respect to GND
-0.5 to +3.6
TERM
V
Commercial
0OC to +70OC
0V
0V
3.3V 0.3V
+
Industrial
-40OC to +85OC
3.3V 0.3V
+
Temperature Under Bias
-55 to +125
oC
(3)
BIAS
T
5669 tbl 05
NOTES:
STG
T
Storage Temperature
Junction Temperature
DC Output Current
-65 to +150
+150
oC
oC
1. This is the parameter TA. This is the "instant on" case temperature.
JN
T
OUT
I
50
mA
5669 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
RecommendedDCOperating
Conditions
Symbol
Parameter
Supply Voltage
Ground
Min.
Typ.
Max.
3.6
0
Unit
V
2. VTERM must not exceed VDD + 0.3V.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
DD
V
3.0
3.3
SS
V
0
0
V
(2)
____
DD
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
V +0.3
V
-0.3(1)
0.8
V
____
5669 tbl 06
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD + 0.3V.
Capacitance(1)(TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2 )
Max. Unit
CIN
VIN = 3dV
9
pF
COUT
VOUT = 3dV
10
pF
5669 tbl 07
NOTES:
1. This parameter is determined by device characteristics but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V .
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V16/5S
70V16/5L
Symbol
|ILI|
Parameter
Test Conditions
Min.
Max.
10
Min.
Max.
5
Unit
µA
µA
V
(1)
___
___
___
___
___
___
Input Leakage Current
VDD = 3.6V, VIN = 0V to VDD
(1)
|ILO|
Output Leakage Currentt
Output Low Voltage
Output High Voltage
IH OUT
o
10
5
CE = V , V = 0V t VDD
VOL
IOL = +4mA
0.4
0.4
___
___
VOH
IOH = -4mA
2.4
2.4
V
5669 tbl 08
NOTE:
1. At VDD < 2.0V, Input leakages are undefined.
6.452
P
R
E
L
I
M
I
N
A
R
Y
P
R
E
PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V ± 0.3V)
70V16/5X15
Com'l Only
70V16/5X20
Com'l
& Ind
70V16/5X25
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
DD
I
Dynamic Operating
Current
(Both Ports Active)
S
L
150
140
215
185
140
130
200
175
130
125
190
165
mA
CE = VIL, Outputs Disabled
SEM = VIH
(3)
f = fMAX
____
____
____
____
____
____
____
____
IND
S
L
140
130
225
195
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
25
20
35
30
20
15
30
25
16
13
30
25
mA
mA
mA
mA
CER and CEL = VIH
SEMR = SEML = VIH
(3)
f = fMAX
____
____
____
____
____
____
____
____
MIL &
IND
S
L
20
15
45
40
(5)
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
85
80
120
110
80
75
110
100
75
72
110
95
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
____
____
____
____
____
____
____
____
MIL &
IND
S
L
80
75
130
115
SEMR = SEML = VIH
Full Standby Current
Both Ports CEL and
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
DD
(Both Ports
-
CER > V - 0.2V,
DD
CMOS Level Inputs)
VIN > V - 0.2V or
____
____
____
____
____
____
____
____
VIN < 0.2V, f = 0(4)
SEMR = SEML > V - 0.2V
MIL &
IND
S
L
1.0
0.2
15
5
DD
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
S
L
85
80
125
105
80
75
115
100
75
70
105
90
CE"A" < 0.2V and
(5)
DD
CE"B" > V - 0.2V
DD
SEMR = SEML > V - 0.2V
____
____
____
____
DD
MIL &
IND
S
L
80
75
130
115
VIN > V - 0.2V or VIN < 0.2V
____
____
____
____
Active Port Outputs Disabled,
(3)
f = fMAX
5669 tbl 09
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 115mA (typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
Output Loads and AC Test
Conditions
3.3V
3.3V
Input Pulse Levels
GND to 3.0V
3ns Max.
1.5V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
590Ω
590Ω
DATAOUT
BUSY
INT
DATAOUT
1.5V
5pF*
435Ω
Figures 1 and 2
30pF
435Ω
5669 tbl 10
,
5669 drw 04
Figure 1. AC Output Test Load
Figure 2. Output Test
Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
Timing of Power-Up / Power-Down
CE
PU
t
tPD
ICC
50%
50%
ISB
,
5669 drw 07
6
6.42
E
L
I
M
I
N
A
R
Y
IDT70V16/5S/L
PRELIMINARY
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
70V16/5X15
Com'l Only
70V16/5X20
Com'l
& Ind
70V16/5X25
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
tRC
Read Cycle Time
15
20
25
ns
ns
ns
____
____
____
tAA
tACE
Address Access Time
15
15
15
20
20
20
25
25
25
____
____
____
____
____
____
____
____
____
Chip Enable Access Time(3)
Byte Enable Access Time(3)
ABE
t
ns
ns
ns
ns
ns
ns
ns
ns
Output Enable Access Time(3)
tAOE
tOH
tLZ
10
12
13
____
____
____
Output Hold from Address Change
3
3
3
Output Low-Z Time(1,2)
____
____
____
3
3
3
____
____
____
Output High-Z Time(1,2)
tHZ
10
12
15
____
____
____
Chip Enable to Power Up Time(1,2)
tPU
tPD
tSOP
tSAA
0
0
0
____
____
____
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access(3)
15
20
25
____
____
____
10
10
10
____
____
____
15
20
25
ns
5669 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
Waveform of Read Cycles(5)
tRC
ADDR
(4)
tAA
(4)
tACE
CE
(4)
tAOE
OE
R/W
(1)
tLZ
t
OH
(4)
DATAOUT
VALID DATA
(2)
tHZ
BUSYOUT
5669 drw 06
(3,4)
tBDD
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.472
P
R
E
L
I
M
I
N
A
R
Y
P
R
E
PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
70V16/5X15
Com'l Only
70V16/5X20
Com'l
& Ind
70V16/5X25
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time
15
12
12
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
tWP
12
0
15
0
20
0
tWR
tDW
tHZ
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
10
15
15
____
____
____
10
12
15
____
____
____
tDH
0
0
0
____
____
____
(1,2)
tWZ
tOW
tSWRD
tSPS
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
12
15
____
____
____
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
ns
5669 tbl 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but not production tested.
3. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltageand temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
8
6.42
E
L
I
M
I
N
A
R
Y
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
tAW
CE or SEM(9)
(3)
(2)
(6)
tWR
tAS
tWP
R/W
(7)
tLZ
tOW
tWZ
(4)
(4)
OUT
DATA
tDW
tDH
DATAIN
5669 drw 08
Timing Waveform of Write Cycle No. 2,CE Controlled Timing(1,5)
t
WC
ADDRESS
or
t
AW
CE
SEM(9)
(6)
tAS
(3)
(2)
tWR
tEW
R/
W
tDW
tDH
DATAIN
5669 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.492
P
R
E
L
I
M
I
N
A
R
Y
P
R
E
PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
VALID ADDRESS
VALID ADDRESS
A0-A2
SEM
I/O
tWR
tAW
tACE
tEW
tWP
tOH
tDW
DATAIN
VALID
tSOP
DATAOUT
VALID(2)
tAS
tDH
R/W
tAOE
tSWRD
OE
Read Cycle
Write Cycle
5669 drw 10
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O8) equal to the semaphore value.
Timing Waveform of Semaphore Write Condition(1,3,4)
A0"A"-A2 "A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2 "B"
R/W"B"
MATCH
SIDE(2)
"B"
SEM"B"
5669 drw 11
NOTES:
1. DOR = DOL =VIH, CER = CEL =VIH.
2. All timing is the same for left and right ports. Port“A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
10
6.42
E
L
I
M
I
N
A
R
Y
IDT70V16/5S/L
PRELIMINARY
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6)
70V16/5X15
Com'l Ony
70V16/5X20
Com'l
& Ind
70V16/5X25
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
____
____
____
____
____
____
____
____
____
____
____
____
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
15
15
15
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
Access Time from Chip Enable LOW
BUSY
15
17
17
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
____
____
____
5
5
5
____
____
____
18
30
30
Write Hold After BUSY(5)
12
15
17
____
____
____
BUSY TIMING (M/S = VIL)
____
____
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
PORT-TO-PORT DELAY TIMING
tWB
0
0
0
ns
ns
tWH
12
15
17
(1)
____
____
____
____
____
____
tWDD
tDDD
Write Pulse to Data Delay
30
25
45
35
50
35
ns
Write Data Valid to Read Data Delay(1)
ns
5669 tbl 13
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' in part numbers indicates power rating (S or L).
Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH)
tWC
MATCH
ADDR"A"
R/W"A"
tWP
tDH
tDW
VALID
DATAIN "A"
(1)
tAPS
MATCH
tWDD
ADDR"B"
tBDD
tBDA
BUSY"B"
DATAOUT "B"
VALID
(3)
tDDD
NOTES:
5669 drw 12
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL.
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S=VIL (SLAVE), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
6.1412
P
R
E
L
I
M
I
N
A
R
Y
P
R
E
PRELIMINARY
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY(3)
tWP
R/W"A"
tWB
BUSY"B"
(1)
tWH
R/W"B"
(2)
5669 drw 13
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
(2)
tAPS
CE"B"
tBAC
t
BDC
BUSY"B"
5669 drw 14
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDR"B"
BUSY"B"
ADDRESS "N"
(2)
tAPS
MATCHING ADDRESS "N"
tBAA
tBDA
5669 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
12
6.42
E
L
I
M
I
N
A
R
Y
IDT70V16/5S/L
PRELIMINARY
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
70V16/5X15
Com'l Only
70V16/5X20
Com'l
& Ind
70V16/5X25
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
t
AS
WR
IN S
IN R
Addre ss Se t-up Time
Write Re covery Time
Interrupt Set Time
0
0
0
ns
ns
ns
t
0
0
0
____
____
____
t
15
15
20
20
20
20
____
____
____
t
Inte rrupt Re se t Time
ns
5669 tbl 14
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
Waveform of Interrupt Timing(1)
tWC
INTERRUPT SET ADDRESS (2)
ADDR"A"
(4)
(3)
tWR
tAS
CE"A"
R/
W"A"
(3)
tINS
INT"B"
5669 drw 16
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
tAS
OE"B"
(3)
tINR
INT"B"
5669 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.1432
P
R
E
L
I
M
I
N
A
R
Y
P
R
E
PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Truth Table III Interrupt ꢀlag(1)
Left Port
Right Port
WL
R/
WR
R/
A13L-A0L
3FFF(4)
X
A13R-A0R
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
CEL
L
OEL
X
INTL
X
CER
OER
X
INTR
(2)
L
X
X
X
X
X
L
X
L
L
X
L
(3)
X
X
X
L
3FFF(4)
3FFE(4)
X
H
(3)
X
X
X
L
X
X
X
(2)
L
L
3FFE(4)
H
X
X
Reset Left INTL Flag
5669 tbl 15
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. A13 is a NC for IDT70V15, therefore Interrupt Addresses are 1FFF and 1FFE.
Truth Table IV Address BUSY
Arbitration
Inputs
Outputs
AOL-A13L
AOR-A13R
(1)
(1)
Function
Normal
Normal
Normal
CEL
X
CER
X
BUSYL
BUSYR
NO MATCH
MATCH
H
H
H
H
H
X
X
H
MATCH
H
H
(3)
L
L
MATCH
(2)
(2)
Write Inhibit
5669 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the
IDT70V16/5 are push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. A13 a NC for IDT70V15, Address comparison will be for A0 - A12.
Truth Table V Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D8 Left
D0 - D8 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
NOTES:
Left port has semaphore token
Semaphore free
5669 tbl 17
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V16/5.
2. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0 - I/O8). These eight semaphores are addressed by A0 - A2.
e. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Truth Table.
14
6.42
E
L
I
M
I
N
A
R
Y
IDT70V16/5S/L
PRELIMINARY
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
CE
MASTER
Dual Port
RAM
CE
SLAVE
Dual Port
RAM
BUSY (R)
(L)
BUSY
(L)
(R)
BUSY
BUSY
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
CE
CE
(L)
BUSY (R)
(R)
BUSY
(L)
BUSY
BUSY (R)
BUSY
(L)
BUSY
5669 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V16/5 RAMs.
ꢀunctionalDescription
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT70V16/5 RAM in master mode, are
push-pulltypeoutputs anddonotrequirepullupresistors tooperate.If
theseRAMsarebeingexpandedindepth,thentheBUSYindicationfor
the resulting array requires the use of an external AND gate.
TheIDT70V16/5provides twoports withseparatecontrol,address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V16/5 has an automatic power down
featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry
thatpermitstherespectiveporttogointoastandbymodewhennotselected
(CE HIGH).Whenaportis enabled,access totheentirememoryarray
ispermitted.
WidthExpansionBusyLogic
Master/SlaveArrays
Interrupts
When expanding an IDT70V16/5 RAM array in width while using
BUSYlogic,onemasterpartisusedtodecidewhichsideoftheRAMarray
willreceiveaBUSYindication,andtooutputthatindication.Anynumber
ofslavestobeaddressedinthesameaddressrangeasthemasteruse
theBUSYsignalasawriteinhibitsignal.ThusontheIDT70V16/5RAM
theBUSYpinisanoutputifthepartisusedasamaster(M/Spin=H),and
theBUSYpinisaninputifthepartusedasaslave(M/Spin=L)asshown
in Figure 3.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. Itignores whetheranaccess is a readorwrite. In
a master/slave array, bothaddress andchipenable mustbe validlong
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwiththeR/Wsignal.Failuretoobservethistimingcan
resultina glitchedinternalwrite inhibitsignalandcorrupteddata inthe
slave.
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessagecenter)is assignedtoeachport. Theleftportinterruptflag
(INTL) is asserted when the right port writes to memory location 3FFE
where a write is defined as the CE = R/W= VIL per Truth Table III. The
leftportclearstheinterruptbyanaddresslocation3FFEaccesswhenCER
=OER =VIL, R/W is a "don't care". Likewise, the right port interrupt flag
(INTR) is asserted when the left port writes to memory location 3FFF
(1FFFforIDT70V15)andtocleartheinterruptflag(INTR),therightport
must access location 3FFF.Themessage(9bits)at3FFEor3FFF(1FFE
or1FFFforIDT70V15)isuser-definedsinceitisinanaddressableSRAM
location.If the interrupt functionisnotused,addresslocations3FFEand
3FFF (1FFE and 1FFF for IDT70V15) are not used as mail boxes but
arestill partoftherandomaccessmemory.RefertoTruthTableIIIforthe
interruptoperation.
BusyLogic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
anduse anyBUSYindicationas aninterruptsource toflagthe eventof
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
Semaphores
TheIDT70V16/5areextremelyfastDual-Port16/8Kx9StaticRAMs
withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.
TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port
RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby
thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe
usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe
Dual-Port RAM or any other shared resource.
The Dual-PortRAMfeatures a fastaccess time, andbothports are
6.1452
P
R
E
L
I
M
I
N
A
R
Y
P
R
E
PRELIMINARY
Industrial and Commercial Temperature Ranges
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
completelyindependentofeachother.Thismeansthattheactivityonthe
leftportinnowayslows theaccess timeoftherightport.Bothports are
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM
enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol
on-chippowerdowncircuitrythatpermits the respective porttogointo
standbymodewhennotselected. Thisistheconditionwhichisshownin
Truth Table I where CE and SEM are both HIGH.
SystemswhichcanbestusetheIDT70V16/5containmultipleproces-
sorsorcontrollersandaretypicallyveryhigh-speedsystemswhichare
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
a performance increase offered by the IDT70V16/5's hardware sema-
phores,whichprovidealockoutmechanismwithoutrequiringcomplex
programming.
throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof
theotheraddresspinshasanyeffect.
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
on that side and a one on the other side (see Truth Table V). That
semaphorecannowonlybemodifiedbythesideshowingthezero.When
aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
settoaoneforbothsides(unlessasemaphorerequestfromtheotherside
ispending)andthencanbewrittentobybothsides.Thefactthattheside
which is able to write a zero into a semaphore subsequently locks out
writes from the other side is what makes semaphore flags useful in
interprocessorcommunications.(Athoroughdiscussionontheuseofthis
featurefollowsshortly.)Azerowrittenintothesamelocationfromtheother
side willbe storedinthe semaphore requestlatchforthatside untilthe
semaphoreisfreedbythefirstside.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
signalsgoactive.Thisservestodisallowthesemaphorefromchanging
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
cause either signal (SEM or OE) to go inactive or the output will never
change.
Softwarehandshakingbetweenprocessors offers themaximumin
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations. The IDT70V16/5 does not use its semaphore flags to
control any resources through hardware, thus allowing the system
designertotalflexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methodsofhardwarearbitrationisthatwaitstatesareneverincurredin
either processor. This can prove to be a major advantage in very high-
speedsystems.
AsequenceWRITE/READmustbeusedbythesemaphoreinorder
to guarantee that no system level contention will occur. A processor
requestsaccesstosharedresourcesbyattemptingtowriteazerointoa
semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore
requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,
afactwhichtheprocessorwillverifybythesubsequentread(seeTruth
TableV).Asanexample,assumeaprocessorwritesazerototheleftport
atafreesemaphorelocation.Onasubsequentread,theprocessorwill
verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol
overtheresourceinquestion.Meanwhile,ifaprocessorontherightside
attempts towriteazerotothesamesemaphoreflagitwillfail,as willbe
verifiedbythefactthataonewillbereadfromthatsemaphoreontheright
side during subsequent read. Had a sequence of READ/WRITE been
used instead,systemcontentionproblemscouldhaveoccurredduring
the gap between the read and write cycles.
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation.The
reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch
havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
overtotheothersideassoonasaoneiswrittenintothefirstside’srequest
latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest
latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
is requestedandthe processorwhichrequesteditnolongerneeds the
resource, the entire system can hang up until a one is written into that
semaphorerequestlatch.
How the Semaphore ꢀlags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
processorwantstousethisresource,itrequeststhetokenbysettingthe
latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
it. If it was successful, it proceeds to assume control over the shared
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe
sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest
that semaphore’s status or remove its request for that semaphore to
performanothertaskandoccasionallyattemptagaintogaincontrolofthe
tokenviathesetandtestsequence.Oncetherightsidehasrelinquished
thetoken,theleftsideshouldsucceedingainingcontrol.
ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting
azerointoasemaphorelatchandisreleasedwhenthesamesidewrites
aonetothatlatch.
TheeightsemaphoreflagsresidewithintheIDT70V16/5inaseparate
memoryspacefromtheDual-PortRAM.This addressspaceisaccessed
byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe
semaphore flags) and using the other control pins (Address, OE, and
R/W)as theywouldbe usedinaccessinga standardstaticRAM. Each
oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside
The criticalcase ofsemaphore timingis whenbothsides requesta
single token by attempting to write a zero into it at the same time. The
16
6.42
E
L
I
M
I
N
A
R
Y
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta- control,itwouldlockouttheleftside.
neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives
Once the left side was finished with its task, it would write a one to
thetoken.Ifonesideisearlierthantheotherinmakingtherequest,thefirst Semaphore 0 and may then try to gain access to Semaphore 1. If
sidetomaketherequestwillreceivethetoken.Ifbothrequestsarriveat Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo
thesametime,theassignmentwillbearbitrarilymadetooneportorthe itssemaphorerequestandperformothertasksuntilitwasabletowrite,then
other.
readazerointoSemaphore1.Iftherightprocessorperformsasimilartask
One caution that should be noted when using semaphores is that withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap
semaphoresalonedonotguaranteethataccesstoaresourceissecure. 8Kblocks ofDual-PortRAMwitheachother.
Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused
ormisinterpreted, a software errorcaneasilyhappen.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
Initializationofthesemaphoresisnotautomaticandmustbehandled semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual-
viatheinitializationprogramatpower-up.Sinceanysemaphorerequest PortRAMorothersharedresources intoeightparts. Semaphores can
flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing
sidesshouldhaveaonewrittenintothematinitializationfrombothsides given a common meaning as was shown in the example above.
to assure that they will be free when needed.
Semaphores are a useful form of arbitration in systems like disk
interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring
atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse
ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea
was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess
theirassignedportionsofmemorycontinuouslywithoutanywaitstates.
Semaphoresarealsousefulinapplicationswherenomemory“WAIT”
stateisavailableononeorbothsides.Onceasemaphorehandshakehas
been performed, both processors can access their assigned RAM
segmentsatfullspeed.
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor
mayberesponsibleforbuildingandupdatingadatastructure.Theother
processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting
processorreadsanincompletedatastructure,amajorerrorconditionmay
exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo
differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks
itandthenisabletogoinandupdatethedatastructure.Whentheupdate
is completed, the data structure block is released. This allows the
interpretingprocessortocomebackandreadthecompletedatastructure,
therebyguaranteeingaconsistentdatastructure.
UsingSemaphoresSomeExamples
Perhapsthesimplestapplicationofsemaphoresistheirapplicationas
resource markers forthe IDT70V16/5’s Dual-PortRAM. Saythe 16Kx
9RAMwastobedividedintotwo8Kx9blockswhichweretobededicated
atanyonetimetoservicingeithertheleftorrightport.Semaphore0could
be used to indicate the side which would control the lower section of
memory,andSemaphore1couldbedefinedastheindicatorfortheupper
sectionofmemory.
Totakearesource,inthis examplethelower8KofDual-PortRAM,
the processor on the left port could write and then read a zero in to
Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread
backratherthana one), the leftprocessorwouldassume controlofthe
lower8K.Meanwhiletherightprocessorwasattemptingtogaincontrolof
theresourceaftertheleftprocessor,itwouldreadbackaoneinresponse
tothezeroithadattemptedtowriteintoSemaphore0.Atthis point,the
softwarecouldchoosetotryandgaincontrolofthesecond8Ksectionby
writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
5669 drw 19
Figure 4. IDT70V16/5 Semaphore Logic
6.1472
P
R
E
L
I
M
I
N
A
R
Y
P
R
E
PRELIMINARY
IDT70V16/5S/L
High-Speed 3.3V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I(1)
PF
J
80-pin TQFP (PN80-1)
68-pin PLCC (J68-1)
15
20
25
Commercial Only
Commercial & Industrial
Commercial Only
Speed in Nanoseconds
S
L
Standard Power
Low Power
70V16 144K (16K x 9-Bit) 2.5V Dual-Port RAM
70V15
72K (8K x 9-Bit) 2.5V Dual-Port RAM
5669 drw 20
NOTE:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
DatasheetDocumentHistory
08/26/02:
InitialPublicRelease
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975StenderWay
Santa Clara, CA 95054
800-345-7015 or 408-727-6116
fax: 408-492-8674
831-754-4613
DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
18
6.42
相关型号：
IDT70V15S20JG
Dual-Port SRAM, 8KX9, 20ns, CMOS, PQCC68, 0.95 X 0.95 INCH, 0.17 INCH HEIGHT, PLASTIC, LCC-68
IDT
IDT70V15S20JGI
Dual-Port SRAM, 8KX9, 20ns, CMOS, PQCC68, 0.95 X 0.95 INCH, 0.17 INCH HEIGHT, PLASTIC, LCC-68
IDT
IDT70V15S25JG
Dual-Port SRAM, 8KX9, 25ns, CMOS, PQCC68, 0.95 X 0.95 INCH, 0.17 INCH HEIGHT, PLASTIC, LCC-68
IDT
©2020 ICPDF网 联系我们和版权申明